1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PCISCH_H 27 #define _SYS_PCISCH_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 /* 34 * Performance counters information. 35 */ 36 #define SCHIZO_SHIFT_PIC0 4 37 #define SCHIZO_SHIFT_PIC1 11 38 39 /* 40 * Schizo-specific register offsets & bit field positions. 41 */ 42 43 /* 44 * [msb] [lsb] 45 * 0x00 <chip_type> <version#> <module-revision#> 46 */ 47 #define SCHIZO_VER_10 CHIP_ID(PCI_CHIP_SCHIZO, 0x00, 0x00) 48 #define SCHIZO_VER_20 CHIP_ID(PCI_CHIP_SCHIZO, 0x02, 0x00) 49 #define SCHIZO_VER_21 CHIP_ID(PCI_CHIP_SCHIZO, 0x03, 0x00) 50 #define SCHIZO_VER_22 CHIP_ID(PCI_CHIP_SCHIZO, 0x04, 0x00) 51 #define SCHIZO_VER_23 CHIP_ID(PCI_CHIP_SCHIZO, 0x05, 0x00) 52 #define SCHIZO_VER_24 CHIP_ID(PCI_CHIP_SCHIZO, 0x06, 0x00) 53 #define SCHIZO_VER_25 CHIP_ID(PCI_CHIP_SCHIZO, 0x07, 0x00) 54 #define XMITS_VER_10 CHIP_ID(PCI_CHIP_XMITS, 0x05, 0x01) 55 #define XMITS_VER_21 CHIP_ID(PCI_CHIP_XMITS, 0x05, 0x03) 56 #define XMITS_VER_30 CHIP_ID(PCI_CHIP_XMITS, 0x05, 0x04) 57 #define TOMATILLO_VER_10 CHIP_ID(PCI_CHIP_TOMATILLO, 0x00, 0x00) 58 #define TOMATILLO_VER_20 CHIP_ID(PCI_CHIP_TOMATILLO, 0x01, 0x00) 59 #define TOMATILLO_VER_21 CHIP_ID(PCI_CHIP_TOMATILLO, 0x02, 0x00) 60 #define TOMATILLO_VER_22 CHIP_ID(PCI_CHIP_TOMATILLO, 0x03, 0x00) 61 #define TOMATILLO_VER_23 CHIP_ID(PCI_CHIP_TOMATILLO, 0x04, 0x00) 62 #define TOMATILLO_VER_24 CHIP_ID(PCI_CHIP_TOMATILLO, 0X05, 0X00) 63 64 /* 65 * Offsets of Control Block registers ("reg" property 2nd entry) 66 */ 67 #define SCHIZO_CB_CSR_OFFSET 0x0 /* reg 1 */ 68 #define SCHIZO_CB_ERRCTRL_OFFSET 0x8 69 #define SCHIZO_CB_INTCTRL_OFFSET 0x10 70 #define SCHIZO_CB_ERRLOG_OFFSET 0x18 71 #define SCHIZO_CB_ECCCTRL_OFFSET 0x20 72 #define SCHIZO_CB_UEAFSR_OFFSET 0x30 73 #define SCHIZO_CB_UEAFAR_OFFSET 0x38 74 #define SCHIZO_CB_CEAFSR_OFFSET 0x40 75 #define SCHIZO_CB_CEAFAR_OFFSET 0x48 76 #define SCHIZO_CB_ESTRCTRL_OFFSET 0x50 77 #define XMITS_CB_SOFT_PAUSE_OFFSET 0x58 78 #define XMITS_CB_IO_LOOPBACK_CONTROL_OFFSET 0x60 79 #define XMITS_CB_SAF_PED_CONTROL_OFFSET 0x68 80 #define XMITS_CB_SAF_PED_LOG_OFFSET 0x70 81 #define XMITS_CB_SAF_PAR_INJECT_IMM_OFFSET 0x78 82 #define XMITS_CB_SAF_PAR_INJECT_1_OFFSET 0x80 83 #define XMITS_CB_SAF_PAR_INJECT_0_OFFSET 0x88 84 #define XMITS_CB_FIRST_ERROR_LOG 0x90 85 #define XMITS_CB_FIRST_ERROR_ADDR 0x98 86 #define XMITS_CB_PCI_LEAF_STATUS 0xA0 87 88 /* 89 * Tomatillo only bits in IOMMU control registers. 90 */ 91 #define TOMATILLO_IOMMU_SEG_DISP_SHIFT 4 92 #define TOMATILLO_IOMMU_TSB_MAX 7 93 #define TOMATIILO_IOMMU_ERR_REG_SHIFT 24 94 #define TOMATILLO_IOMMU_ERRSTS_SHIFT 25 95 #define TOMATILLO_IOMMU_ERR (1ull << 24) 96 #define TOMATILLO_IOMMU_ERRSTS (3ull << 25) 97 #define TOMATILLO_IOMMU_ERR_ILLTSBTBW (1ull << 27) 98 #define TOMATILLO_IOMMU_ERR_BAD_VA (1ull << 28) 99 100 #define TOMATILLO_IOMMU_PROTECTION_ERR 0x0 101 #define TOMATILLO_IOMMU_INVALID_ERR 0x1 102 #define TOMATILLO_IOMMU_TIMEOUT_ERR 0x2 103 #define TOMATILLO_IOMMU_ECC_ERR 0x3 104 105 /* 106 * Offsets of performance monitoring registers. 107 */ 108 #define SCHIZO_PERF_PCI_PCR_OFFSET 0x00000100 109 #define SCHIZO_PERF_PCI_PIC_OFFSET 0x00000108 110 #define SCHIZO_PERF_PCI_ICD_OFFSET 0x00000110 111 #define SCHIZO_PERF_SAF_PCR_OFFSET 0x00007000 112 #define SCHIZO_PERF_SAF_PIC_OFFSET 0x00007008 113 114 /* 115 * Offsets of registers in the PBM block: 116 */ 117 #define SCHIZO_PCI_CTRL_REG_OFFSET 0x2000 118 #define SCHIZO_PCI_ASYNC_FLT_STATUS_REG_OFFSET 0x2010 119 #define SCHIZO_PCI_ASYNC_FLT_ADDR_REG_OFFSET 0x2018 120 #define SCHIZO_PCI_DIAG_REG_OFFSET 0x2020 121 #define SCHIZO_PCI_ESTAR_REG_OFFSET 0x2028 122 #define TOMATILLO_TGT_ADDR_SPACE_OFFSET 0x2490 123 #define TOMATILLO_TGT_ERR_VALOG_OFFSET 0x2498 124 125 #define XMITS10_PCI_X_ERROR_STATUS_REG_OFFSET 0x2030 126 #define XMITS10_PCI_X_DIAG_REG_OFFSET 0x2038 127 #define XMITS_PCI_X_ERROR_STATUS_REG_OFFSET 0x2300 128 #define XMITS_PCI_X_DIAG_REG_OFFSET 0x2308 129 #define XMITS_PARITY_DETECT_REG_OFFSET 0x2040 130 #define XMITS_PARITY_LOG_REG_OFFSET 0x2048 131 #define XMITS_PARITY_INJECT_REG_OFFSET 0x2050 132 #define XMITS_PARITY_INJECT_1_REG_OFFSET 0x2058 133 #define XMITS_PARITY_INJECT_0_REG_OFFSET 0x2060 134 #define XMITS_UPPER_RETRY_COUNTER_REG_OFFSET 0x2310 135 136 /* 137 * Offsets of IO Cache Registers: 138 */ 139 #define TOMATILLO_IOC_CSR_OFF 0x2248 140 #define TOMATILLO_IOC_TAG_OFF 0x2250 141 #define TOMATIILO_IOC_DAT_OFF 0x2290 142 143 /* 144 * Offsets of registers in the iommu block: 145 */ 146 #define SCHIZO_IOMMU_FLUSH_CTX_REG_OFFSET 0x00000218 147 #define TOMATILLO_IOMMU_ERR_TFAR_OFFSET 0x0220 148 149 /* 150 * Offsets of registers in the streaming cache block: 151 */ 152 #define SCHIZO_SC_CTRL_REG_OFFSET 0x00002800 153 #define SCHIZO_SC_INVL_REG_OFFSET 0x00002808 154 #define SCHIZO_SC_SYNC_REG_OFFSET 0x00002810 155 #define SCHIZO_SC_CTX_INVL_REG_OFFSET 0x00002818 156 #define SCHIZO_SC_CTX_MATCH_REG_OFFSET 0x00010000 157 #define SCHIZO_SC_DATA_DIAG_OFFSET 0x0000b000 158 #define SCHIZO_SC_TAG_DIAG_OFFSET 0x0000ba00 159 #define SCHIZO_SC_LTAG_DIAG_OFFSET 0x0000bb00 160 161 /* 162 * MAX_PRF when enabled will always prefetch the max of 8 163 * prefetches if possible. 164 */ 165 #define XMITS_SC_MAX_PRF (0x1ull << 7) 166 167 /* 168 * Offsets of registers in the PCI Idle Check Diagnostics Register. 169 */ 170 #define SCHIZO_PERF_PCI_ICD_DMAW_PARITY_INT_ENABLE 0x4000 171 #define SCHIZO_PERF_PCI_ICD_PCI_2_0_COMPATIBLE 0x8000 172 173 /* 174 * Offsets of registers in the interrupt block: 175 */ 176 #define SCHIZO_IB_SLOT_INTR_MAP_REG_OFFSET 0x1100 177 #define SCHIZO_IB_INTR_MAP_REG_OFFSET 0x1000 178 #define SCHIZO_IB_CLEAR_INTR_REG_OFFSET 0x1400 179 #define SCHIZO_PBM_DMA_SYNC_REG_OFFSET 0x1A08 180 #define PBM_DMA_SYNC_COMP_REG_OFFSET 0x1A10 181 #define PBM_DMA_SYNC_PEND_REG_OFFSET 0x1A18 182 183 /* 184 * Address space offsets and sizes: 185 */ 186 #define SCHIZO_SIZE 0x0000800000000000ull 187 188 /* 189 * Schizo-specific fields of interrupt mapping register: 190 */ 191 #define SCHIZO_INTR_MAP_REG_NID 0x0000000003E00000ull 192 #define SCHIZO_INTR_MAP_REG_NID_SHIFT 21 193 194 /* 195 * schizo ECC UE AFSR bit definitions: 196 */ 197 #define SCHIZO_ECC_UE_AFSR_ERRPNDG 0x0300000000000000ull 198 #define SCHIZO_ECC_UE_AFSR_MASK 0x000003ff00000000ull 199 #define SCHIZO_ECC_UE_AFSR_MASK_SHIFT 32 200 #define SCHIZO_ECC_UE_AFSR_QW_OFFSET 0x00000000C0000000ull 201 #define SCHIZO_ECC_UE_AFSR_QW_OFFSET_SHIFT 30 202 #define SCHIZO_ECC_UE_AFSR_AGENT_MID 0x000000001f000000ull 203 #define SCHIZO_ECC_UE_AFSR_AGENT_MID_SHIFT 24 204 #define SCHIZO_ECC_UE_AFSR_PARTIAL 0x0000000000800000ull 205 #define SCHIZO_ECC_UE_AFSR_OWNED_IN 0x0000000000400000ull 206 #define SCHIZO_ECC_UE_AFSR_MTAG_SYND 0x00000000000f0000ull 207 #define SCHIZO_ECC_UE_AFSR_MTAG_SYND_SHIFT 16 208 #define SCHIZO_ECC_UE_AFSR_MTAG 0x000000000000e000ull 209 #define SCHIZO_ECC_UE_AFSR_MTAG_SHIFT 13 210 #define SCHIZO_ECC_UE_AFSR_SYND 0x00000000000001ffull 211 #define SCHIZO_ECC_UE_AFSR_SYND_SHIFT 0 212 213 /* 214 * schizo ECC CE AFSR bit definitions: 215 */ 216 #define SCHIZO_ECC_CE_AFSR_ERRPNDG 0x0300000000000000ull 217 #define SCHIZO_ECC_CE_AFSR_MASK 0x000003ff00000000ull 218 #define SCHIZO_ECC_CE_AFSR_MASK_SHIFT 32 219 #define SCHIZO_ECC_CE_AFSR_QW_OFFSET 0x00000000C0000000ull 220 #define SCHIZO_ECC_CE_AFSR_QW_OFFSET_SHIFT 30 221 #define SCHIZO_ECC_CE_AFSR_AGENT_MID 0x000000001f000000ull 222 #define SCHIZO_ECC_CE_AFSR_AGENT_MID_SHIFT 24 223 #define SCHIZO_ECC_CE_AFSR_PARTIAL 0x0000000000800000ull 224 #define SCHIZO_ECC_CE_AFSR_OWNED_IN 0x0000000000400000ull 225 #define SCHIZO_ECC_CE_AFSR_MTAG_SYND 0x00000000000f0000ull 226 #define SCHIZO_ECC_CE_AFSR_MTAG_SYND_SHIFT 16 227 #define SCHIZO_ECC_CE_AFSR_MTAG 0x000000000000e000ull 228 #define SCHIZO_ECC_CE_AFSR_MTAG_SHIFT 13 229 #define SCHIZO_ECC_CE_AFSR_SYND 0x00000000000001ffull 230 #define SCHIZO_ECC_CE_AFSR_SYND_SHIFT 0 231 232 /* 233 * schizo ECC UE/CE AFAR bit definitions: 234 */ 235 #define SCHIZO_ECC_AFAR_IO_TXN 0x0000080000000000ull 236 #define SCHIZO_ECC_AFAR_PIOW_MASK 0x0000078000000000ull 237 #define SCHIZO_ECC_AFAR_PIOW_UPA64S 0x0000078000000000ull 238 #define SCHIZO_ECC_AFAR_PIOW_NL_REG 0x0000040000000000ull 239 #define SCHIZO_ECC_AFAR_PIOW_NL 0x0000050000000000ull 240 #define SCHIZO_ECC_AFAR_PIOW_NL_ALT 0x0000051000000000ull 241 #define SCHIZO_ECC_AFAR_PIOW_PCIA_REG 0x0000020000000000ull 242 #define SCHIZO_ECC_AFAR_PIOW_PCIA_MEM 0x0000030000000000ull 243 #define SCHIZO_ECC_AFAR_PIOW_PCIA_CFGIO 0x0000031000000000ull 244 #define SCHIZO_ECC_AFAR_PIOW_PCIB_REG 0x0000000000000000ull 245 #define SCHIZO_ECC_AFAR_PIOW_PCIB_MEM 0x0000010000000000ull 246 #define SCHIZO_ECC_AFAR_PIOW_PCIB_CFGIO 0x0000011000000000ull 247 #define SCHIZO_ECC_AFAR_PIOW_SAFARI_REGS 0x0000060000000000ull 248 #define SCHIZO_ECC_AFAR_PIOW_ADDR_MASK 0x0000000fffffffffull 249 #define SCHIZO_ECC_AFAR_ADDR_MASK 0x000007ffffffffffull 250 251 /* 252 * schizo pci control register bits: 253 */ 254 #define SCHIZO_PCI_CTRL_BUS_UNUSABLE (1ull << 63) 255 #define TOMATILLO_PCI_CTRL_PCI_DTO_ERR (1ull << 62) 256 #define TOMATILLO_PCI_CTRL_DTO_INT_EN (1ull << 61) 257 #define SCHIZO_PCI_CTRL_ERR_SLOT_LOCK (1ull << 51) 258 #define SCHIZO_PCI_CTRL_ERR_SLOT (7ull << 48) 259 #define SCHIZO_PCI_CTRL_ERR_SLOT_SHIFT 48 260 #define SCHIZO_PCI_CTRL_PCI_TTO_ERR (1ull << 38) 261 #define SCHIZO_PCI_CTRL_PCI_RTRY_ERR (1ull << 37) 262 #define SCHIZO_PCI_CTRL_PCI_MMU_ERR (1ull << 36) 263 #define TOMATILLO_PCI_CTRL_PEN_RD_MLTPL (1ull << 30) 264 #define TOMATILLO_PCI_CTRL_PEN_RD_ONE (1ull << 29) 265 #define TOMATILLO_PCI_CTRL_PEN_RD_LINE (1ull << 28) 266 #define TOMATILLO_PCI_CTRL_FRC_TRGT_ABRT (1ull << 27) 267 #define TOMATILLO_PCI_CTRL_FRC_TRGT_RTRY (1ull << 26) 268 #define SCHIZO_PCI_CTRL_PTO (3ull << 24) 269 #define SCHIZO_PCI_CTRL_PTO_SHIFT 24 270 #define TOMATILLO_PCI_CTRL_TRGT_RW_STL_WT (3ull << 21) 271 #define TOMATILLO_PCI_CTRL_TRGT_RW_STL_WT_SHIFT 21 272 #define SCHIZO_PCI_CTRL_MMU_INT_EN (1ull << 19) 273 #define SCHIZO_PCI_CTRL_SBH_INT_EN (1ull << 18) 274 #define SCHIZO_PCI_CTRL_ERR_INT_EN (1ull << 17) 275 #define SCHIZO_PCI_CTRL_ARB_PARK (1ull << 16) 276 #define SCHIZO_PCI_CTRL_RST (1ull << 8) 277 #define SCHIZO_PCI_CTRL_ARB_EN_MASK 0xffull 278 279 #define XMITS10_PCI_CTRL_ARB_EN_MASK 0x0full 280 #define XMITS_PCI_CTRL_X_MODE (0x1ull << 32) 281 #define XMITS_PCI_CTRL_X_ERRINT_EN (0x1ull << 20) 282 #define XMITS_PCI_CTRL_DMA_WR_PERR (0x1ull << 51) 283 284 /* 285 * schizo PCI asynchronous fault status register bit definitions: 286 */ 287 #define SCHIZO_PCI_AFSR_PE_SHIFT 58 288 #define SCHIZO_PCI_AFSR_SE_SHIFT 52 289 #define SCHIZO_PCI_AFSR_E_MA 0x0000000000000020ull 290 #define SCHIZO_PCI_AFSR_E_TA 0x0000000000000010ull 291 #define SCHIZO_PCI_AFSR_E_RTRY 0x0000000000000008ull 292 #define SCHIZO_PCI_AFSR_E_PERR 0x0000000000000004ull 293 #define SCHIZO_PCI_AFSR_E_TTO 0x0000000000000002ull 294 #define SCHIZO_PCI_AFSR_E_UNUSABLE 0x0000000000000001ull 295 #define SCHIZO_PCI_AFSR_E_MASK 0x000000000000003full 296 #define SCHIZO_PCI_AFSR_DWORDMASK 0x0000030000000000ull 297 #define SCHIZO_PCI_AFSR_DWORDMASK_SHIFT 40 298 #define SCHIZO_PCI_AFSR_BYTEMASK 0x000000ff00000000ull 299 #define SCHIZO_PCI_AFSR_BYTEMASK_SHIFT 32 300 #define SCHIZO_PCI_AFSR_BLK 0x0000000080000000ull 301 #define SCHIZO_PCI_AFSR_CONF_SPACE 0x0000000040000000ull 302 #define SCHIZO_PCI_AFSR_MEM_SPACE 0x0000000020000000ull 303 #define SCHIZO_PCI_AFSR_IO_SPACE 0x0000000010000000ull 304 305 /* Schizo/Xmits control block Safari Error log bits */ 306 #define SCHIZO_CB_ELOG_BAD_CMD (0x1ull << 62) 307 #define SCHIZO_CB_ELOG_SSM_DIS (0x1ull << 61) 308 #define SCHIZO_CB_ELOG_BAD_CMD_PCIA (0x1ull << 60) 309 #define SCHIZO_CB_ELOG_BAD_CMD_PCIB (0x1ull << 59) 310 #define XMITS_CB_ELOG_PAR_ERR_INT_PCIB (0x1ull << 19) 311 #define XMITS_CB_ELOG_PAR_ERR_INT_PCIA (0x1ull << 18) 312 #define XMITS_CB_ELOG_PAR_ERR_INT_SAF (0x1ull << 17) 313 #define XMITS_CB_ELOG_PLL_ERR_PCIB (0x1ull << 16) 314 #define XMITS_CB_ELOG_PLL_ERR_PCIA (0x1ull << 15) 315 #define XMITS_CB_ELOG_PLL_ERR_SAF (0x1ull << 14) 316 #define SCHIZO_CB_ELOG_CPU1_PAR_SINGLE (0x1ull << 13) 317 #define SCHIZO_CB_ELOG_CPU1_PAR_BIDI (0x1ull << 12) 318 #define SCHIZO_CB_ELOG_CPU0_PAR_SINGLE (0x1ull << 11) 319 #define SCHIZO_CB_ELOG_CPU0_PAR_BIDI (0x1ull << 10) 320 #define SCHIZO_CB_ELOG_SAF_CIQ_TO (0x1ull << 9) 321 #define SCHIZO_CB_ELOG_SAF_LPQ_TO (0x1ull << 8) 322 #define SCHIZO_CB_ELOG_SAF_SFPQ_TO (0x1ull << 7) 323 #define SCHIZO_CB_ELOG_SAF_UFPQ_TO (0x1ull << 6) 324 #define SCHIZO_CB_ELOG_ADDR_PAR_ERR (0x1ull << 5) 325 #define SCHIZO_CB_ELOG_UNMAP_ERR (0x1ull << 4) 326 #define SCHIZO_CB_ELOG_BUS_ERR (0x1ull << 2) 327 #define SCHIZO_CB_ELOG_TO_ERR (0x1ull << 1) 328 #define SCHIZO_CB_ELOG_DSTAT_ERR 0x1ull 329 330 /* Used for the tomatillo micro tlb bug. errata #82 */ 331 #define SCHIZO_VPN_MASK ((1 << 19) - 1) 332 333 /* Tomatillo control block JBUS error log bits */ 334 #define TOMATILLO_CB_ELOG_SNOOP_ERR_GR (0x1ull << 21) 335 #define TOMATILLO_CB_ELOG_SNOOP_ERR_PCI (0x1ull << 20) 336 #define TOMATILLO_CB_ELOG_SNOOP_ERR_RD (0x1ull << 19) 337 #define TOMATILLO_CB_ELOG_SNOOP_ERR_RDS (0x1ull << 17) 338 #define TOMATILLO_CB_ELOG_SNOOP_ERR_RDSA (0x1ull << 16) 339 #define TOMATILLO_CB_ELOG_SNOOP_ERR_OWN (0x1ull << 15) 340 #define TOMATILLO_CB_ELOG_SNOOP_ERR_RDO (0x1ull << 14) 341 #define TOMATILLO_CB_ELOG_WR_DATA_PAR_ERR (0x1ull << 13) 342 #define TOMATILLO_CB_ELOG_CTL_PAR_ERR (0x1ull << 12) 343 #define TOMATILLO_CB_ELOG_SNOOP_ERR (0x1ull << 11) 344 #define TOMATILLO_CB_ELOG_ILL_BYTE_EN (0x1ull << 10) 345 #define TOMATILLO_CB_ELOG_ILL_COH_IN (0x1ull << 8) 346 #define TOMATILLO_CB_ELOG_RD_DATA_PAR_ERR (0x1ull << 6) 347 #define TOMATILLO_CB_ELOG_TO_EXP_ERR (0x1ull << 3) 348 349 /* Tomatillo control block JBUS control/status bits */ 350 #define TOMATILLO_CB_CSR_CTRL_PERR_GEN (0x1ull << 29) 351 352 #define XMITS_PCI_X_AFSR_P_SC_ERR (0x1ull << 51) 353 #define XMITS_PCI_X_AFSR_S_SC_ERR (0x1ull << 50) 354 355 #define XMITS_PCIX_MSG_CLASS_MASK 0xf00 356 #define XMITS_PCIX_MSG_INDEX_MASK 0xff 357 #define XMITS_PCIX_MSG_MASK \ 358 (XMITS_PCIX_MSG_CLASS_MASK | XMITS_PCIX_MSG_INDEX_MASK) 359 360 #define XMITS_PCI_X_P_MSG_SHIFT 16 361 #define XMITS_PCI_X_S_MSG_SHIFT 4 362 363 #define PBM_AFSR_TO_PRIERR(afsr) \ 364 (afsr >> SCHIZO_PCI_AFSR_PE_SHIFT & SCHIZO_PCI_AFSR_E_MASK) 365 #define PBM_AFSR_TO_SECERR(afsr) \ 366 (afsr >> SCHIZO_PCI_AFSR_SE_SHIFT & SCHIZO_PCI_AFSR_E_MASK) 367 #define PBM_AFSR_TO_BYTEMASK(afsr) \ 368 ((afsr & SCHIZO_PCI_AFSR_BYTEMASK) >> SCHIZO_PCI_AFSR_BYTEMASK_SHIFT) 369 #define PBM_AFSR_TO_DWORDMASK(afsr) \ 370 ((afsr & SCHIZO_PCI_AFSR_DWORDMASK) >> \ 371 SCHIZO_PCI_AFSR_DWORDMASK_SHIFT) 372 373 /* 374 * XMITS Upper Retry Counter Register (bits 15:0) 375 */ 376 #define XMITS_UPPER_RETRY_MASK 0xFFFF 377 378 /* 379 * XMITS PCI-X Diagnostic Register bit definitions 380 */ 381 #define XMITS_PCI_X_DIAG_DIS_FAIR (0x1ull << 19) 382 #define XMITS_PCI_X_DIAG_CRCQ_VALID (0x1ull << 18) 383 #define XMITS_PCI_X_DIAG_SRCQ_VALID_SHIFT 10 384 #define XMITS_PCI_X_DIAG_SRCQ_ONE (0x1ull << 9) 385 #define XMITS_PCI_X_DIAG_CRCQ_FLUSH (0x1ull << 8) 386 #define XMITS_PCI_X_DIAG_SRCQ_FLUSH_SHIFT 0 387 #define XMITS_PCI_X_DIAG_BUGCNTL_MASK 0xFFFF /* bits 47:32 */ 388 #define XMITS_PCI_X_DIAG_BUGCNTL_SHIFT 32 389 390 #define XMITS_PCI_X_DIAG_SRCQ_MASK 0xff 391 392 /* 393 * XMITS PCI-X Error Status Register bit definitions 394 */ 395 396 #define XMITS_PCI_X_STATUS_PE_SHIFT 58 397 #define XMITS_PCI_X_STATUS_SE_SHIFT 50 398 #define XMITS_PCI_X_STATUS_E_MASK 0x3f 399 #define XMITS_PCI_X_STATUS_PFAR_MASK 0xffffffff 400 #define XMITS_PCIX_STAT_SC_DSCRD 0x20ull 401 #define XMITS_PCIX_STAT_SC_TTO 0x10ull 402 /* 403 * As a workaround for an XMITS ASIC bug, the following PCI-X errors are 404 * assigned new bit positions within the PCI-X Error Status Register to 405 * match what is actually implemented in the XMITS ASIC: 406 * 407 * Spec New 408 * Error Bit Position Bit Position 409 * -------------------- ------------ ------------ 410 * XMITS_PCIX_STAT_SMMU 0x8ull 0x4ull 411 * XMITS_PCIX_STAT_SDSTAT 0x4ull 0x8ull 412 * XMITS_PCIX_STAT_CMMU 0x2ull 0x1ull 413 * XMITS_PCIX_STAT_CDSTAT 0x1ull 0x2ull 414 * 415 */ 416 #define XMITS_PCIX_STAT_SMMU 0x4ull 417 #define XMITS_PCIX_STAT_SDSTAT 0x8ull 418 #define XMITS_PCIX_STAT_CMMU 0x1ull 419 #define XMITS_PCIX_STAT_CDSTAT 0x2ull 420 421 #define XMITS_PCIX_STAT_SERR_ON_PERR (1ull << 32) 422 #define XMITS_PCIX_STAT_PERR_RECOV_INT_EN (1ull << 33) 423 #define XMITS_PCIX_STAT_PERR_RECOV_INT (1ull << 34) 424 425 /* 426 * PCI-X Message Classes and Indexes 427 */ 428 #define PCIX_CLASS_WRITE_COMPLETION 0x000 429 #define PCIX_WRITE_COMPLETION_NORMAL 0x00 430 431 #define PCIX_CLASS_BRIDGE 0x100 432 #define PCIX_BRIDGE_MASTER_ABORT 0x00 433 #define PCIX_BRIDGE_TARGET_ABORT 0x01 434 #define PCIX_BRIDGE_WRITE_DATA_PARITY 0x02 435 436 #define PCIX_CLASS_CPLT 0x200 437 #define PCIX_CPLT_OUT_OF_RANGE 0x00 438 #define PCIX_CPLT_SPLIT_WRITE_DATA 0x01 439 #define XMITS_CPLT_NO_ERROR 0x80 440 #define XMITS_CPLT_STREAM_DSTAT 0x81 441 #define XMITS_CPLT_STREAM_MMU 0x82 442 #define XMITS_CPLT_CONSIST_DSTAT 0x85 443 #define XMITS_CPLT_CONSIST_MMU 0x86 444 445 #define PCIX_NO_CLASS 0x999 446 #define PCIX_MULTI_ERR 1 447 #define PCIX_SINGLE_ERR 0 448 449 #define PBM_PCIX_TO_PRIERR(pcix_stat) \ 450 (pcix_stat >> XMITS_PCI_X_STATUS_PE_SHIFT & XMITS_PCI_X_STATUS_E_MASK) 451 #define PBM_PCIX_TO_SECERR(pcix_stat) \ 452 (pcix_stat >> XMITS_PCI_X_STATUS_SE_SHIFT & XMITS_PCI_X_STATUS_E_MASK) 453 #define PBM_AFSR_TO_PRISPLIT(afsr) \ 454 ((afsr >> XMITS_PCI_X_P_MSG_SHIFT) & XMITS_PCIX_MSG_MASK) 455 #define PBM_AFSR_TO_SECSPLIT(afsr) \ 456 ((afsr >> XMITS_PCI_X_S_MSG_SHIFT) & XMITS_PCIX_MSG_MASK) 457 458 #define PCIX_ERRREG_OFFSET (XMITS_PCI_X_ERROR_STATUS_REG_OFFSET -\ 459 SCHIZO_PCI_CTRL_REG_OFFSET) 460 461 /* 462 * Nested message structure to allow for storing all the PCI-X 463 * split completion messages in tabular form. 464 */ 465 typedef struct pcix_err_msg_rec { 466 uint32_t msg_key; 467 char *msg_class; 468 char *msg_str; 469 } pcix_err_msg_rec_t; 470 471 typedef struct pcix_err_tbl { 472 uint32_t err_class; 473 uint32_t err_rec_num; 474 pcix_err_msg_rec_t *err_msg_tbl; 475 } pcix_err_tbl_t; 476 477 478 /* 479 * Tomatillo IO Cache CSR bit definitions: 480 */ 481 482 #define TOMATILLO_WRT_PEN (1ull << 19) 483 #define TOMATILLO_NC_PEN_RD_MLTPL (1ull << 18) 484 #define TOMATILLO_NC_PEN_RD_ONE (1ull << 17) 485 #define TOMATILLO_NC_PEN_RD_LINE (1ull << 16) 486 #define TOMATILLO_PLEN_RD_MTLPL (3ull << 14) 487 #define TOMATILLO_PLEN_RD_ONE (3ull << 12) 488 #define TOMATILLO_PLEN_RD_LINE (3ull << 10) 489 #define TOMATILLO_POFFSET_SHIFT 3 490 #define TOMATILLO_POFFSET (0x7full << TOMATILLO_POFFSET_SHIFT) 491 #define TOMATILLO_C_PEN_RD_MLTPL (1ull << 2) 492 #define TOMATILLO_C_PEN_RD_ONE (1ull << 1) 493 #define TOMATILLO_C_PEN_RD_LINE (1ull << 0) 494 495 /* 496 * schizo PCI diagnostic register bit definitions: 497 */ 498 #define SCHIZO_PCI_DIAG_DIS_RTRY_ARB 0x0000000000000080ull 499 500 /* 501 * schizo IOMMU TLB TAG diagnostic register bits 502 */ 503 #define TLBTAG_CONTEXT_SHIFT 25 504 #define TLBTAG_ERRSTAT_SHIFT 23 505 #define TLBTAG_CONTEXT_BITS (0xffful << TLBTAG_CONTEXT_SHIFT) 506 #define TLBTAG_ERRSTAT_BITS (0x3ul << TLBTAG_ERRSTAT_SHIFT) 507 #define TLBTAG_ERR_BIT (0x1ul << 22) 508 #define TLBTAG_WRITABLE_BIT (0x1ul << 21) 509 #define TLBTAG_STREAM_BIT (0x1ul << 20) 510 #define TLBTAG_PGSIZE_BIT (0x1ul << 19) 511 #define TLBTAG_PCIVPN_BITS 0x7fffful 512 513 #define TLBTAG_ERRSTAT_PROT 0 514 #define TLBTAG_ERRSTAT_INVALID 1 515 #define TLBTAG_ERRSTAT_TIMEOUT 2 516 #define TLBTAG_ERRSTAT_ECCUE 3 517 518 /* 519 * schizo IOMMU TLB Data RAM diagnostic register bits 520 */ 521 #define TLBDATA_VALID_BIT (0x1ull << 32) 522 #define TLBDATA_CACHE_BIT (0x1ull << 30) 523 #define TLBDATA_MEMPA_BITS ((0x1ull << 30) - 1) 524 525 extern uint_t cb_buserr_intr(caddr_t a); 526 527 /* 528 * pbm_cdma_flag(schizo only): consistent dma sync handshake 529 */ 530 #define PBM_CDMA_DONE 0xcc /* arbitrary pattern set by interrupt handler */ 531 #define PBM_CDMA_PEND 0x55 /* arbitrary pattern set by sync requester */ 532 #define PBM_CDMA_INO_BASE 0x35 /* ino can be used for cdma sync */ 533 534 /* 535 * Estar control bit for schizo estar reg 536 */ 537 #define SCHIZO_PCI_CTRL_BUS_SPEED 0x0000000000000001ull 538 539 #define PCI_CMN_ID(chip_type, id) \ 540 ((chip_type) == PCI_CHIP_TOMATILLO ? ((id) >> 1) << 1 : (id)) 541 #define PCI_ID_TO_IGN(pci_id) ((pci_ign_t)((pci_id) & 0x1f)) 542 #define PCI_ID_TO_NODEID(pci_id) ((cb_nid_t)((pci_id) >> PCI_IGN_BITS)) 543 544 #define PCI_BRIDGE_TYPE(cmn_p) \ 545 (((cmn_p->pci_chip_id >> 16) == PCI_CHIP_SCHIZO) ? PCI_SCHIZO : \ 546 ((cmn_p->pci_chip_id >> 16) == PCI_CHIP_TOMATILLO) ? PCI_TOMATILLO : \ 547 ((cmn_p->pci_chip_id >> 16) == PCI_CHIP_XMITS) ? PCI_XMITS : "") 548 /* 549 * Tomatillo only 550 */ 551 #define NBIGN(ib_p) ((ib_p)->ib_ign ^ 1) 552 #define IB_INO_TO_NBMONDO(ib_p, ino) IB_IGN_TO_MONDO(NBIGN(ib_p), ino) 553 554 /* 555 * Mask to tell which PCI Side we are on 556 */ 557 #define PCI_SIDE_ADDR_MASK 0x100000ull 558 559 /* 560 * Offset from Schizo Base of Schizo CSR Base 561 */ 562 #define PBM_CTRL_OFFSET 0x410000ull 563 564 /* 565 * The following macro defines the 42-bit bus width support for SAFARI bus 566 * and JBUS in DVMA and iommu bypass transfers: 567 */ 568 569 #define SAFARI_JBUS_IOMMU_BYPASS_END 0xFFFC03FFFFFFFFFFull 570 571 #ifdef __cplusplus 572 } 573 #endif 574 575 #endif /* _SYS_PCISCH_H */ 576