1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PCI_VAR_H 27 #define _SYS_PCI_VAR_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /* 36 * The following typedef is used to represent a 37 * 1275 "reg" property of a PCI nexus. 38 */ 39 typedef struct pci_nexus_regspec { 40 uint64_t phys_addr; 41 uint64_t size; 42 } pci_nexus_regspec_t; 43 44 typedef enum { PSYCHO, SCHIZO } pci_bridge_t; 45 typedef enum { A, B } pci_side_t; 46 typedef enum { PCI_NEW, PCI_ATTACHED, PCI_DETACHED, PCI_SUSPENDED } pci_state_t; 47 typedef enum { PCI_PBM_OBJ, PCI_ECC_OBJ, PCI_CB_OBJ } pci_obj_t; 48 typedef enum { PCI_OBJ_INTR_ADD, PCI_OBJ_INTR_REMOVE } pci_obj_op_t; 49 50 #define PCI_ATTACH_RETCODE(obj, op, err) \ 51 ((err) ? (obj) << 8 | (op) << 4 | (err) & 0xf : DDI_SUCCESS) 52 53 #define PCI_OTHER_SIDE(side) ((side) ^ 1) 54 55 /* 56 * the sequence of the chip_type appearance is significant. There are code 57 * depending on it: CHIP_TYPE(pci_p) < PCI_CHIP_SCHIZO. 58 */ 59 typedef enum { 60 PCI_CHIP_UNIDENTIFIED = 0, 61 62 PCI_CHIP_PSYCHO = 1, 63 PCI_CHIP_SABRE, 64 PCI_CHIP_HUMMINGBIRD, 65 66 PCI_CHIP_SCHIZO = 0x11, 67 PCI_CHIP_XMITS, 68 PCI_CHIP_TOMATILLO 69 } pci_chip_id_t; 70 71 /* 72 * [msb] [lsb] 73 * 0x00 <chip_type> <version#> <module-revision#> 74 */ 75 #define CHIP_ID(t, v, m) (((t) << 16) | ((v) << 8) | (m)) 76 #define ID_CHIP_TYPE(id) ((id) >> 16) 77 #define PCI_CHIP_ID(pci_p) ((pci_p)->pci_common_p->pci_chip_id) 78 #define CHIP_TYPE(pci_p) ID_CHIP_TYPE(PCI_CHIP_ID(pci_p)) 79 #define CHIP_REV(pci_p) (PCI_CHIP_ID(pci_p) & 0xFF) 80 #define CHIP_VER(pci_p) ((PCI_CHIP_ID(pci_p) >> 8) & 0xFF) 81 #define CB_CHIP_TYPE(cb_p) ((cb_p)->cb_pci_cmn_p->pci_chip_id >> 16) 82 83 /* 84 * pci common soft state structure: 85 * 86 * Each psycho or schizo is represented by a pair of pci nodes in the 87 * device tree. A single pci common soft state is allocated for each 88 * pair. The UPA (Safari) bus id of the psycho (schizo) is used for 89 * the instance number. The attach routine uses the existance of a 90 * pci common soft state structure to determine if one node from the 91 * pair has been attached. 92 */ 93 struct pci_common { 94 uint_t pci_common_id; 95 96 /* pointers & counters to facilitate attach/detach & suspend/resume */ 97 ushort_t pci_common_refcnt; /* # of sides suspended + attached */ 98 ushort_t pci_common_attachcnt; /* # of sides attached */ 99 uint16_t pci_common_tsb_cookie; /* IOMMU TSB allocation */ 100 pci_t *pci_p[2]; /* pci soft states of both sides */ 101 102 uint32_t pci_chip_id; /* Bus bridge chip identification */ 103 104 /* Links to functional blocks potentially shared between pci nodes */ 105 iommu_t *pci_common_iommu_p; 106 cb_t *pci_common_cb_p; 107 ib_t *pci_common_ib_p; 108 ecc_t *pci_common_ecc_p; 109 110 /* 111 * Performance counters kstat. 112 */ 113 pci_cntr_pa_t pci_cmn_uks_pa; 114 kstat_t *pci_common_uksp; /* ptr to upstream kstat */ 115 kmutex_t pci_fm_mutex; /* per chip error handling mutex */ 116 }; 117 118 /* 119 * pci soft state structure: 120 * 121 * Each pci node has a pci soft state structure. 122 */ 123 struct pci { 124 /* 125 * State flags and mutex: 126 */ 127 pci_state_t pci_state; 128 uint_t pci_soft_state; 129 #define PCI_SOFT_STATE_OPEN 0x01 130 #define PCI_SOFT_STATE_OPEN_EXCL 0x02 131 #define PCI_SOFT_STATE_CLOSED 0x04 132 uint_t pci_open_count; 133 uint16_t pci_tsb_cookie; /* IOMMU TSB allocation */ 134 kmutex_t pci_mutex; 135 136 /* 137 * Links to other state structures: 138 */ 139 pci_common_t *pci_common_p; /* pointer common soft state */ 140 dev_info_t *pci_dip; /* devinfo structure */ 141 ib_t *pci_ib_p; /* interrupt block */ 142 cb_t *pci_cb_p; /* control block */ 143 pbm_t *pci_pbm_p; /* PBM block */ 144 iommu_t *pci_iommu_p; /* IOMMU block */ 145 sc_t *pci_sc_p; /* streaming cache block */ 146 ecc_t *pci_ecc_p; /* ECC error block */ 147 148 /* 149 * other state info: 150 */ 151 uint_t pci_id; /* UPA (or Safari) device id */ 152 pci_side_t pci_side; 153 154 /* 155 * pci device node properties: 156 */ 157 pci_bus_range_t pci_bus_range; /* "bus-range" */ 158 pci_ranges_t *pci_ranges; /* "ranges" data & length */ 159 int pci_ranges_length; 160 uint32_t *pci_inos; /* inos from "interrupts" prop */ 161 int pci_inos_len; /* "interrupts" length */ 162 int pci_numproxy; /* upa interrupt proxies */ 163 int pci_thermal_interrupt; /* node has thermal interrupt */ 164 165 /* 166 * register mapping: 167 */ 168 caddr_t pci_address[4]; 169 ddi_acc_handle_t pci_ac[4]; 170 171 /* Interrupt support */ 172 int intr_map_size; 173 struct intr_map *intr_map; 174 struct intr_map_mask *intr_map_mask; 175 176 /* performance counters */ 177 pci_cntr_addr_t pci_ks_addr; 178 kstat_t *pci_ksp; 179 180 /* Hotplug information */ 181 182 boolean_t hotplug_capable; 183 184 /* Fault Management support */ 185 int pci_fm_cap; 186 ddi_iblock_cookie_t pci_fm_ibc; 187 }; 188 189 /* 190 * PSYCHO and PBM soft state macros: 191 */ 192 #define get_pci_soft_state(i) \ 193 ((pci_t *)ddi_get_soft_state(per_pci_state, (i))) 194 195 #define alloc_pci_soft_state(i) \ 196 ddi_soft_state_zalloc(per_pci_state, (i)) 197 198 #define free_pci_soft_state(i) \ 199 ddi_soft_state_free(per_pci_state, (i)) 200 201 #define get_pci_common_soft_state(i) \ 202 ((pci_common_t *)ddi_get_soft_state(per_pci_common_state, (i))) 203 204 #define alloc_pci_common_soft_state(i) \ 205 ddi_soft_state_zalloc(per_pci_common_state, (i)) 206 207 #define free_pci_common_soft_state(i) \ 208 ddi_soft_state_free(per_pci_common_state, (i)) 209 210 #define DEV_TO_SOFTSTATE(dev) ((pci_t *)ddi_get_soft_state(per_pci_state, \ 211 PCIHP_AP_MINOR_NUM_TO_INSTANCE(getminor(dev)))) 212 213 extern void *per_pci_state; /* per-pbm soft state pointer */ 214 extern void *per_pci_common_state; /* per-psycho soft state pointer */ 215 extern kmutex_t pci_global_mutex; /* attach/detach common struct lock */ 216 extern kmutex_t dvma_active_list_mutex; 217 218 /* 219 * function prototypes for bus ops routines: 220 */ 221 extern int 222 pci_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp, 223 off_t offset, off_t len, caddr_t *addrp); 224 extern int 225 pci_dma_setup(dev_info_t *dip, dev_info_t *rdip, 226 ddi_dma_req_t *dmareq, ddi_dma_handle_t *handlep); 227 extern int 228 pci_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_attr_t *attrp, 229 int (*waitfp)(caddr_t), caddr_t arg, ddi_dma_handle_t *handlep); 230 extern int 231 pci_dma_bindhdl(dev_info_t *dip, dev_info_t *rdip, 232 ddi_dma_handle_t handle, ddi_dma_req_t *dmareq, 233 ddi_dma_cookie_t *cookiep, uint_t *ccountp); 234 extern int 235 pci_dma_unbindhdl(dev_info_t *dip, dev_info_t *rdip, 236 ddi_dma_handle_t handle); 237 extern int 238 pci_dma_flush(dev_info_t *dip, dev_info_t *rdip, 239 ddi_dma_handle_t handle, off_t off, size_t len, 240 uint_t cache_flags); 241 extern int 242 pci_dma_ctlops(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 243 enum ddi_dma_ctlops cmd, off_t *offp, size_t *lenp, caddr_t *objp, 244 uint_t cache_flags); 245 extern int 246 pci_ctlops(dev_info_t *dip, dev_info_t *rdip, 247 ddi_ctl_enum_t op, void *arg, void *result); 248 extern int 249 pci_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 250 ddi_intr_handle_impl_t *handle, void *result); 251 252 #ifdef __cplusplus 253 } 254 #endif 255 256 #endif /* _SYS_PCI_VAR_H */ 257