1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_PCI_VAR_H 28 #define _SYS_PCI_VAR_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* 37 * The following typedef is used to represent a 38 * 1275 "bus-range" property of a PCI Bus node. 39 */ 40 typedef struct bus_range { 41 uint32_t lo; 42 uint32_t hi; 43 } pci_bus_range_t; 44 45 /* 46 * The following typedef is used to represent a 47 * 1275 "reg" property of a PCI nexus. 48 */ 49 typedef struct pci_nexus_regspec { 50 uint64_t phys_addr; 51 uint64_t size; 52 } pci_nexus_regspec_t; 53 54 /* 55 * The following typedef is used to represent an entry in the "ranges" 56 * property of a device node. 57 */ 58 typedef struct ranges { 59 uint32_t child_high; 60 uint32_t child_mid; 61 uint32_t child_low; 62 uint32_t parent_high; 63 uint32_t parent_low; 64 uint32_t size_high; 65 uint32_t size_low; 66 } pci_ranges_t; 67 68 typedef enum { PSYCHO, SCHIZO } pci_bridge_t; 69 typedef enum { A, B } pci_side_t; 70 typedef enum { PCI_NEW, PCI_ATTACHED, PCI_DETACHED, PCI_SUSPENDED } pci_state_t; 71 typedef enum { PCI_PBM_OBJ, PCI_ECC_OBJ, PCI_CB_OBJ } pci_obj_t; 72 typedef enum { PCI_OBJ_INTR_ADD, PCI_OBJ_INTR_REMOVE } pci_obj_op_t; 73 74 #define PCI_ATTACH_RETCODE(obj, op, err) \ 75 ((err) ? (obj) << 8 | (op) << 4 | (err) & 0xf : DDI_SUCCESS) 76 77 #define PCI_OTHER_SIDE(side) ((side) ^ 1) 78 79 /* 80 * the sequence of the chip_type appearance is significant. There are code 81 * depending on it: CHIP_TYPE(pci_p) < PCI_CHIP_SCHIZO. 82 */ 83 typedef enum { 84 PCI_CHIP_UNIDENTIFIED = 0, 85 86 PCI_CHIP_PSYCHO = 1, 87 PCI_CHIP_SABRE, 88 PCI_CHIP_HUMMINGBIRD, 89 90 PCI_CHIP_SCHIZO = 0x11, 91 PCI_CHIP_XMITS, 92 PCI_CHIP_TOMATILLO 93 } pci_chip_id_t; 94 95 /* 96 * [msb] [lsb] 97 * 0x00 <chip_type> <version#> <module-revision#> 98 */ 99 #define CHIP_ID(t, v, m) (((t) << 16) | ((v) << 8) | (m)) 100 #define ID_CHIP_TYPE(id) ((id) >> 16) 101 #define PCI_CHIP_ID(pci_p) ((pci_p)->pci_common_p->pci_chip_id) 102 #define CHIP_TYPE(pci_p) ID_CHIP_TYPE(PCI_CHIP_ID(pci_p)) 103 #define CHIP_REV(pci_p) (PCI_CHIP_ID(pci_p) & 0xFF) 104 #define CHIP_VER(pci_p) ((PCI_CHIP_ID(pci_p) >> 8) & 0xFF) 105 #define CB_CHIP_TYPE(cb_p) ((cb_p)->cb_pci_cmn_p->pci_chip_id >> 16) 106 107 /* 108 * pci common soft state structure: 109 * 110 * Each psycho or schizo is represented by a pair of pci nodes in the 111 * device tree. A single pci common soft state is allocated for each 112 * pair. The UPA (Safari) bus id of the psycho (schizo) is used for 113 * the instance number. The attach routine uses the existance of a 114 * pci common soft state structure to determine if one node from the 115 * pair has been attached. 116 */ 117 struct pci_common { 118 uint_t pci_common_id; 119 120 /* pointers & counters to facilitate attach/detach & suspend/resume */ 121 ushort_t pci_common_refcnt; /* # of sides suspended + attached */ 122 ushort_t pci_common_attachcnt; /* # of sides attached */ 123 uint16_t pci_common_tsb_cookie; /* IOMMU TSB allocation */ 124 pci_t *pci_p[2]; /* pci soft states of both sides */ 125 126 uint32_t pci_chip_id; /* Bus bridge chip identification */ 127 128 /* Links to functional blocks potentially shared between pci nodes */ 129 iommu_t *pci_common_iommu_p; 130 cb_t *pci_common_cb_p; 131 ib_t *pci_common_ib_p; 132 ecc_t *pci_common_ecc_p; 133 134 /* 135 * Performance counters kstat. 136 */ 137 pci_cntr_pa_t pci_cmn_uks_pa; 138 kstat_t *pci_common_uksp; /* ptr to upstream kstat */ 139 kmutex_t pci_fm_mutex; /* per chip error handling mutex */ 140 }; 141 142 /* 143 * pci soft state structure: 144 * 145 * Each pci node has a pci soft state structure. 146 */ 147 struct pci { 148 /* 149 * State flags and mutex: 150 */ 151 pci_state_t pci_state; 152 uint_t pci_soft_state; 153 #define PCI_SOFT_STATE_OPEN 0x01 154 #define PCI_SOFT_STATE_OPEN_EXCL 0x02 155 #define PCI_SOFT_STATE_CLOSED 0x04 156 uint_t pci_open_count; 157 uint16_t pci_tsb_cookie; /* IOMMU TSB allocation */ 158 kmutex_t pci_mutex; 159 160 /* 161 * Links to other state structures: 162 */ 163 pci_common_t *pci_common_p; /* pointer common soft state */ 164 dev_info_t *pci_dip; /* devinfo structure */ 165 ib_t *pci_ib_p; /* interrupt block */ 166 cb_t *pci_cb_p; /* control block */ 167 pbm_t *pci_pbm_p; /* PBM block */ 168 iommu_t *pci_iommu_p; /* IOMMU block */ 169 sc_t *pci_sc_p; /* streaming cache block */ 170 ecc_t *pci_ecc_p; /* ECC error block */ 171 172 /* 173 * other state info: 174 */ 175 uint_t pci_id; /* UPA (or Safari) device id */ 176 pci_side_t pci_side; 177 178 /* 179 * pci device node properties: 180 */ 181 pci_bus_range_t pci_bus_range; /* "bus-range" */ 182 pci_ranges_t *pci_ranges; /* "ranges" data & length */ 183 int pci_ranges_length; 184 uint32_t *pci_inos; /* inos from "interrupts" prop */ 185 int pci_inos_len; /* "interrupts" length */ 186 int pci_numproxy; /* upa interrupt proxies */ 187 int pci_thermal_interrupt; /* node has thermal interrupt */ 188 189 /* 190 * register mapping: 191 */ 192 caddr_t pci_address[4]; 193 ddi_acc_handle_t pci_ac[4]; 194 195 /* Interrupt support */ 196 int intr_map_size; 197 struct intr_map *intr_map; 198 struct intr_map_mask *intr_map_mask; 199 200 /* performance counters */ 201 pci_cntr_addr_t pci_ks_addr; 202 kstat_t *pci_ksp; 203 204 /* Hotplug information */ 205 206 boolean_t hotplug_capable; 207 208 /* Fault Management support */ 209 int pci_fm_cap; 210 ddi_iblock_cookie_t pci_fm_ibc; 211 }; 212 213 /* 214 * PSYCHO and PBM soft state macros: 215 */ 216 #define get_pci_soft_state(i) \ 217 ((pci_t *)ddi_get_soft_state(per_pci_state, (i))) 218 219 #define alloc_pci_soft_state(i) \ 220 ddi_soft_state_zalloc(per_pci_state, (i)) 221 222 #define free_pci_soft_state(i) \ 223 ddi_soft_state_free(per_pci_state, (i)) 224 225 #define get_pci_common_soft_state(i) \ 226 ((pci_common_t *)ddi_get_soft_state(per_pci_common_state, (i))) 227 228 #define alloc_pci_common_soft_state(i) \ 229 ddi_soft_state_zalloc(per_pci_common_state, (i)) 230 231 #define free_pci_common_soft_state(i) \ 232 ddi_soft_state_free(per_pci_common_state, (i)) 233 234 #define DEV_TO_SOFTSTATE(dev) ((pci_t *)ddi_get_soft_state(per_pci_state, \ 235 PCIHP_AP_MINOR_NUM_TO_INSTANCE(getminor(dev)))) 236 237 extern void *per_pci_state; /* per-pbm soft state pointer */ 238 extern void *per_pci_common_state; /* per-psycho soft state pointer */ 239 extern kmutex_t pci_global_mutex; /* attach/detach common struct lock */ 240 extern kmutex_t dvma_active_list_mutex; 241 242 /* 243 * function prototypes for bus ops routines: 244 */ 245 extern int 246 pci_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp, 247 off_t offset, off_t len, caddr_t *addrp); 248 extern int 249 pci_dma_setup(dev_info_t *dip, dev_info_t *rdip, 250 ddi_dma_req_t *dmareq, ddi_dma_handle_t *handlep); 251 extern int 252 pci_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_attr_t *attrp, 253 int (*waitfp)(caddr_t), caddr_t arg, ddi_dma_handle_t *handlep); 254 extern int 255 pci_dma_bindhdl(dev_info_t *dip, dev_info_t *rdip, 256 ddi_dma_handle_t handle, ddi_dma_req_t *dmareq, 257 ddi_dma_cookie_t *cookiep, uint_t *ccountp); 258 extern int 259 pci_dma_unbindhdl(dev_info_t *dip, dev_info_t *rdip, 260 ddi_dma_handle_t handle); 261 extern int 262 pci_dma_flush(dev_info_t *dip, dev_info_t *rdip, 263 ddi_dma_handle_t handle, off_t off, size_t len, 264 uint_t cache_flags); 265 extern int 266 pci_dma_ctlops(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 267 enum ddi_dma_ctlops cmd, off_t *offp, size_t *lenp, caddr_t *objp, 268 uint_t cache_flags); 269 extern int 270 pci_ctlops(dev_info_t *dip, dev_info_t *rdip, 271 ddi_ctl_enum_t op, void *arg, void *result); 272 extern int 273 pci_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 274 ddi_intr_handle_impl_t *handle, void *result); 275 276 #ifdef __cplusplus 277 } 278 #endif 279 280 #endif /* _SYS_PCI_VAR_H */ 281