1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_PCI_IOMMU_H 28 #define _SYS_PCI_IOMMU_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #include <sys/vmem.h> 37 38 typedef uint64_t dvma_addr_t; 39 typedef uint64_t dma_bypass_addr_t; 40 typedef uint64_t dma_peer_addr_t; 41 typedef uint16_t dvma_context_t; 42 typedef uint64_t window_t; 43 44 /* 45 * The following typedef's represents the types for DMA transactions 46 * and corresponding DMA addresses supported by psycho/schizo. 47 */ 48 typedef enum { IOMMU_XLATE, IOMMU_BYPASS, PCI_PEER_TO_PEER } iommu_dma_t; 49 50 /* 51 * The following macros define the iommu page size and related operations. 52 */ 53 #define IOMMU_PAGE_SHIFT 13 54 #define IOMMU_PAGE_SIZE (1 << IOMMU_PAGE_SHIFT) 55 #define IOMMU_PAGE_MASK ~(IOMMU_PAGE_SIZE - 1) 56 #define IOMMU_PAGE_OFFSET (IOMMU_PAGE_SIZE - 1) 57 #define IOMMU_PTOB(x) (((uint64_t)(x)) << IOMMU_PAGE_SHIFT) 58 #define IOMMU_BTOP(x) ((x) >> IOMMU_PAGE_SHIFT) 59 #define IOMMU_BTOPR(x) IOMMU_BTOP((x) + IOMMU_PAGE_OFFSET) 60 61 /* 62 * control register decoding 63 */ 64 /* tsb size: 0=1k 1=2k 2=4k 3=8k 4=16k 5=32k 6=64k 7=128k */ 65 #define IOMMU_CTL_TO_TSBSIZE(ctl) ((ctl) >> 16) 66 #define IOMMU_TSBSIZE_TO_TSBENTRIES(s) ((1 << (s)) << (13 - 3)) 67 #define IOMMU_DARWIN_BOGUS_TSBSIZE 7 68 69 /* 70 * boiler plate for tte (everything except the pfn) 71 */ 72 #define MAKE_TTE_TEMPLATE(pfn, mp) (COMMON_IOMMU_TTE_V | \ 73 (pf_is_memory(pfn) ? COMMON_IOMMU_TTE_C : 0) | \ 74 ((mp->dmai_rflags & DDI_DMA_READ) ? COMMON_IOMMU_TTE_W : 0) | \ 75 ((mp->dmai_rflags & DDI_DMA_CONSISTENT) ? 0 : COMMON_IOMMU_TTE_S)) 76 #define TTE_IS_INVALID(tte) (((tte) & COMMON_IOMMU_TTE_V) == 0x0ull) 77 78 /* 79 * The following macros define the address ranges supported for DVMA 80 * and iommu bypass transfers. 81 */ 82 #define COMMON_IOMMU_BYPASS_BASE 0xFFFC000000000000ull 83 #define COMMON_IOMMU_BYPASS_END 0xFFFC00FFFFFFFFFFull 84 85 /* 86 * For iommu bypass addresses, bit 43 specifies cacheability. 87 */ 88 #define COMMON_IOMMU_BYPASS_NONCACHE 0x0000080000000000ull 89 90 /* 91 * Generic iommu definitions and types: 92 */ 93 #define IOMMU_TLB_ENTRIES 16 94 95 /* 96 * The following macros are for loading and unloading iotte 97 * entries. 98 */ 99 #define COMMON_IOMMU_TTE_SIZE 8 100 #define COMMON_IOMMU_TTE_V 0x8000000000000000ull 101 #define COMMON_IOMMU_TTE_S 0x1000000000000000ull 102 #define COMMON_IOMMU_TTE_C 0x0000000000000010ull 103 #define COMMON_IOMMU_TTE_W 0x0000000000000002ull 104 #define COMMON_IOMMU_INVALID_TTE 0x0000000000000000ull 105 106 /* 107 * Tomatillo's micro TLB bug. errata #82 108 */ 109 typedef struct dvma_unbind_req { 110 uint32_t dur_base; 111 uint_t dur_npg; 112 uint_t dur_flags; /* = dmai_flags & DMAI_FLAGS_VMEMCACHE */ 113 } dvma_unbind_req_t; 114 115 /* 116 * iommu block soft state structure: 117 * 118 * Each pci node may share an iommu block structure with its peer 119 * node of have its own private iommu block structure. 120 */ 121 typedef struct iommu iommu_t; 122 struct iommu { 123 124 pci_t *iommu_pci_p; /* link back to pci soft state */ 125 int iommu_inst; /* ddi_get_instance(iommu_pci_p->pci_dip) */ 126 127 volatile uint64_t *iommu_ctrl_reg; 128 volatile uint64_t *iommu_tsb_base_addr_reg; 129 volatile uint64_t *iommu_flush_page_reg; 130 volatile uint64_t *iommu_flush_ctx_reg; /* schizo only */ 131 volatile uint64_t *iommu_tfar_reg; /* tomatillo only */ 132 133 /* 134 * virtual and physical addresses and size of the iommu tsb: 135 */ 136 uint64_t *iommu_tsb_vaddr; 137 uint64_t iommu_tsb_paddr; 138 uint_t iommu_tsb_entries; 139 uint_t iommu_tsb_size; 140 141 /* 142 * address ranges of dvma space: 143 */ 144 dvma_addr_t iommu_dvma_base; 145 dvma_addr_t iommu_dvma_end; 146 dvma_addr_t iommu_dvma_fast_end; 147 dvma_addr_t dvma_base_pg; /* = IOMMU_BTOP(iommu_dvma_base) */ 148 dvma_addr_t dvma_end_pg; /* = IOMMU_BTOP(iommu_dvma_end) */ 149 150 /* 151 * address ranges of dma bypass space: 152 */ 153 dma_bypass_addr_t iommu_dma_bypass_base; 154 dma_bypass_addr_t iommu_dma_bypass_end; 155 156 /* 157 * virtual memory map and callback id for dvma space: 158 */ 159 vmem_t *iommu_dvma_map; 160 uintptr_t iommu_dvma_clid; 161 162 /* 163 * fields for fast dvma interfaces: 164 */ 165 ulong_t iommu_dvma_reserve; 166 167 /* 168 * dvma fast track page cache byte map 169 */ 170 uint8_t *iommu_dvma_cache_locks; 171 uint_t iommu_dvma_addr_scan_start; 172 173 /* 174 * dvma context bitmap 175 */ 176 uint64_t *iommu_ctx_bitmap; 177 178 /* 179 * dvma debug 180 */ 181 kmutex_t dvma_debug_lock; 182 uint32_t dvma_alloc_rec_index; 183 uint32_t dvma_free_rec_index; 184 uint32_t dvma_active_count; 185 186 struct dvma_rec *dvma_alloc_rec; 187 struct dvma_rec *dvma_free_rec; 188 struct dvma_rec *dvma_active_list; 189 190 /* 191 * tomatillo's micro TLB bug. errata #82 192 */ 193 dvma_unbind_req_t *iommu_mtlb_req_p; /* unbind requests */ 194 uint32_t iommu_mtlb_maxpgs; /* GC threshold */ 195 uint32_t iommu_mtlb_npgs; /* total page count */ 196 uint32_t iommu_mtlb_nreq; /* total request count */ 197 kmutex_t iommu_mtlb_lock; 198 }; 199 200 typedef struct pci_dvma_range_prop { 201 uint32_t dvma_base; 202 uint32_t dvma_len; 203 } pci_dvma_range_prop_t; 204 205 #define IOMMU_PAGE_INDEX(iommu_p, dvma_pg) ((dvma_pg) - (iommu_p)->dvma_base_pg) 206 #define IOMMU_PAGE_FLUSH(iommu_p, dvma_pg) \ 207 *(iommu_p)->iommu_flush_page_reg = IOMMU_PTOB(dvma_pg) 208 #define IOMMU_UNLOAD_TTE(iommu_p, pg_index) \ 209 (iommu_p)->iommu_tsb_vaddr[pg_index] = COMMON_IOMMU_INVALID_TTE 210 #define IOMMU_PAGE_TTEPA(iommu_p, dvma_pg) \ 211 ((iommu_p)->iommu_tsb_paddr + (IOMMU_PAGE_INDEX(iommu_p, dvma_pg) << 3)) 212 213 #define IOMMU_CONTEXT_BITS 12 214 #define IOMMU_CTX_MASK ((1 << IOMMU_CONTEXT_BITS) - 1) 215 #define IOMMU_TTE_CTX_SHIFT 47 216 #define IOMMU_CTX2TTE(ctx) (((uint64_t)(ctx)) << IOMMU_TTE_CTX_SHIFT) 217 #define IOMMU_TTE2CTX(tte) \ 218 (((tte) >> (IOMMU_TTE_CTX_SHIFT - 32)) & IOMMU_CTX_MASK) 219 #define MP2CTX(mp) IOMMU_TTE2CTX((uint32_t)(uintptr_t)(mp)->dmai_tte) 220 221 /* dvma debug */ 222 #define DVMA_DBG_ON(iommu_p) \ 223 ((1ull << (iommu_p)->iommu_inst) & pci_dvma_debug_on) 224 #define DVMA_DBG_OFF(iommu_p) \ 225 ((1ull << (iommu_p)->iommu_inst) & pci_dvma_debug_off) 226 227 extern void pci_dvma_debug_fini(iommu_t *iommu_p); 228 extern void pci_dvma_alloc_debug(iommu_t *iommu_p, char *address, uint_t len, 229 ddi_dma_impl_t *mp); 230 extern void pci_dvma_free_debug(iommu_t *iommu_p, char *address, uint_t len, 231 ddi_dma_impl_t *mp); 232 233 /* dvma routines */ 234 extern void iommu_map_pages(iommu_t *iommu_p, ddi_dma_impl_t *mp, 235 dvma_addr_t dvma_pg, size_t npages, size_t pfn_index); 236 extern void iommu_unmap_pages(iommu_t *iommu_p, dvma_addr_t dvma_pg, 237 uint_t npages); 238 extern void iommu_remap_pages(iommu_t *iommu_p, ddi_dma_impl_t *mp, 239 dvma_addr_t dvma_pg, size_t npages, size_t pfn_index); 240 extern void iommu_map_window(iommu_t *iommu_p, 241 ddi_dma_impl_t *mp, window_t window); 242 extern void iommu_unmap_window(iommu_t *iommu_p, ddi_dma_impl_t *mp); 243 244 /* iommu initialization routines */ 245 extern void iommu_configure(iommu_t *iommu_p); 246 extern void iommu_create(pci_t *pci_p); 247 extern void iommu_destroy(pci_t *pci_p); 248 extern uint_t iommu_tsb_size_encode(uint_t tsb_bytes); 249 250 /* TSB allocate/free */ 251 extern int pci_alloc_tsb(pci_t *pci_p); 252 extern void pci_free_tsb(pci_t *pci_p); 253 254 #ifdef __cplusplus 255 } 256 #endif 257 258 #endif /* _SYS_PCI_IOMMU_H */ 259