1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 1998 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_ENVCTRL_UE450_H 28 #define _SYS_ENVCTRL_UE450_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* 37 * envctrl_ue450.h 38 * 39 * This header file contains environmental control definitions specific 40 * to the UltraEnterprise-450 (aka. Ultra-4) platform. 41 */ 42 43 #define OVERTEMP_TIMEOUT_USEC 60 * MICROSEC 44 #define BLINK_TIMEOUT_USEC 500 * (MICROSEC / MILLISEC) 45 46 #define MAX_TAZ_CONTROLLERS 0x02 47 #define ENVCTRL_TAZCPU_STRING "SUNW,UltraSPARC" 48 #define ENVCTRL_TAZBLKBRDCPU_STRING "SUNW,UltraSPARC-II" 49 50 /* 51 * MACROS 52 */ 53 54 #define S1 &unitp->bus_ctl_regs->s1 55 #define S0 &unitp->bus_ctl_regs->s0 56 57 /* 58 * I2c Sensor Types 59 */ 60 61 #define PCD8584 0x00 /* Bus Controller Master */ 62 #define PCF8591 0x01 /* Temp Sensor 8bit A/D, D/A */ 63 #define PCF8574 0x02 /* PS, FAN, LED, Fail and Control */ 64 #define TDA8444T 0x03 /* Fan Speed Control, 8 bit D/A */ 65 #define PCF8574A 0x04 /* 8574A chip */ 66 #define PCF8583 0x05 /* PCF8583 clock chip */ 67 68 /* 69 * Max number of a particular 70 * device on 1 bus. 71 */ 72 #define MAX_DEVS 0x10 73 #define I2C_NODEV 0xFF 74 #define MIN_FAN_BANKS 0x02 75 #define INSTANCE_0 0x00 76 77 /* 78 * Defines for the PCF8583 Clock Calendar Chip 79 * We use this chip as a watchdog timer for the fans 80 * should the kernel thread controling the fans get 81 * wedged. If it does, the alarm wil go off and 82 * set the fans to max speed. 83 * Valid addresses for this chip are A0, A2. 84 * We use the address at A0. 85 * To address this chip the format is as folows (write mode) 86 * | SLaveaddress |MEMORY LOCATION| DATA| 87 * Wgere memory location is the internal location from 88 * 0x00 - 0x0F. 0x00 is the CSR and MUST be addressed 89 * directly. 90 */ 91 92 #define PCF8583_BASE_ADDR 0xA0 93 #define PCF8583_READ_BIT 0x01 94 95 #define CLOCK_CSR_REG 0x00 96 97 #define ALARM_CTRL_REG 0x07 98 #define EGG_TIMER_VAL 0x96 99 #define DIAG_MAX_TIMER_VAL 0x00 100 #define MAX_CL_VAL 59 101 #define MIN_DIAG_TEMPR 0x00 102 #define MAX_DIAG_TEMPR 70 103 #define MAX_AMB_TEMP 50 104 #define MAX_CPU_TEMP 80 105 #define MAX_PS_TEMP 100 106 #define MAX_PS_ADVAL 0xfd 107 #define PS_DEFAULT_VAL 17 /* corresponds to 90 C in lookup table */ 108 #define PS_TEMP_WARN 95 109 #define CPU_AMB_RISE 20 /* cpu runs avg of 20 above amb */ 110 #define PS_AMB_RISE 30 /* cpu runs avg of 30 above amb */ 111 112 #define CLOCK_ALARM_REG_A 0x08 113 #define CLOCK_ENABLE_TIMER 0xCB 114 #define CLOCK_ENABLE_TIMER_S 0xCA 115 116 #define CLOCK_DISABLE 0xA0 117 #define CLOCK_ENABLE 0x04 118 119 /* Keyswitch Definitions */ 120 #define ENVCTRL_FSP_KEYMASK 0xC0 121 #define ENVCTRL_FSP_POMASK 0x20 122 #define ENVCTRL_FSP_KEYLOCKED 0x00 123 #define ENVCTRL_FSP_KEYOFF 0x40 124 #define ENVCTRL_FSP_KEYDIAG 0x80 125 #define ENVCTRL_FSP_KEYON 0xC0 126 127 /* Front Status Panel Definitions */ 128 #define ENVCTRL_FSP_DISK_ERR 0x01 129 #define ENVCTRL_FSP_PS_ERR 0x02 130 #define ENVCTRL_FSP_TEMP_ERR 0x04 131 #define ENVCTRL_FSP_GEN_ERR 0x08 132 #define ENVCTRL_FSP_ACTIVE 0x10 133 #define ENVCTRL_FSP_POWER 0x20 134 #define ENVCTRL_FSP_USRMASK (ENVCTRL_FSP_DISK_ERR | ENVCTRL_FSP_GEN_ERR) 135 136 #define ENVCTRL_ENCL_FSP 0x00 137 #define ENVCTRL_ENCL_AMBTEMPR 0x01 138 #define ENVCTRL_ENCL_CPUTEMPR 0x02 139 #define ENVCTRL_ENCL_BACKPLANE4 0x03 140 #define ENVCTRL_ENCL_BACKPLANE8 0x04 141 142 #define ENVCTRL_FSP_OFF 0x4F 143 144 /* 145 * configuration registers 146 * Register S1 Looks like the following: 147 * WRITE MODE ONLY 148 * 149 * MSB -------------------------------------> LSB 150 * ---------------------------------------------- 151 * | X | ESO | ES1 | ES2 | ENI | STA | STO | ACK | 152 * ---------------------------------------------- 153 * Low order bits 154 */ 155 156 #define CSRS1_ENI 0x08 /* Enable interrupts */ 157 #define CSRS1_STA 0x04 /* Packet Start */ 158 #define CSRS1_STO 0x02 /* Packet Stop */ 159 #define CSRS1_ACK 0x01 /* Packet ACK */ 160 161 /* Hight order bits */ 162 #define CSRS1_PIN 0x80 /* READ and WRITE mode Enable Serial Output */ 163 #define CSRS1_ESO 0x40 /* Enable Serial Output */ 164 #define CSRS1_ES1 0x20 165 #define CSRS1_ES2 0x10 166 167 /* 168 * configuration registers 169 * Register S1 Looks like the following: 170 * READ MODE ONLY 171 * 172 * MSB -------------------------------------> LSB 173 * ---------------------------------------------- 174 * | PIN | 0 | STS | BER | AD0/LRB | AAS | LAB | BB| 175 * ---------------------------------------------- 176 */ 177 178 #define CSRS1_STS 0x20 /* For Slave receiv mode stop */ 179 #define CSRS1_BER 0x10 /* Bus Error */ 180 181 #define CSRS1_LRB 0x08 /* Last Received Bit */ 182 #define CSRS1_AAS 0x04 /* Addressed as Slave */ 183 #define CSRS1_LAB 0x02 /* Lost Arbitration Bit */ 184 #define CSRS1_BB 0x01 /* Bus Busy */ 185 186 #define START CSRS1_PIN | CSRS1_ESO | CSRS1_STA | CSRS1_ACK 187 #define STOP CSRS1_PIN | CSRS1_ESO | CSRS1_STO | CSRS1_ACK 188 /* 189 * A read wants to have an NACK on the bus to stop 190 * transmitting data from the slave. If you don't 191 * NACK the SDA line will get stuck low. After this you 192 * can send the stop with the ack. 193 */ 194 #define NACK CSRS1_PIN | CSRS1_ESO 195 196 /* 197 * ESO = Enable Serial output 198 * ES1 and ES2 have different meanings based upon ES0. 199 * The following table explains this association. 200 * 201 * ES0 = 0 = serial interface off. 202 * --------------------------------------------------------- 203 * | A0 | ES1 | ES1 | iACK | OPERATION 204 * --------------------------------------------------------- 205 * | H | X | X | X | Read/write CSR1 (S1) Status n/a 206 * | | | | | 207 * | L | 0 | 0 | X | R/W Own Address S0' 208 * | | | | | 209 * | L | 0 | 1 | X | R/W Intr Vector S3 210 * | | | | | 211 * | L | 1 | 0 | X | R/W Clock Register S2 212 * --------------------------------------------------------- 213 * 214 * ES0 = 1 = serial interface ON. 215 * --------------------------------------------------------- 216 * | A0 | ES1 | ES1 | iACK | OPERATION 217 * --------------------------------------------------------- 218 * | H | X | X | H | Write Control Register (S1) 219 * | | | | | 220 * | H | X | X | H | Read Status Register (S1) 221 * | | | | | 222 * | L | X | 0 | H | R/W Data Register (S0) 223 * | | | | | 224 * | L | X | 1 | H | R/W Interrupt Vector (S3) 225 * | | | | | 226 * | X | 0 | X | L | R Interrupt Vector (S3) ack cycle 227 * | | | | | 228 * | X | 1 | X | L | long distance mode 229 * --------------------------------------------------------- 230 * 231 */ 232 233 #ifdef TESTBED 234 struct envctrl_pcd8584_regs { 235 uchar_t s0; /* Own Address S0' */ 236 uchar_t pad[3]; /* Padding XXX Will go away in FCS */ 237 uchar_t s1; /* Control Status register */ 238 uchar_t pad1[3]; 239 uchar_t clock_s2; /* Clock programming register */ 240 }; 241 #else 242 struct envctrl_pcd8584_regs { 243 uchar_t s0; /* Own Address S0' */ 244 uchar_t s1; /* Control Status register */ 245 uchar_t clock_s2; /* Clock programming register */ 246 }; 247 #endif 248 #define ENVCTRL_BUS_INIT0 0x80 249 #define ENVCTRL_BUS_INIT1 0x55 250 #define ENVCTRL_BUS_CLOCK0 0xA0 251 #define ENVCTRL_BUS_CLOCK1 0x1C 252 #define ENVCTRL_BUS_ESI 0xC1 253 254 255 /* 256 * PCF8591 Chip Used for temperature sensors 257 * 258 * Check with bob to see if singled ended inputs are true 259 * for the pcf8591 temp sensors.. 260 * 261 * Addressing Register definition. 262 * A0-A2 valid range is 0-7 263 * 264 * 7 6 5 4 3 2 1 0 265 * ------------------------------------------------ 266 * | 1 | 0 | 0 | 1 | A2 | A1 | A0 | R/W | 267 * ------------------------------------------------ 268 */ 269 270 271 #define PCF8591_BASE_ADDR 0x90 272 #define PCF8501_MAX_DEVS 0x08 273 274 #define MAXPS 0x02 /* 0 based array */ 275 276 #define PSTEMP0 0x00 /* DUMMY PS */ 277 #define PSTEMP1 0x94 278 #define PSTEMP2 0x92 279 #define PSTEMP3 0x90 280 #define ENVCTRL_CPU_PCF8591_ADDR (PCF8591_BASE_ADDR | PCF8591_DEV7) 281 282 #define PCF8591_DEV0 0x00 283 #define PCF8591_DEV1 0x02 284 #define PCF8591_DEV2 0x04 285 #define PCF8591_DEV3 0x06 286 #define PCF8591_DEV4 0x08 287 #define PCF8591_DEV5 0x0A 288 #define PCF8591_DEV6 0x0C 289 #define PCF8591_DEV7 0x0E 290 291 292 /* 293 * For the LM75 thermal watchdog chip by TI 294 */ 295 296 #define LM75_BASE_ADDR 0x9A 297 #define LM75_READ_BIT 0x01 298 #define LM75_CONFIG_ADDR2 0x02 299 #define LM75_CONFIG_ADDR4 0x04 300 #define LM75_CONFIG_ADDR6 0x06 301 #define LM75_CONFIG_ADDR8 0x08 302 #define LM75_CONFIG_ADDRA 0x0A 303 #define LM75_CONFIG_ADDRC 0x0C 304 #define LM75_CONFIG_ADDRE 0x0E 305 #define LM75_COMP_MASK 0x100 306 #define LM75_COMP_MASK_UPPER 0xFF 307 308 /* 309 * CONTROL OF CHIP 310 * PCF8591 Temp sensing control register definitions 311 * 312 * 7 6 5 4 3 2 1 0 313 * --------------------------------------------- 314 * | 0 | AOE | X | X | 0 | AIF | X | X | 315 * --------------------------------------------- 316 * AOE = Analog out enable.. not used on out implementation 317 * 5 & 4 = Analog Input Programming.. see data sheet for bits.. 318 * 319 * AIF = Auto increment flag 320 * bits 1 & 0 are for the Chennel number. 321 */ 322 323 #define PCF8591_ANALOG_OUTPUT_EN 0x40 324 #define PCF8591_ANALOG_INPUT_EN 0x00 325 #define PCF8591_READ_BIT 0x01 326 327 328 #define PCF8591_AUTO_INCR 0x04 329 #define PCF8591_OSCILATOR 0x40 330 331 #define PCF8591_MAX_PORTS 0x04 332 333 #define PCF8591_CH_0 0x00 334 #define PCF8591_CH_1 0x01 335 #define PCF8591_CH_2 0x02 336 #define PCF8591_CH_3 0x03 337 338 struct envctrl_pcf8591_chip { 339 uchar_t chip_num; /* valid values are 0-7 */ 340 int type; /* type is PCF8591 */ 341 uchar_t sensor_num; /* AIN0, AIN1, AIN2 AIN3 */ 342 uchar_t temp_val; /* value of temp probe */ 343 }; 344 345 346 /* 347 * PCF8574 Fan Fail, Power Supply Fail Detector 348 * This device is driven by interrupts. Each time it interrupts 349 * you must look at the CSR to see which ports caused the interrupt 350 * they are indicated by a 1. 351 * 352 * Address map of this chip 353 * 354 * ------------------------------------------- 355 * | 0 | 1 | 1 | 1 | A2 | A1 | A0 | 0 | 356 * ------------------------------------------- 357 * 358 */ 359 360 #define PCF8574A_BASE_ADDR 0x70 361 #define PCF8574_BASE_ADDR 0x40 362 363 #define PCF8574_READ_BIT 0x01 364 365 #define ENVCTRL_PCF8574_DEV0 0x00 366 #define ENVCTRL_PCF8574_DEV1 0x02 367 #define ENVCTRL_PCF8574_DEV2 0x04 368 #define ENVCTRL_PCF8574_DEV3 0x06 369 #define ENVCTRL_PCF8574_DEV4 0x08 370 #define ENVCTRL_PCF8574_DEV5 0x0A 371 #define ENVCTRL_PCF8574_DEV6 0x0C 372 #define ENVCTRL_PCF8574_DEV7 0x0E 373 #define ENVCTRL_INTR_CHIP PCF8574_DEV7 374 375 #define PS1 PCF8574A_BASE_ADDR | ENVCTRL_PCF8574_DEV3 376 #define PS2 PCF8574A_BASE_ADDR | ENVCTRL_PCF8574_DEV2 377 #define PS3 PCF8574A_BASE_ADDR | ENVCTRL_PCF8574_DEV1 378 379 #define ENVCTRL_PCF8574_PORT0 0x01 380 #define ENVCTRL_PCF8574_PORT1 0x02 381 #define ENVCTRL_PCF8574_PORT2 0x04 382 #define ENVCTRL_PCF8574_PORT3 0x08 383 #define ENVCTRL_PCF8574_PORT4 0x10 384 #define ENVCTRL_PCF8574_PORT5 0x20 385 #define ENVCTRL_PCF8574_PORT6 0x40 386 #define ENVCTRL_PCF8574_PORT7 0x80 387 388 #define ENVCTRL_DFLOP_INIT0 0x77 389 #define ENVCTRL_DFLOP_INIT1 0x7F 390 391 #define ENVCTRL_DEVINTR_INTI0 0xF7 392 #define ENVCTRL_DEVINTR_INTI1 0xFF 393 394 #define CPU_FAN_1 0x01 395 #define CPU_FAN_2 0x02 396 #define CPU_FAN_3 0x03 397 398 #define PS_FAN_1 CPU_FAN_1 399 #define PS_FAN_2 CPU_FAN_2 400 #define PS_FAN_3 CPU_FAN_3 401 402 #define AFB_FAN_1 0x00 403 404 struct envctrl_pcf8574_chip { 405 uchar_t chip_num; /* valid values are 0-7 */ 406 int type; /* type is PCF8574 */ 407 uint_t val; 408 }; 409 410 411 /* 412 * TDA8444T chip structure 413 * FAN Speed Control 414 */ 415 416 /* ADDRESSING */ 417 418 #define TDA8444T_BASE_ADDR 0x40 419 420 421 #define ENVCTRL_TDA8444T_DEV0 0x00 422 #define ENVCTRL_TDA8444T_DEV1 0x02 423 #define ENVCTRL_TDA8444T_DEV2 0x04 424 #define ENVCTRL_TDA8444T_DEV3 0x06 425 #define ENVCTRL_TDA8444T_DEV4 0x08 426 #define ENVCTRL_TDA8444T_DEV5 0x0A 427 #define ENVCTRL_TDA8444T_DEV6 0x0C 428 #define ENVCTRL_TDA8444T_DEV7 0x0E 429 430 #define ENVCTRL_FAN_ADDR_MIN ENVCTRL_TDA8444T_DEV0 431 #define ENVCTRL_FAN_ADDR_MAX ENVCTRL_TDA8444T_DEV7 432 433 /* Control information and port addressing */ 434 435 #define NO_AUTO_PORT_INCR 0xF0 436 #define AUTO_PORT_INCR 0x00 437 #define TDA8444T_READ_BIT 0x01 438 439 #define ENVCTRL_CPU_FANS 0x00 440 #define ENVCTRL_PS_FANS 0x01 441 #define ENVCTRL_AFB_FANS 0x02 442 443 #define MAX_FAN_SPEED 0x3f 444 #define MIN_FAN_VAL 0x00 445 #define MAX_FAN_VAL 0x3f 446 #define AFB_MAX 0x3f 447 #define AFB_MIN 0x1d 448 449 struct envctrl_tda8444t_chip { 450 uchar_t chip_num; /* valid values are 0-7 */ 451 int type; /* type is TDA8444T */ 452 uchar_t fan_num; /* Ao0-Ao7 */ 453 uchar_t val; /* for fan speed */ 454 }; 455 456 /* 457 * This table converts an A/D value from the cpu thermistor to a 458 * temperature in degrees C. Usable range is typically 35-135. 459 */ 460 461 static short cpu_temps[] = { 462 150, 150, 150, 150, 150, 150, 150, 150, /* 0-7 */ 463 150, 150, 150, 150, 150, 150, 150, 150, /* 8-15 */ 464 150, 150, 150, 150, 150, 150, 150, 150, /* 16-23 */ 465 150, 150, 150, 148, 146, 144, 143, 142, /* 24-31 */ 466 141, 140, 138, 136, 135, 134, 133, 132, /* 32-39 */ 467 131, 130, 129, 128, 127, 126, 125, 124, /* 40-47 */ 468 123, 122, 121, 121, 120, 120, 119, 118, /* 48-55 */ 469 117, 116, 115, 114, 113, 112, 112, 111, /* 56-63 */ 470 111, 110, 110, 110, 109, 109, 108, 107, /* 64-71 */ 471 106, 106, 105, 105, 104, 103, 102, 101, /* 72-79 */ 472 101, 100, 100, 100, 99, 99, 98, 98, /* 80-87 */ 473 97, 97, 96, 96, 95, 95, 94, 94, /* 88-95 */ 474 93, 93, 92, 92, 91, 91, 91, 90, /* 96-103 */ 475 90, 90, 89, 89, 88, 88, 87, 87, /* 104-111 */ 476 86, 86, 85, 85, 84, 84, 83, 83, /* 112-119 */ 477 82, 82, 82, 81, 81, 80, 80, 80, /* 120-127 */ 478 80, 79, 79, 79, 78, 78, 78, 77, /* 128-135 */ 479 77, 77, 76, 76, 76, 75, 75, 75, /* 136-143 */ 480 74, 74, 74, 73, 73, 73, 72, 72, /* 144-151 */ 481 72, 71, 71, 71, 70, 70, 70, 70, /* 142-159 */ 482 69, 69, 69, 68, 68, 68, 68, 67, /* 160-167 */ 483 67, 67, 67, 66, 66, 66, 66, 65, /* 168-175 */ 484 65, 65, 64, 64, 64, 63, 63, 63, /* 176-183 */ 485 62, 62, 62, 61, 61, 61, 61, 60, /* 184-191 */ 486 60, 60, 60, 59, 59, 59, 58, 58, /* 192-199 */ 487 58, 57, 57, 57, 56, 56, 56, 56, /* 200-207 */ 488 55, 55, 55, 55, 54, 54, 54, 53, /* 208-215 */ 489 53, 53, 52, 52, 52, 51, 51, 51, /* 216-223 */ 490 51, 50, 50, 50, 49, 49, 49, 48, /* 224-231 */ 491 48, 48, 47, 47, 47, 46, 46, 46, /* 232-239 */ 492 45, 45, 45, 44, 44, 44, 43, 43, /* 240-247 */ 493 43, 42, 42, 42, 41, 41, 41, 40, /* 248-255 */ 494 40, /* 256 */ 495 }; 496 497 static short ps_temps[] = { 498 160, 155, 154, 150, 130, 125, 120, 115, /* 0-7 */ 499 110, 110, 106, 103, 101, 100, 97, 94, /* 8-15 */ 500 92, 90, 88, 86, 84, 83, 82, 81, /* 16-23 */ 501 80, 79, 78, 77, 76, 74, 72, 71, /* 24-31 */ 502 70, 69, 68, 67, 66, 65, 64, 63, /* 32-39 */ 503 62, 62, 61, 61, 60, 60, 60, 59, /* 40-47 */ 504 59, 58, 58, 57, 56, 56, 55, 55, /* 48-55 */ 505 54, 54, 53, 53, 52, 52, 51, 51, /* 56-63 */ 506 50, 50, 50, 49, 49, 49, 49, 48, /* 64-71 */ 507 48, 48, 48, 47, 47, 47, 47, 46, /* 72-79 */ 508 46, 46, 45, 44, 43, 42, 41, 41, /* 80-87 */ 509 40, 40, 40, 40, 39, 39, 39, 38, /* 88-95 */ 510 38, 38, 37, 37, 36, 36, 36, 35, /* 96-103 */ 511 35, 35, 35, 34, 34, 34, 33, 33, /* 104-111 */ 512 32, 32, 32, 32, 32, 32, 31, 31, /* 112-119 */ 513 31, 31, 31, 30, 30, 30, 29, 29, /* 120-127 */ 514 29, 29, 29, 29, 28, 28, 28, 28, /* 128-135 */ 515 28, 28, 27, 27, 27, 27, 27, 26, /* 136-143 */ 516 26, 26, 26, 26, 26, 26, 26, 26, /* 144-151 */ 517 25, 25, 25, 25, 24, 24, 23, 23, /* 142-159 */ 518 22, 22, 21, 21, 21, 21, 21, 21, /* 160-167 */ 519 20, 20, 20, 20, 19, 19, 19, 19, /* 168-175 */ 520 19, 18, 18, 18, 18, 18, 17, 17, /* 176-183 */ 521 17, 17, 17, 16, 16, 16, 16, 15, /* 184-191 */ 522 15, 15, 15, 15, 15, 14, 14, 14, /* 192-199 */ 523 14, 14, 13, 13, 13, 13, 12, 12, /* 200-207 */ 524 12, 12, 12, 11, 11, 11, 11, 11, /* 208-215 */ 525 10, 10, 10, 10, 10, 10, 10, 10, /* 216-223 */ 526 9, 9, 9, 9, 9, 9, 8, 8, /* 224-231 */ 527 8, 8, 8, 7, 7, 7, 7, 7, /* 232-239 */ 528 7, 6, 6, 6, 6, 6, 6, 6, /* 240-247 */ 529 5, 5, 5, 5, 5, 5, 5, 4, /* 248-255 */ 530 4, /* 256 */ 531 }; 532 533 /* 534 * This is the lookup table used for P1 and FCS systems to convert a temperature 535 * to a fanspeed for the CPU side of the machine. 536 */ 537 538 static short acme_cpu_fanspd[] = { 539 31, 31, 31, 31, 31, 31, 31, 31, /* 0-7 */ 540 31, 31, 31, 31, 31, 31, 31, 31, /* 8-15 */ 541 31, 31, 31, 31, 31, 31, 31, 31, /* 16-23 */ 542 31, 31, 31, 31, 32, 33, 34, 35, /* 24-31 */ 543 36, 37, 38, 39, 40, 42, 43, 45, /* 32-39 */ 544 48, 49, 50, 51, 52, 53, 54, 55, /* 40-47 */ 545 56, 57, 58, 59, 60, 61, 62, 63, /* 48-55 */ 546 63, 63, 63, 63, 63, 63, 63, 63, /* 56-63 */ 547 63, 63, 63, 63, 63, 63, 63, 63, /* 64-71 */ 548 63, 63, 63, 63, 63, 63, 63, 63, /* 72-79 */ 549 63, 63, 63, 63, 63, 63, 63, 63, /* 80-87 */ 550 63, 63, 63, 63, 63, 63, 63, 63, /* 88-95 */ 551 63, 63, 63, 63, 63, 63, 63, 63, /* 96-103 */ 552 63, 63, 63, 63, 63, 63, 63, 63, /* 104-111 */ 553 }; 554 555 /* 556 * This is the lookup table used for P1 and FCS systems to convert a temperature 557 * to a fanspeed for the CPU side of the machine. 558 */ 559 560 static short acme_ps_fanspd[] = { 561 31, 31, 31, 31, 31, 31, 31, 31, /* 0-7 */ 562 31, 31, 31, 31, 31, 31, 31, 31, /* 8-15 */ 563 31, 31, 31, 31, 31, 31, 31, 31, /* 16-23 */ 564 31, 31, 31, 31, 31, 33, 34, 35, /* 24-31 */ 565 36, 37, 38, 38, 39, 40, 41, 42, /* 32-39 */ 566 43, 45, 46, 47, 48, 48, 48, 48, /* 40-47 */ 567 48, 48, 49, 50, 51, 52, 53, 54, /* 48-55 */ 568 55, 56, 57, 58, 59, 60, 61, 62, /* 56-63 */ 569 63, 63, 63, 63, 63, 63, 63, 63, /* 64-71 */ 570 63, 63, 63, 63, 63, 63, 63, 63, /* 72-79 */ 571 63, 63, 63, 63, 63, 63, 63, 63, /* 80-87 */ 572 63, 63, 63, 63, 63, 63, 63, 63, /* 88-95 */ 573 63, 63, 63, 63, 63, 63, 63, 63, /* 96-103 */ 574 63, 63, 63, 63, 63, 63, 63, 63, /* 104-111 */ 575 }; 576 577 static short ps_fans[] = { 578 10, 10, 10, 10, 10, 10, 10, 10, /* 0-7 */ 579 10, 10, 10, 10, 10, 10, 10, 10, /* 8-15 */ 580 10, 10, 10, 10, 10, 10, 10, 10, /* 16-23 */ 581 10, 10, 10, 10, 10, 10, 10, 10, /* 24-31 */ 582 10, 10, 10, 10, 10, 10, 10, 10, /* 32-39 */ 583 11, 12, 13, 14, 15, 16, 17, 18, /* 24-31 */ 584 19, 20, 21, 22, 23, 24, 25, 26, /* 32-39 */ 585 27, 28, 29, 30, 31, 32, 33, 34, /* 40-47 */ 586 35, 36, 37, 38, 39, 40, 41, 42, /* 48-55 */ 587 43, 44, 45, 46, 47, 48, 49, 50, /* 56-63 */ 588 50, 50, 50, 50, 50, 50, 50, 50, /* 56-63 */ 589 13, 12, 11, 10, 10, 10, 10, 10, /* 64-71 */ 590 10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 591 10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 592 10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 593 10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 594 10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 595 10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 596 10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 597 10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 598 10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 599 10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 600 10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 601 10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 602 10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 603 10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 604 10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 605 10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 606 10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 607 10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 608 10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 609 10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 610 10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 611 10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 612 10, 613 }; 614 615 /* 616 * Get a fan speed setting based upon a temperature value 617 * from the above lookup tables. 618 * Less than zero ia a special case and greater than 70 is a 619 * the operating range of the powersupply. The system operating 620 * range is 5 - 40 Degrees C. 621 * This may need some tuning. 622 * The MAX_CPU_TEMP is set to 80 now, this table is used to set their 623 * fans. 624 */ 625 static short fan_speed[] = { 626 30, 29, 28, 27, 26, 25, 24, 23, /* 0-7 */ 627 23, 23, 23, 23, 22, 21, 20, 20, /* 8-15 */ 628 20, 20, 20, 20, 20, 20, 20, 20, /* 16-23 */ 629 19, 18, 17, 16, 15, 14, 13, 12, /* 24-31 */ 630 11, 11, 11, 11, 11, 11, 11, 11, /* 32-39 */ 631 11, 11, 11, 10, 10, 10, 9, 8, /* 40-47 */ 632 7, 6, 5, 4, 3, 2, 1, 1, /* 48-55 */ 633 1, 1, 1, 1, 1, 1, 1, 1, /* 56-63 */ 634 1, 1, 1, 1, 1, 1, 1, 1, /* 64-71 */ 635 1, 1, 1, 1, 1, 1, 1, 1, /* 72-79 */ 636 1, 1, 1, 1, 1, 1, 1, 1, /* 80-87 */ 637 }; 638 639 640 #if defined(_KERNEL) 641 642 struct envctrlunit { 643 struct envctrl_pcd8584_regs *bus_ctl_regs; 644 ddi_acc_handle_t ctlr_handle; 645 kmutex_t umutex; /* lock for this structure */ 646 int instance; 647 dev_info_t *dip; /* device information */ 648 struct envctrl_ps ps_kstats[MAX_DEVS]; /* kstats for powersupplies */ 649 struct envctrl_fan fan_kstats[MAX_DEVS]; /* kstats for fans */ 650 struct envctrl_encl encl_kstats[MAX_DEVS]; /* kstats for enclosure */ 651 int cpu_pr_location[ENVCTRL_MAX_CPUS]; /* slot true if cpu present */ 652 uint_t num_fans_present; 653 uint_t num_ps_present; 654 uint_t num_encl_present; 655 uint_t num_cpus_present; 656 kstat_t *psksp; 657 kstat_t *fanksp; 658 kstat_t *enclksp; 659 ddi_iblock_cookie_t ic_trap_cookie; /* interrupt cookie */ 660 queue_t *readq; /* pointer to readq */ 661 queue_t *writeq; /* pointer to writeq */ 662 mblk_t *msg; /* current message block */ 663 /* CPR support */ 664 boolean_t suspended; /* TRUE if driver suspended */ 665 boolean_t oflag; /* already open */ 666 int current_mode; /* NORMAL or DIAG_MODE */ 667 int AFB_present; /* is the AFB present */ 668 timeout_id_t timeout_id; /* timeout id */ 669 timeout_id_t pshotplug_id; /* ps poll id */ 670 int ps_present[MAXPS+1]; /* PS present t/f 0 not used */ 671 int num_fans_failed; /* don't change fan speed if > 0 */ 672 int activity_led_blink; 673 int present_led_state; /* is it on or off?? */ 674 timeout_id_t blink_timeout_id; 675 int initting; /* 1 is TRUE , 0 is FALSE , used to mask intrs */ 676 boolean_t shutdown; /* TRUE = power off in error event */ 677 678 }; 679 680 #endif /* _KERNEL */ 681 682 #ifdef __cplusplus 683 } 684 #endif 685 686 #endif /* _SYS_ENVCTRL_UE450_H */ 687