xref: /titanic_41/usr/src/uts/sun4u/starcat/sys/schpc_msg.h (revision aac517695f87c6b55a5fefa5a14da8c270097ef4)
1*03831d35Sstevel /*
2*03831d35Sstevel  * CDDL HEADER START
3*03831d35Sstevel  *
4*03831d35Sstevel  * The contents of this file are subject to the terms of the
5*03831d35Sstevel  * Common Development and Distribution License (the "License").
6*03831d35Sstevel  * You may not use this file except in compliance with the License.
7*03831d35Sstevel  *
8*03831d35Sstevel  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9*03831d35Sstevel  * or http://www.opensolaris.org/os/licensing.
10*03831d35Sstevel  * See the License for the specific language governing permissions
11*03831d35Sstevel  * and limitations under the License.
12*03831d35Sstevel  *
13*03831d35Sstevel  * When distributing Covered Code, include this CDDL HEADER in each
14*03831d35Sstevel  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15*03831d35Sstevel  * If applicable, add the following below this CDDL HEADER, with the
16*03831d35Sstevel  * fields enclosed by brackets "[]" replaced with your own identifying
17*03831d35Sstevel  * information: Portions Copyright [yyyy] [name of copyright owner]
18*03831d35Sstevel  *
19*03831d35Sstevel  * CDDL HEADER END
20*03831d35Sstevel  */
21*03831d35Sstevel 
22*03831d35Sstevel /*
23*03831d35Sstevel  * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
24*03831d35Sstevel  * Use is subject to license terms.
25*03831d35Sstevel  */
26*03831d35Sstevel 
27*03831d35Sstevel #ifndef _SYS_SCHPC_MSG_H
28*03831d35Sstevel #define	_SYS_SCHPC_MSG_H
29*03831d35Sstevel 
30*03831d35Sstevel /*
31*03831d35Sstevel  * This header file describes the messages that are sent between the
32*03831d35Sstevel  * schpc Hot Plug Controller Driver running on the domain and the System
33*03831d35Sstevel  * Controller.
34*03831d35Sstevel  */
35*03831d35Sstevel 
36*03831d35Sstevel #ifdef	__cplusplus
37*03831d35Sstevel extern "C" {
38*03831d35Sstevel #endif
39*03831d35Sstevel 
40*03831d35Sstevel /*
41*03831d35Sstevel  * Format of the Get Slot Status specific part of
42*03831d35Sstevel  * PCI Hot Plug message.
43*03831d35Sstevel  */
44*03831d35Sstevel typedef struct {
45*03831d35Sstevel 	uint16_t	slot_power_on 		:1, /* Slot Power is on */
46*03831d35Sstevel 			slot_powergood		:1, /* Slot Power is good */
47*03831d35Sstevel 			slot_powerfault		:1, /* Slot Power has faulted */
48*03831d35Sstevel 			slot_empty		:1, /* No occupant in slot */
49*03831d35Sstevel 			slot_freq_cap		:2, /* Slot's Freq Capability */
50*03831d35Sstevel 			slot_freq_setting	:2, /* Slot Freq setting */
51*03831d35Sstevel 			slot_condition		:2, /* Condition of slot */
52*03831d35Sstevel 			slot_HEALTHY		:1, /* Value of HEALTHY# sig */
53*03831d35Sstevel 			slot_ENUM		:1, /* Value of ENUM# sig */
54*03831d35Sstevel 			slot_mode_cap		:1, /* Conven or PCI-X */
55*03831d35Sstevel 			slot_mode_setting	:1, /* Conven or PCI-X */
56*03831d35Sstevel 			reserved		:2;
57*03831d35Sstevel 	uint8_t		slot_replystatus;
58*03831d35Sstevel } pci_getslot_t;
59*03831d35Sstevel 
60*03831d35Sstevel /*
61*03831d35Sstevel  * Format of the Set Slot Status specific part of
62*03831d35Sstevel  * PCI Hot Plug message.
63*03831d35Sstevel  */
64*03831d35Sstevel typedef struct {
65*03831d35Sstevel 	uint16_t	slot_power_on		:1, /* Connect Slot to bus */
66*03831d35Sstevel 			slot_power_off		:1, /* Disconnect from bus */
67*03831d35Sstevel 			slot_led_power		:2, /* Slot Power LED */
68*03831d35Sstevel 			slot_led_service	:2, /* OK To Remove LED */
69*03831d35Sstevel 			slot_led_fault		:2, /* Fault LED */
70*03831d35Sstevel 			slot_disable_ENUM	:1, /* Disable ENUM Event */
71*03831d35Sstevel 			slot_enable_ENUM	:1, /* Enable ENUM Event */
72*03831d35Sstevel 			slot_disable_HEALTHY	:1, /* Disable HEALTHY EVENT */
73*03831d35Sstevel 			slot_enable_HEALTHY	:1, /* Enable HEALTHY EVENT */
74*03831d35Sstevel 			reserved		:4;
75*03831d35Sstevel 	uint8_t		slot_replystatus;
76*03831d35Sstevel } pci_setslot_t;
77*03831d35Sstevel 
78*03831d35Sstevel /*
79*03831d35Sstevel  * Format of the Slot Event specific part of
80*03831d35Sstevel  * the PCI Hot Plug message.
81*03831d35Sstevel  */
82*03831d35Sstevel typedef struct {
83*03831d35Sstevel 	uint16_t	slot_power		:1, /* Slot Power has changed */
84*03831d35Sstevel 			slot_presence		:1, /* occupant has been    */
85*03831d35Sstevel 						    /* inserted or removed  */
86*03831d35Sstevel 			slot_ENUM		:1, /* ENUM# has changed */
87*03831d35Sstevel 			slot_HEALTHY		:1, /* HEALTHY# has changed */
88*03831d35Sstevel 			slot_powergood		:1, /* Power is good */
89*03831d35Sstevel 			slot_powerfault		:1, /* Power has faulted */
90*03831d35Sstevel 			reserved		:10;
91*03831d35Sstevel } pci_slotevent_t;
92*03831d35Sstevel 
93*03831d35Sstevel /*
94*03831d35Sstevel  * PCI Hot Plug message
95*03831d35Sstevel  */
96*03831d35Sstevel typedef struct {
97*03831d35Sstevel 	uint8_t		pcimsg_node;
98*03831d35Sstevel 	uint8_t		pcimsg_board;
99*03831d35Sstevel 	uint8_t		pcimsg_slot;
100*03831d35Sstevel 	uint8_t		pcimsg_revision;
101*03831d35Sstevel 	uint8_t		pcimsg_command;
102*03831d35Sstevel 	union {
103*03831d35Sstevel 		pci_setslot_t	pcimsg_setslot;
104*03831d35Sstevel 		pci_getslot_t	pcimsg_getslot;
105*03831d35Sstevel 		pci_slotevent_t	pcimsg_slotevent;
106*03831d35Sstevel 	} pcimsg_type;
107*03831d35Sstevel } pcimsg_t;
108*03831d35Sstevel 
109*03831d35Sstevel /*
110*03831d35Sstevel  * Keys for the outgoing and incoming mailboxes
111*03831d35Sstevel  */
112*03831d35Sstevel #define	KEY_PCSC	0x50435343	/* Outgoing Mailbox 'PCSC' */
113*03831d35Sstevel #define	KEY_SCPC	0x53435043	/* Incoming Mailbox 'SCPC' */
114*03831d35Sstevel 
115*03831d35Sstevel /*
116*03831d35Sstevel  * default timeout in seconds for mboxsc_getmsg calls
117*03831d35Sstevel  */
118*03831d35Sstevel #define	PCSC_TIMEOUT	30
119*03831d35Sstevel 
120*03831d35Sstevel /* Commands */
121*03831d35Sstevel #define	PCIMSG_GETSLOTSTATUS	0x1
122*03831d35Sstevel #define	PCIMSG_SETSLOTSTATUS	0x2
123*03831d35Sstevel #define	PCIMSG_SLOTEVENT	0x3
124*03831d35Sstevel 
125*03831d35Sstevel /* Message Revisions */
126*03831d35Sstevel #define	PCIMSG_REVISION		0x10
127*03831d35Sstevel #define	PCIMSG_REVISION_1_0	0x10
128*03831d35Sstevel 
129*03831d35Sstevel /*
130*03831d35Sstevel  * Values for the slot_condition field of the get slot status command.
131*03831d35Sstevel  */
132*03831d35Sstevel #define	PCIMSG_SLOTCOND_UNKNOWN		0x0
133*03831d35Sstevel #define	PCIMSG_SLOTCOND_GOOD		0x1
134*03831d35Sstevel #define	PCIMSG_SLOTCOND_REC_FAIL	0x2
135*03831d35Sstevel #define	PCIMSG_SLOTCOND_OCC_FAIL	0x3
136*03831d35Sstevel 
137*03831d35Sstevel /*
138*03831d35Sstevel  * Values for the slot_freq_cap and slot_freq_setting fields of the get
139*03831d35Sstevel  * slot status command.
140*03831d35Sstevel  */
141*03831d35Sstevel #define	PCIMSG_FREQ_33MHZ	0x0
142*03831d35Sstevel #define	PCIMSG_FREQ_66MHZ	0x1
143*03831d35Sstevel #define	PCIMSG_FREQ_90MHZ	0x2
144*03831d35Sstevel #define	PCIMSG_FREQ_133MHZ	0x3
145*03831d35Sstevel 
146*03831d35Sstevel /*
147*03831d35Sstevel  * Values for the slot_mode_cap and slot_mode_setting of the get
148*03831d35Sstevel  * slot status command.
149*03831d35Sstevel  */
150*03831d35Sstevel #define	PCIMSG_MODE_CONVEN	0x0
151*03831d35Sstevel #define	PCIMSG_MODE_PCIX	0x1
152*03831d35Sstevel 
153*03831d35Sstevel /*
154*03831d35Sstevel  * Values for the PRSNT signals.
155*03831d35Sstevel  */
156*03831d35Sstevel #define	PCIMSG_PRSNT_NOADAPTER	0x0
157*03831d35Sstevel #define	PCIMSG_PRSNT_25W	0x1
158*03831d35Sstevel #define	PCIMSG_PRSNT_15W	0x2
159*03831d35Sstevel #define	PCIMSG_PRSNT_7_5W	0x3
160*03831d35Sstevel 
161*03831d35Sstevel /*
162*03831d35Sstevel  * Values to turn on and off slot characteristics.
163*03831d35Sstevel  */
164*03831d35Sstevel #define	PCIMSG_ON		0x1
165*03831d35Sstevel #define	PCIMSG_OFF		0x0
166*03831d35Sstevel 
167*03831d35Sstevel /*
168*03831d35Sstevel  * Values to set the power, service and fault LEDs
169*03831d35Sstevel  */
170*03831d35Sstevel #define	PCIMSG_LED_OFF		0x00
171*03831d35Sstevel #define	PCIMSG_LED_ON		0x01
172*03831d35Sstevel #define	PCIMSG_LED_FLASH	0x02
173*03831d35Sstevel 
174*03831d35Sstevel /*
175*03831d35Sstevel  * Return values for the slot_replystatus field for the get/set slot status
176*03831d35Sstevel  * commands.
177*03831d35Sstevel  */
178*03831d35Sstevel #define	PCIMSG_REPLY_GOOD	0x0
179*03831d35Sstevel #define	PCIMSG_REPLY_FAIL	0x1
180*03831d35Sstevel 
181*03831d35Sstevel #ifdef __cplusplus
182*03831d35Sstevel }
183*03831d35Sstevel #endif
184*03831d35Sstevel 
185*03831d35Sstevel #endif /* _SYS_SCHPC_MSG_H */
186