1*03831d35Sstevel /* 2*03831d35Sstevel * CDDL HEADER START 3*03831d35Sstevel * 4*03831d35Sstevel * The contents of this file are subject to the terms of the 5*03831d35Sstevel * Common Development and Distribution License (the "License"). 6*03831d35Sstevel * You may not use this file except in compliance with the License. 7*03831d35Sstevel * 8*03831d35Sstevel * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*03831d35Sstevel * or http://www.opensolaris.org/os/licensing. 10*03831d35Sstevel * See the License for the specific language governing permissions 11*03831d35Sstevel * and limitations under the License. 12*03831d35Sstevel * 13*03831d35Sstevel * When distributing Covered Code, include this CDDL HEADER in each 14*03831d35Sstevel * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*03831d35Sstevel * If applicable, add the following below this CDDL HEADER, with the 16*03831d35Sstevel * fields enclosed by brackets "[]" replaced with your own identifying 17*03831d35Sstevel * information: Portions Copyright [yyyy] [name of copyright owner] 18*03831d35Sstevel * 19*03831d35Sstevel * CDDL HEADER END 20*03831d35Sstevel */ 21*03831d35Sstevel 22*03831d35Sstevel /* 23*03831d35Sstevel * Copyright 2000 Sun Microsystems, Inc. All rights reserved. 24*03831d35Sstevel * Use is subject to license terms. 25*03831d35Sstevel */ 26*03831d35Sstevel 27*03831d35Sstevel #ifndef _SYS_IOSRAMVAR_H 28*03831d35Sstevel #define _SYS_IOSRAMVAR_H 29*03831d35Sstevel 30*03831d35Sstevel #pragma ident "%Z%%M% %I% %E% SMI" 31*03831d35Sstevel 32*03831d35Sstevel #ifdef __cplusplus 33*03831d35Sstevel extern "C" { 34*03831d35Sstevel #endif 35*03831d35Sstevel 36*03831d35Sstevel 37*03831d35Sstevel /* 38*03831d35Sstevel * Data sizes used by the original author 39*03831d35Sstevel */ 40*03831d35Sstevel #ifndef UINT32SZ 41*03831d35Sstevel #define UINT32SZ sizeof (uint32_t) 42*03831d35Sstevel #define UINT64SZ sizeof (uint64_t) 43*03831d35Sstevel #endif 44*03831d35Sstevel 45*03831d35Sstevel /* 46*03831d35Sstevel * Values used for tunnel switching 47*03831d35Sstevel */ 48*03831d35Sstevel #define OBP_TSWITCH_REQREPLY 0 /* request reply from SSC */ 49*03831d35Sstevel #define OBP_TSWITCH_NOREPLY 1 /* don't wait for reply */ 50*03831d35Sstevel #define IOSRAM_TSWITCH_RETRY 20 /* # of times to wait for */ 51*03831d35Sstevel /* current tunnel switch to */ 52*03831d35Sstevel /* end when starting a new */ 53*03831d35Sstevel /* one */ 54*03831d35Sstevel /* 55*03831d35Sstevel * When performing back-to-back tunnel switches, we have to make sure that 56*03831d35Sstevel * HWAD (the SC-side implementation) has time to find the new tunnel from 57*03831d35Sstevel * one switch before we invalidate it for the next switch. To ensure that, 58*03831d35Sstevel * we make sure that the time between consecutive tunnel switches is at 59*03831d35Sstevel * least twice the polling rate HWAD uses to detect the new tunnel. 60*03831d35Sstevel */ 61*03831d35Sstevel #define IOSRAM_TSWITCH_DELAY_US 100000 62*03831d35Sstevel 63*03831d35Sstevel /* 64*03831d35Sstevel * Values used for hash table maintenance 65*03831d35Sstevel */ 66*03831d35Sstevel #define IOSRAM_HASHSZ 0x20 /* # hash entries */ 67*03831d35Sstevel #define IOSRAM_HASH(key) ((((key) >> 24) ^ ((key) >> 16) ^\ 68*03831d35Sstevel ((key) >> 9) ^ (key)) & (IOSRAM_HASHSZ - 1)) 69*03831d35Sstevel 70*03831d35Sstevel /* 71*03831d35Sstevel * A pair of flags is associated with each IOSRAM chunk in the IOSRAM TOC. 72*03831d35Sstevel * These flags are stored sequentially in the "SC Domain Communication Data" 73*03831d35Sstevel * ('SDCD') IOSRAM chunk. The data-valid/int-pending flags are one byte each 74*03831d35Sstevel * and stored sequentially with data-valid flag being the first. The following 75*03831d35Sstevel * macros define the offset of the flags for each IOSRAM chunk based upon its 76*03831d35Sstevel * location (index) in the IOSRAM TOC. 77*03831d35Sstevel */ 78*03831d35Sstevel #define IOSRAM_DATAVALID_FLAGOFF(index) (2 * (index)) 79*03831d35Sstevel #define IOSRAM_INTPENDING_FLAGOFF(index) (2 * (index) + 1) 80*03831d35Sstevel 81*03831d35Sstevel /* 82*03831d35Sstevel * IOSRAM node properties (per IOSRAM node) 83*03831d35Sstevel */ 84*03831d35Sstevel #define IOSRAM_REG_PROP "reg" 85*03831d35Sstevel #define IOSRAM_TUNNELOK_PROP "tunnel-capable" 86*03831d35Sstevel 87*03831d35Sstevel /* 88*03831d35Sstevel * Other IOSRAM properties (on chosen node and parent hierarchy) 89*03831d35Sstevel */ 90*03831d35Sstevel #define IOSRAM_CHOSEN_PROP "iosram" 91*03831d35Sstevel #define IOSRAM_PORTID_PROP "portid" 92*03831d35Sstevel 93*03831d35Sstevel /* 94*03831d35Sstevel * Interrupt priority (PIL) used for IOSRAM interrupts. The value 5 was 95*03831d35Sstevel * chosen somewhat arbitrarily based on the fact that it is higher than 96*03831d35Sstevel * disks and lower than networks. 97*03831d35Sstevel */ 98*03831d35Sstevel #define IOSRAM_PIL 5 99*03831d35Sstevel 100*03831d35Sstevel /* 101*03831d35Sstevel * IOSRAM header structure, located at the beginning of IOSRAM. 102*03831d35Sstevel * 103*03831d35Sstevel * NOTE - New fields may be appended to this structure, but no existing fields 104*03831d35Sstevel * may be altered in any way!!! 105*03831d35Sstevel */ 106*03831d35Sstevel typedef struct { 107*03831d35Sstevel uint32_t status; 108*03831d35Sstevel uint32_t version; 109*03831d35Sstevel uint32_t toc_offset; 110*03831d35Sstevel uint32_t sms_mbox_version; 111*03831d35Sstevel uint32_t os_mbox_version; 112*03831d35Sstevel uint32_t obp_mbox_version; 113*03831d35Sstevel uint32_t sms_change_mask; 114*03831d35Sstevel uint32_t os_change_mask; 115*03831d35Sstevel } iosram_hdr_t; 116*03831d35Sstevel 117*03831d35Sstevel /* 118*03831d35Sstevel * Values for the status field 119*03831d35Sstevel */ 120*03831d35Sstevel #define IOSRAM_INVALID 0x494e5644 /* 'INVD' */ 121*03831d35Sstevel #define IOSRAM_VALID 0x56414c44 /* 'VALD' */ 122*03831d35Sstevel #define IOSRAM_INTRANSIT 0x494e5452 /* 'INTR' */ 123*03831d35Sstevel 124*03831d35Sstevel /* 125*03831d35Sstevel * Maximum IOSRAM Protocol version understood by this implementation 126*03831d35Sstevel */ 127*03831d35Sstevel #define IOSRAM_MAX_PROTOCOL_VERSION 1 128*03831d35Sstevel 129*03831d35Sstevel /* 130*03831d35Sstevel * Bit definitions for *_change_mask fields 131*03831d35Sstevel */ 132*03831d35Sstevel #define IOSRAM_HDRFIELD_SMS_MBOX_VER 0x00000001 133*03831d35Sstevel #define IOSRAM_HDRFIELD_OS_MBOX_VER 0x00000002 134*03831d35Sstevel #define IOSRAM_HDRFIELD_TOC_INDEX 0x00000004 135*03831d35Sstevel 136*03831d35Sstevel /* 137*03831d35Sstevel * Macros used to access fields in the header 138*03831d35Sstevel */ 139*03831d35Sstevel #define IOSRAM_GET_HDRFIELD32(softp, field) \ 140*03831d35Sstevel (ddi_get32((softp)->handle, &((iosram_hdr_t *)(softp)->iosramp)->field)) 141*03831d35Sstevel #define IOSRAM_SET_HDRFIELD32(softp, field, val) \ 142*03831d35Sstevel (ddi_put32((softp)->handle, &((iosram_hdr_t *)(softp)->iosramp)->field,\ 143*03831d35Sstevel (val))) 144*03831d35Sstevel 145*03831d35Sstevel /* 146*03831d35Sstevel * IOSRAM contains various data chunks and the key, location and size of 147*03831d35Sstevel * each IOSRAM chunk is communicated to the IOSRAM driver in the form of a 148*03831d35Sstevel * Table of Contents. This structre contains one entry for each IOSRAM 149*03831d35Sstevel * chunk, as well as an initial index entry. Each entry has the following 150*03831d35Sstevel * structure. 151*03831d35Sstevel * 152*03831d35Sstevel * NOTE - Although the unused field may be renamed for some use in the future, 153*03831d35Sstevel * no other modification to this structure is allowed!!! 154*03831d35Sstevel */ 155*03831d35Sstevel 156*03831d35Sstevel typedef struct { 157*03831d35Sstevel uint32_t key; /* IOSRAM chunk key */ 158*03831d35Sstevel uint32_t off; /* IOSRAM chunk starting offset */ 159*03831d35Sstevel uint32_t len; /* IOSRAM chunk length */ 160*03831d35Sstevel uint32_t unused; /* currently unused */ 161*03831d35Sstevel } iosram_toc_entry_t; 162*03831d35Sstevel 163*03831d35Sstevel /* 164*03831d35Sstevel * Special values used in some TOC entries 165*03831d35Sstevel */ 166*03831d35Sstevel #define IOSRAM_FLAGS_KEY 0x53444344 /* 'SDCD' - flags chunk key */ 167*03831d35Sstevel #define IOSRAM_INDEX_KEY 0x494e4458 /* 'INDX' - index entry key */ 168*03831d35Sstevel #define IOSRAM_INDEX_OFF 0xFFFFFFFF /* index entry offset */ 169*03831d35Sstevel 170*03831d35Sstevel 171*03831d35Sstevel /* 172*03831d35Sstevel * IOSRAM flags structure. An array of these - one for every IOSRAM chunk - is 173*03831d35Sstevel * stored in the SDCD chunk. 174*03831d35Sstevel */ 175*03831d35Sstevel typedef struct { 176*03831d35Sstevel uint8_t data_valid; 177*03831d35Sstevel uint8_t int_pending; 178*03831d35Sstevel } iosram_flags_t; 179*03831d35Sstevel 180*03831d35Sstevel /* 181*03831d35Sstevel * IOSRAM callback data structure 182*03831d35Sstevel */ 183*03831d35Sstevel typedef struct { 184*03831d35Sstevel uchar_t busy; /* cback handler is active/busy */ 185*03831d35Sstevel uchar_t unregister; /* delayed callback unregistration */ 186*03831d35Sstevel void (*handler)(); /* cback handler */ 187*03831d35Sstevel void *arg; /* cback handler arg */ 188*03831d35Sstevel } iosram_cback_t; 189*03831d35Sstevel 190*03831d35Sstevel 191*03831d35Sstevel /* 192*03831d35Sstevel * IOSRAM per chunk state 193*03831d35Sstevel */ 194*03831d35Sstevel typedef struct iosram_chunk { 195*03831d35Sstevel iosram_toc_entry_t toc_data; /* Data from TOC entry */ 196*03831d35Sstevel iosram_cback_t cback; /* callback info */ 197*03831d35Sstevel uint8_t *basep; /* kvaddr for this IOSRAM chunk */ 198*03831d35Sstevel iosram_flags_t *flagsp; 199*03831d35Sstevel struct iosram_chunk *hash; /* next entry in the hash list */ 200*03831d35Sstevel } iosram_chunk_t; 201*03831d35Sstevel 202*03831d35Sstevel 203*03831d35Sstevel /* 204*03831d35Sstevel * IOSRAM per instance state 205*03831d35Sstevel */ 206*03831d35Sstevel 207*03831d35Sstevel typedef struct iosramsoft { 208*03831d35Sstevel struct iosramsoft *prev; /* ptr for linked list */ 209*03831d35Sstevel struct iosramsoft *next; /* ptr for linked list */ 210*03831d35Sstevel 211*03831d35Sstevel boolean_t suspended; /* TRUE if driver suspended */ 212*03831d35Sstevel int instance; /* driver instance number */ 213*03831d35Sstevel dev_info_t *dip; /* device information */ 214*03831d35Sstevel 215*03831d35Sstevel uchar_t *iosramp; /* IOSRAM mapped vaddr */ 216*03831d35Sstevel int iosramlen; /* IOSRAM length */ 217*03831d35Sstevel int nchunks; /* # IOSRAM chunks */ 218*03831d35Sstevel iosram_chunk_t *chunks; /* ptr to iosram_chunk array */ 219*03831d35Sstevel iosram_chunk_t *flags_chunk; /* ptr to flags chunk */ 220*03831d35Sstevel ddi_acc_handle_t handle; /* IOSRAM map handle */ 221*03831d35Sstevel 222*03831d35Sstevel ddi_iblock_cookie_t real_iblk; /* real intr iblock cookie */ 223*03831d35Sstevel ddi_iblock_cookie_t soft_iblk; /* soft intr iblock cookie */ 224*03831d35Sstevel ddi_softintr_t softintr_id; /* soft interrupt ID */ 225*03831d35Sstevel ushort_t intr_busy; /* softintr handler busy */ 226*03831d35Sstevel ushort_t intr_pending; /* interrupt pending */ 227*03831d35Sstevel 228*03831d35Sstevel int state; /* IOSRAM state (see below) */ 229*03831d35Sstevel int portid; /* Card port ID for tswitch */ 230*03831d35Sstevel uint32_t tswitch_ok; /* # successful tunnel switch */ 231*03831d35Sstevel uint32_t tswitch_fail; /* # failed tunnel switch */ 232*03831d35Sstevel 233*03831d35Sstevel ddi_acc_handle_t sbbc_handle; /* SBBC regs map handle */ 234*03831d35Sstevel iosram_sbbc_region_t *sbbc_region; /* region of SBBC registers */ 235*03831d35Sstevel uint32_t int_enable_sav; /* save int enable reg. on suspend */ 236*03831d35Sstevel kmutex_t intr_mutex; /* real interrupt handler mutex */ 237*03831d35Sstevel } iosramsoft_t; 238*03831d35Sstevel 239*03831d35Sstevel 240*03831d35Sstevel /* IOSRAM state value */ 241*03831d35Sstevel #define IOSRAM_STATE_INIT 0x0001 /* initialization */ 242*03831d35Sstevel #define IOSRAM_STATE_SLAVE 0x0002 /* SLAVE IOSRAM */ 243*03831d35Sstevel #define IOSRAM_STATE_MASTER 0x0004 /* MASTER IOSRAM */ 244*03831d35Sstevel #define IOSRAM_STATE_MAPPED 0x0008 /* IOSRAM mapped */ 245*03831d35Sstevel 246*03831d35Sstevel #define IOSRAM_STATE_TSWITCH 0x0010 /* tunnel switch source/target */ 247*03831d35Sstevel #define IOSRAM_STATE_DETACH 0x0020 /* IOSRAM instance being detached */ 248*03831d35Sstevel 249*03831d35Sstevel 250*03831d35Sstevel #if DEBUG 251*03831d35Sstevel #define IOSRAM_STATS 1 /* enable IOSRAM statistics */ 252*03831d35Sstevel #define IOSRAM_LOG 1 /* enable IOSRAM logging */ 253*03831d35Sstevel #endif 254*03831d35Sstevel 255*03831d35Sstevel #if IOSRAM_STATS 256*03831d35Sstevel 257*03831d35Sstevel /* 258*03831d35Sstevel * IOSRAM statistics 259*03831d35Sstevel */ 260*03831d35Sstevel struct iosram_stat { 261*03831d35Sstevel uint32_t read; /* calls to iosram_read */ 262*03831d35Sstevel uint32_t write; /* calls to iosram_{force_}write */ 263*03831d35Sstevel uint32_t getflag; /* calls to iosram_getflag */ 264*03831d35Sstevel uint32_t setflag; /* calls to iosram_getflag */ 265*03831d35Sstevel uint32_t tswitch; /* # tunnel switch */ 266*03831d35Sstevel uint32_t callbacks; /* # callbacks invoked */ 267*03831d35Sstevel uint32_t intr_recv; /* # interrupts received */ 268*03831d35Sstevel uint32_t sintr_recv; /* # softintr received */ 269*03831d35Sstevel uint32_t intr_send; /* # interrupts sent */ 270*03831d35Sstevel uint64_t bread; /* # bytes read */ 271*03831d35Sstevel uint64_t bwrite; /* # bytes written */ 272*03831d35Sstevel }; 273*03831d35Sstevel 274*03831d35Sstevel #define IOSRAM_STAT(field) iosram_stats.field++ 275*03831d35Sstevel #define IOSRAM_STAT_ADD(field, amount) iosram_stats.field += (uint64_t)amount 276*03831d35Sstevel #define IOSRAM_STAT_SET(field, count) iosram_stats.field = (uint64_t)count 277*03831d35Sstevel 278*03831d35Sstevel #else /* !IOSRAM_STATS */ 279*03831d35Sstevel 280*03831d35Sstevel #define IOSRAM_STAT(field) 281*03831d35Sstevel #define IOSRAM_STAT_ADD(field, amount) 282*03831d35Sstevel #define IOSRAM_STAT_SET(field, count) 283*03831d35Sstevel 284*03831d35Sstevel #endif /* !IOSRAM_STATS */ 285*03831d35Sstevel 286*03831d35Sstevel 287*03831d35Sstevel #if IOSRAM_LOG 288*03831d35Sstevel 289*03831d35Sstevel /* 290*03831d35Sstevel * IOSRAM log related structures and extern declarations 291*03831d35Sstevel */ 292*03831d35Sstevel 293*03831d35Sstevel #define IOSRAM_MAXLOG 64 294*03831d35Sstevel 295*03831d35Sstevel typedef struct { 296*03831d35Sstevel uint32_t seq; /* logseg# */ 297*03831d35Sstevel clock_t tstamp; /* time stamp */ 298*03831d35Sstevel caddr_t fmt; /* format ptr */ 299*03831d35Sstevel intptr_t arg1; /* first arg */ 300*03831d35Sstevel intptr_t arg2; /* second arg */ 301*03831d35Sstevel intptr_t arg3; /* third arg */ 302*03831d35Sstevel intptr_t arg4; /* fourth arg */ 303*03831d35Sstevel } iosram_log_t; 304*03831d35Sstevel 305*03831d35Sstevel #define IOSRAMLOG(level, fmt, a1, a2, a3, a4) \ 306*03831d35Sstevel if (iosram_log_level >= level) { \ 307*03831d35Sstevel iosram_log(fmt, (intptr_t)a1, (intptr_t)a2, \ 308*03831d35Sstevel (intptr_t)a3, (intptr_t)a4); \ 309*03831d35Sstevel } 310*03831d35Sstevel 311*03831d35Sstevel extern int iosram_log_level; 312*03831d35Sstevel extern uint32_t iosram_logseq; 313*03831d35Sstevel extern iosram_log_t iosram_logbuf[IOSRAM_MAXLOG]; 314*03831d35Sstevel extern void iosram_log(caddr_t, intptr_t, intptr_t, intptr_t, intptr_t); 315*03831d35Sstevel 316*03831d35Sstevel #else /* !IOSRAM_LOG */ 317*03831d35Sstevel 318*03831d35Sstevel #define IOSRAMLOG(level, fmt, a1, a2, a3, a4) 319*03831d35Sstevel 320*03831d35Sstevel #endif /* !IOSRAM_LOG */ 321*03831d35Sstevel 322*03831d35Sstevel 323*03831d35Sstevel #ifdef __cplusplus 324*03831d35Sstevel } 325*03831d35Sstevel #endif 326*03831d35Sstevel 327*03831d35Sstevel #endif /* _SYS_IOSRAMVAR_H */ 328