1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/types.h> 30 #include <sys/machsystm.h> 31 #include <sys/x_call.h> 32 #include <sys/cmp.h> 33 #include <sys/debug.h> 34 #include <sys/chip.h> 35 #include <sys/cheetahregs.h> 36 37 /* 38 * Note: We assume that chipid == portid. This is not necessarily true. 39 * We buried it down here in the implementation, and not in the 40 * interfaces, so that we can change it later. 41 */ 42 43 /* 44 * pre-alloc'ed because this is used early in boot (before the memory 45 * allocator is available). 46 */ 47 static cpuset_t chips[MAX_CPU_CHIPID]; 48 49 /* 50 * Returns 1 if cpuid is CMP-capable, 0 otherwise. 51 */ 52 int 53 cmp_cpu_is_cmp(processorid_t cpuid) 54 { 55 chipid_t chipid; 56 57 /* N.B. We're assuming that the cpunode[].portid is still intact */ 58 chipid = cpunodes[cpuid].portid; 59 return (!CPUSET_ISNULL(chips[chipid])); 60 } 61 62 /* 63 * Indicate that this core (cpuid) resides on the chip indicated by chipid. 64 * Called during boot and DR add. 65 */ 66 void 67 cmp_add_cpu(chipid_t chipid, processorid_t cpuid) 68 { 69 CPUSET_ADD(chips[chipid], cpuid); 70 } 71 72 /* 73 * Indicate that this core (cpuid) is being DR removed. 74 */ 75 void 76 cmp_delete_cpu(processorid_t cpuid) 77 { 78 chipid_t chipid; 79 80 /* N.B. We're assuming that the cpunode[].portid is still intact */ 81 chipid = cpunodes[cpuid].portid; 82 CPUSET_DEL(chips[chipid], cpuid); 83 } 84 85 /* 86 * Called when cpuid is being onlined or offlined. If the offlined 87 * processor is CMP-capable then current target of the CMP Error Steering 88 * Register is set to either the lowest numbered on-line sibling core, if 89 * one exists, or else to this core. 90 */ 91 void 92 cmp_error_resteer(processorid_t cpuid) 93 { 94 cpuset_t mycores; 95 cpu_t *cpu; 96 chipid_t chipid; 97 int i; 98 99 if (!cmp_cpu_is_cmp(cpuid)) 100 return; 101 102 ASSERT(MUTEX_HELD(&cpu_lock)); 103 chipid = cpunodes[cpuid].portid; 104 mycores = chips[chipid]; 105 106 /* Look for an online sibling core */ 107 for (i = 0; i < NCPU; i++) { 108 if (i == cpuid) 109 continue; 110 111 if (CPU_IN_SET(mycores, i) && 112 (cpu = cpu_get(i)) != NULL && cpu_is_active(cpu)) { 113 /* Found one, reset error steering */ 114 xc_one(i, (xcfunc_t *)set_cmp_error_steering, 0, 0); 115 break; 116 } 117 } 118 119 /* No online sibling cores, point to this core. */ 120 if (i == NCPU) { 121 xc_one(cpuid, (xcfunc_t *)set_cmp_error_steering, 0, 0); 122 } 123 } 124 125 chipid_t 126 cmp_cpu_to_chip(processorid_t cpuid) 127 { 128 if (!cmp_cpu_is_cmp(cpuid)) { 129 /* This CPU is not a CMP, so by definition chipid==cpuid */ 130 ASSERT(cpuid < MAX_CPU_CHIPID && CPUSET_ISNULL(chips[cpuid])); 131 return (cpuid); 132 } 133 134 /* N.B. We're assuming that the cpunode[].portid is still intact */ 135 return (cpunodes[cpuid].portid); 136 } 137 138 /* 139 * Return a chip "id" for the given cpu_t 140 * cpu_t's residing on the same physical processor 141 * should map to the same "id" 142 */ 143 chipid_t 144 chip_plat_get_chipid(cpu_t *cp) 145 { 146 return (cmp_cpu_to_chip(cp->cpu_id)); 147 } 148 149 /* 150 * We don't have any multi-threaded cores on sun4u yet. 151 */ 152 id_t 153 chip_plat_get_coreid(cpu_t *cp) 154 { 155 return (cp->cpu_id); 156 } 157 158 void 159 chip_plat_define_chip(cpu_t *cp, chip_def_t *cd) 160 { 161 int impl; 162 163 /* 164 * Define the chip's type 165 */ 166 impl = cpunodes[cp->cpu_id].implementation; 167 168 if (IS_JAGUAR(impl)) { 169 cd->chipd_type = CHIP_CMP_SPLIT_CACHE; 170 } else if (IS_PANTHER(impl)) { 171 cd->chipd_type = CHIP_CMP_SHARED_CACHE; 172 } else { 173 cd->chipd_type = CHIP_DEFAULT; 174 } 175 176 /* 177 * Define any needed adjustment of rechoose_interval 178 * For now, all chips use the default. This 179 * will change with future processors. 180 */ 181 cd->chipd_rechoose_adj = 0; 182 } 183