1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_OPL_HWDESC_H 27 #define _SYS_OPL_HWDESC_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /* 36 * Hardware Descriptor. 37 */ 38 39 #define HWD_SBS_PER_DOMAIN 32 /* System boards per domain */ 40 #define HWD_CPUS_PER_CORE 4 /* Strands per physical core */ 41 #define HWD_CORES_PER_CPU_CHIP 4 /* Cores per processor chip */ 42 #define HWD_CPU_CHIPS_PER_CMU 4 /* Processor chips per CMU */ 43 #define HWD_SCS_PER_CMU 4 /* System controllers per CMU */ 44 #define HWD_DIMMS_PER_CMU 32 /* Memory DIMMs per CMU */ 45 #define HWD_IOCS_PER_IOU 2 /* Oberon chips per I/O unit */ 46 #define HWD_PCI_CHANNELS_PER_IOC 2 /* PCI channels per Oberon chip */ 47 #define HWD_LEAVES_PER_PCI_CHANNEL 2 /* Leaves per PCI channel */ 48 #define HWD_PCI_CHANNELS_PER_SB 4 /* PCI channels per system board */ 49 #define HWD_CMU_CHANNEL 4 /* CMU channel number */ 50 #define HWD_IO_BOATS_PER_IOU 6 /* I/O boats per I/O unit */ 51 #define HWD_BANKS_PER_CMU 8 /* Memory banks per CMU */ 52 #define HWD_MAX_MEM_CHUNKS 8 /* Chunks per board */ 53 54 typedef uint32_t hwd_stat_t; /* component status */ 55 56 /* 57 * Values for hwd_stat_t. 58 */ 59 #define HWD_STAT_UNKNOWN 0x0000 /* No status yet */ 60 #define HWD_STAT_PRESENT 0x0001 /* Present */ 61 #define HWD_STAT_MISS 0x0002 /* Missing */ 62 #define HWD_STAT_MISCONFIG 0x0003 /* Misconfigured */ 63 #define HWD_STAT_PASS 0x0004 /* Ok */ 64 #define HWD_STAT_FAIL 0x0080 /* Failed by XSCF */ 65 #define HWD_STAT_FAIL_OBP 0x0081 /* Failed by POST/OBP */ 66 #define HWD_STAT_FAIL_OS 0x0082 /* Failed by OS */ 67 68 #define HWD_STAT_FAILED 0x0080 69 70 #define HWD_MASK_NOT_USED 0x8000 /* If this bit is set, the component */ 71 /* is not used (even if it presents) */ 72 73 #define HWD_STATUS_FAILED(stat) ((stat) & HWD_STAT_FAILED) 74 #define HWD_STATUS_OK(stat) ((stat) == HWD_STAT_PASS) 75 #define HWD_STATUS_PRESENT(stat) \ 76 ((stat) & (HWD_STAT_PRESENT | HWD_STAT_PASS)) 77 #define HWD_STATUS_NONE(stat) \ 78 (((stat) == HWD_STAT_UNKNOWN) || ((stat) == HWD_STAT_MISS)) 79 80 #define HWD_VERSION_MAJOR 1 81 #define HWD_VERSION_MINOR 1 82 83 /* 84 * Hardware Descriptor Header. 85 * 86 * Some fields occur repeatedly in different structures: 87 * 88 * spare* This field is for future use. 89 * 90 * filler* This field is used to show alignment. This could also 91 * be used in the future for something. 92 * 93 * check_sum This contains the check sum of the structure it resides in. 94 */ 95 typedef struct { 96 uint32_t hdr_magic; /* magic code ('HWDE') */ 97 struct hwdesc_version { 98 uint16_t major; 99 uint16_t minor; 100 } hdr_version; /* structure version */ 101 102 /* 103 * Domain Identifier. The OPL system can have 104 * upto 24 domains so domain id can be 0 - 23. 105 */ 106 uint8_t hdr_domain_id; 107 char hdr_filler[3]; 108 109 /* 110 * offsets from the beginning of the header to: 111 * - SB status information (hwd_sb_status_t) 112 * - domain information (hwd_domain_info_t) 113 * - SB information (hwd_sb_info_t). 114 */ 115 uint32_t hdr_sb_status_offset; 116 uint32_t hdr_domain_info_offset; 117 uint32_t hdr_sb_info_offset; 118 119 uint32_t hdr_spare[9]; 120 uint32_t hdr_check_sum; 121 } hwd_header_t; 122 123 /* 124 * SB Status 125 */ 126 typedef struct { 127 hwd_stat_t sb_status[HWD_SBS_PER_DOMAIN]; /* status of all LSBs */ 128 uint32_t sb_spare[15]; 129 uint32_t sb_check_sum; 130 } hwd_sb_status_t; 131 132 /* 133 * SP -> Domain Information. 134 */ 135 typedef struct { 136 uint32_t dinf_reset_factor; /* domain reset reason */ 137 uint32_t dinf_host_id; /* domain unique id */ 138 uint64_t dinf_system_frequency; /* Hz */ 139 uint64_t dinf_stick_frequency; /* Hz */ 140 uint32_t dinf_scf_command_timeout; /* SCF i/f timeout seconds */ 141 uint32_t dinf_model_info; /* FF1/2 DC1/2/3 */ 142 uint8_t dinf_mac_address[6]; /* system MAC address */ 143 uint8_t dinf_filler1[10]; 144 uint8_t dinf_dr_status; /* 0: DR capable, !0: no DR */ 145 uint8_t dinf_filler2[7]; 146 /* 147 * Specification of degeneracy operation of POST by XSCF 148 * 0x00: off 149 * 0x20: component 150 * 0x40: board 151 * 0x80: system 152 */ 153 uint8_t dinf_config_policy; 154 /* 155 * Specification of diagnosis operation of POST by XSCF 156 * 0x00: off 157 * 0x20: min 158 * 0x40: max 159 */ 160 uint8_t dinf_diag_level; 161 /* 162 * Specification of boot operation of OBP by XSCF 163 * 0x00: It follows other settings. 164 * 0x80: Auto boot is not done. 165 */ 166 uint8_t dinf_boot_mode; 167 uint8_t dinf_spare1[5]; 168 int64_t dinf_cpu_start_time; /* seconds since the Epoch */ 169 char dinf_banner_name[64]; /* system banner string */ 170 char dinf_platform_token[64]; /* platform name */ 171 uint32_t dinf_floating_board_bitmap; /* bit 0 = SB0 ... */ 172 uint32_t dinf_spare2[12]; 173 uint32_t dinf_check_sum; 174 } hwd_domain_info_t; 175 176 /* 177 * CPU Strand 178 */ 179 typedef struct { 180 hwd_stat_t cpu_status; 181 char cpu_component_name[32]; 182 uint16_t cpu_cpuid; /* 0x0000, 0x0001, ... 0x01ff */ 183 uint16_t cpu_filler; 184 uint32_t cpu_spare[6]; 185 } hwd_cpu_t; 186 187 /* 188 * CPU Core 189 */ 190 typedef struct { 191 hwd_stat_t core_status; 192 char core_component_name[32]; 193 uint32_t core_filler1; 194 uint64_t core_frequency; /* Hz */ 195 uint64_t core_config; /* bus config reg */ 196 uint64_t core_version; /* processor VER */ 197 uint16_t core_manufacturer; /* VER.manuf */ 198 uint16_t core_implementation; /* VER.impl */ 199 uint8_t core_mask; /* VER.mask */ 200 uint8_t core_filler2[3]; 201 uint32_t core_l1_icache_size; 202 uint16_t core_l1_icache_line_size; 203 uint16_t core_l1_icache_associativity; 204 uint32_t core_num_itlb_entries; 205 uint32_t core_l1_dcache_size; 206 uint16_t core_l1_dcache_line_size; 207 uint16_t core_l1_dcache_associativity; 208 uint32_t core_num_dtlb_entries; 209 uint32_t core_spare1[4]; 210 uint32_t core_l2_cache_size; 211 uint16_t core_l2_cache_line_size; 212 uint16_t core_l2_cache_associativity; 213 uint32_t core_l2_cache_sharing; /* bit N:coreN */ 214 uint32_t core_spare2[5]; 215 hwd_cpu_t core_cpus[HWD_CPUS_PER_CORE]; 216 uint32_t core_spare3[4]; 217 } hwd_core_t; 218 219 /* 220 * CPU Chip 221 */ 222 typedef struct { 223 hwd_stat_t chip_status; 224 char chip_component_name[32]; /* example: "CPU#x" */ 225 char chip_fru_name[32]; /* example: "CPU#x" */ 226 char chip_compatible[32]; /* example: "FJSV,SPARC64-VI" */ 227 /* 228 * Jupiter Bus Device ID 229 * 0x0400, 0x0408, ... , 0x05f8 230 */ 231 uint16_t chip_portid; 232 uint16_t chip_filler; 233 uint32_t chip_spare1[6]; 234 hwd_core_t chip_cores[HWD_CORES_PER_CPU_CHIP]; 235 uint32_t chip_spare2[4]; 236 } hwd_cpu_chip_t; 237 238 /* 239 * SC 240 */ 241 typedef struct { 242 hwd_stat_t sc_status; 243 uint32_t sc_filler; 244 /* 245 * Top address of SC registers in this XSB 246 */ 247 uint64_t sc_register_address; 248 } hwd_sc_t; 249 250 /* 251 * Bank 252 */ 253 typedef struct { 254 hwd_stat_t bank_status; 255 hwd_stat_t bank_cs_status[2]; /* DIMM pair status */ 256 uint32_t bank_filler1; 257 uint64_t bank_register_address; /* address of mem patrol regs */ 258 uint8_t bank_mac_ocd; /* calibrated MAC OCD value */ 259 uint8_t bank_filler2[3]; 260 uint8_t bank_dimm_ocd[4][2]; /* calibrated DIMM OCD value */ 261 uint32_t bank_tune; /* for POST use */ 262 uint32_t bank_spare[2]; 263 } hwd_bank_t; 264 265 /* 266 * Chunk 267 */ 268 typedef struct { 269 uint64_t chnk_start_address; 270 uint64_t chnk_size; 271 } hwd_chunk_t; 272 273 /* 274 * Dimm 275 */ 276 typedef struct { 277 hwd_stat_t dimm_status; 278 uint32_t dimm_filler1; 279 uint64_t dimm_capacity; /* bytes */ 280 uint64_t dimm_available_capacity; /* bytes */ 281 uint8_t dimm_rank; /* 1 or 2 */ 282 uint8_t dimm_filler2[7]; 283 char dimm_component_name[32]; /* "MEM#xyz" */ 284 char dimm_fru_name[32]; /* "MEM#xyz" */ 285 } hwd_dimm_t; 286 287 /* 288 * CS 289 */ 290 typedef struct { 291 hwd_stat_t cs_status; 292 uint8_t cs_number_of_dimms; 293 uint8_t cs_filler[3]; 294 uint64_t cs_available_capacity; 295 uint64_t cs_dimm_capacity; 296 uint8_t cs_dimm_badd[8]; /* Value to initialize MAC by POST */ 297 uint16_t cs_dimm_add[8]; /* Value to initialize MAC by POST */ 298 uint8_t cs_pa_mac_table[64]; /* PA <-> MAC address conversion */ 299 } hwd_cs_t; 300 301 /* 302 * Memory 303 */ 304 typedef struct { 305 uint64_t mem_start_address; /* Memory start for this LSB */ 306 uint64_t mem_size; /* Memory size for this LSB */ 307 hwd_bank_t mem_banks[HWD_BANKS_PER_CMU]; 308 /* 309 * Mirroring mode: 310 * 0x00 or 0x01 311 * 0x00 : not 'memory mirror mode' 312 * 0x01 : 'memory mirror mode' 313 */ 314 uint8_t mem_mirror_mode; /* mirroring mode */ 315 /* 316 * Memory configuration: 317 * 0x01 : 1 divided mode 318 * 0x02 : 2 divided mode 319 * 0x04 : 4 divided mode 320 * 321 * It is always set to 0x04 at the XSB mode. 322 */ 323 uint8_t mem_division_mode; 324 uint8_t mem_piece_number; /* 0-3 memory slot group used */ 325 uint8_t mem_cs_interleave; /* 1:cs interleave, 0:not */ 326 uint32_t mem_filler[3]; 327 uint8_t mem_available_bitmap[512]; /* for POST use */ 328 uint8_t mem_degrade_bitmap[16384]; /* for POST use */ 329 hwd_chunk_t mem_chunks[HWD_MAX_MEM_CHUNKS]; 330 hwd_dimm_t mem_dimms[HWD_DIMMS_PER_CMU]; 331 hwd_cs_t mem_cs[2]; 332 } hwd_memory_t; 333 334 typedef struct { 335 hwd_stat_t scf_status; 336 char scf_component_name[32]; /* "SCFI#z" */ 337 } hwd_scf_interface_t; 338 339 typedef struct { 340 hwd_stat_t tty_status; 341 char tty_component_name[32]; /* "TTY#z" */ 342 } hwd_tty_t; 343 344 typedef struct { 345 uint8_t fver_major; /* firmware major version */ 346 uint8_t fver_minor; /* firmware minor version */ 347 uint8_t fver_local; /* firmware local version */ 348 uint8_t fver_filler; 349 } hwd_fmem_version_t; 350 351 typedef struct { 352 hwd_stat_t fmem_status; /* status of flash */ 353 char fmem_component_name[32]; 354 uint8_t fmem_used; /* non-zero: fmem is used */ 355 uint8_t fmem_filler[3]; 356 hwd_fmem_version_t fmem_version; 357 uint32_t fmem_spare; 358 } hwd_fmem_t; 359 360 /* 361 * CMU CH 362 */ 363 typedef struct { 364 hwd_stat_t chan_status; 365 /* 366 * CMU_CH port ID 367 * LSB0 is 0x0008, LSB1 is 0x0018, ... , LSB15 is 0x00f8 368 */ 369 uint16_t chan_portid; 370 uint16_t chan_filler; 371 char chan_component_name[32]; /* "U2P#z" */ 372 hwd_scf_interface_t chan_scf_interface; 373 hwd_tty_t chan_serial; 374 hwd_fmem_t chan_fmem[2]; 375 } hwd_cmu_chan_t; 376 377 /* 378 * CMU 379 */ 380 typedef struct { 381 char cmu_component_name[32]; /* example: "CxS0y" */ 382 char cmu_fru_name[32]; /* example: "Cabinet#x-CMU#y" */ 383 384 hwd_cpu_chip_t cmu_cpu_chips[HWD_CPU_CHIPS_PER_CMU]; /* CPU */ 385 hwd_sc_t cmu_scs[HWD_SCS_PER_CMU]; /* SC */ 386 hwd_memory_t cmu_memory; /* Memory */ 387 hwd_cmu_chan_t cmu_ch; /* CMU CH */ 388 uint32_t cmu_spare[32]; 389 } hwd_cmu_t; 390 391 typedef struct { 392 hwd_stat_t slot_status; 393 char slot_name[16]; 394 } hwd_slot_t; 395 396 /* 397 * IO Boat 398 */ 399 typedef struct { 400 hwd_stat_t iob_status; 401 char iob_component_name[32]; 402 char iob_fru_name[32]; 403 /* 404 * IO_Boat type 405 * 0x01 : PCI-X Slot Type 406 * 0x02 : PCI Express Slot Type 407 */ 408 uint32_t iob_type; /* PCI-X or PCI Express */ 409 uint64_t iob_io_box_info; /* location of I/O */ 410 /* 411 * Information of switch on IO_boat 412 * use only switch_status[0] when PCI-X type IO_boat 413 */ 414 hwd_stat_t iob_switch_status[3]; /* PCIE switch statuses */ 415 /* 416 * Information of bridge on IO_boat 417 * use only when PCI-X type IO_boat 418 */ 419 hwd_stat_t iob_bridge_status[3]; /* PCIX bridge statuses */ 420 hwd_slot_t iob_slot[6]; /* PCI slot names */ 421 uint32_t iob_spare[8]; 422 } hwd_io_boat_t; 423 424 /* IOU PCI Express Slot */ 425 typedef struct { 426 uint32_t iou_type; /* 0: empty, 1: card, 2: IO boat */ 427 hwd_slot_t iou_slot; 428 hwd_io_boat_t iou_io_boat; 429 } hwd_iou_slot_t; 430 431 typedef struct { 432 hwd_stat_t ff_onb_switch_status; 433 uint8_t ff_onb_filler[64]; 434 hwd_stat_t ff_onb_bridge_status; 435 hwd_stat_t ff_onb_sas_status; 436 hwd_stat_t ff_onb_gbe_status; 437 hwd_iou_slot_t ff_onb_slot; 438 hwd_slot_t ff_onb_xslot; 439 } hwd_ff_onboard_t; 440 441 typedef struct { 442 hwd_stat_t ioua_status; /* IOUA status */ 443 char ioua_component_name[32]; 444 char ioua_fru_name[32]; 445 hwd_stat_t ioua_bridge_status; 446 hwd_stat_t ioua_sas_status; 447 hwd_stat_t ioua_gbe_status; 448 } hwd_ioua_t; 449 450 typedef struct { 451 uint8_t iou_desc_filler[80]; 452 hwd_iou_slot_t iou_desc_slot; 453 } hwd_iou_slot_desc_t; 454 455 typedef struct { 456 hwd_stat_t leaf_status; 457 uint16_t leaf_port_id; /* portid (logical leaf id) */ 458 uint8_t leaf_filler[6]; 459 uint32_t leaf_slot_type; /* card or boat */ 460 union { 461 hwd_ff_onboard_t leaf_ff_onboard; 462 hwd_ioua_t leaf_ioua; 463 hwd_iou_slot_desc_t leaf_iou_slot; 464 uint8_t leaf_spare[448]; 465 } leaf_u; 466 uint64_t leaf_cfgio_offset; /* config space offset */ 467 uint64_t leaf_cfgio_size; /* config space size */ 468 uint64_t leaf_mem32_offset; /* offset of mem32 area */ 469 uint64_t leaf_mem32_size; /* size of mem32 area */ 470 uint64_t leaf_mem64_offset; /* offset of mem64 area */ 471 uint64_t leaf_mem64_size; /* size of mem64 area */ 472 } hwd_leaf_t; 473 474 /* 475 * PCI CH 476 */ 477 typedef struct { 478 hwd_stat_t pci_status; /* PCI CH status */ 479 char pci_component_name[32]; 480 char pci_fru_name[32]; 481 uint8_t pci_filler[12]; 482 hwd_leaf_t pci_leaf[HWD_LEAVES_PER_PCI_CHANNEL]; 483 } hwd_pci_ch_t; 484 485 /* 486 * System Board 487 */ 488 typedef struct { 489 /* 490 * SB 491 */ 492 hwd_stat_t sb_status; 493 uint8_t sb_mode; /* 0:PSB 1:XSB */ 494 uint8_t sb_psb_number; /* PSB number for this LSB */ 495 uint8_t sb_filler1[10]; 496 497 hwd_cmu_t sb_cmu; /* CMU */ 498 499 hwd_pci_ch_t sb_pci_ch[HWD_PCI_CHANNELS_PER_SB]; /* PCI CH */ 500 501 uint32_t sb_spare[31]; 502 uint32_t sb_check_sum; 503 } hwd_sb_t; 504 505 #define HWD_DATA_SIZE (36 * 1024) /* Size of HWD data from SCF */ 506 507 #ifdef __cplusplus 508 } 509 #endif 510 511 #endif /* _SYS_OPL_HWDESC_H */ 512