1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26#pragma ident "%Z%%M% %I% %E% SMI" 27 28#if !defined(lint) 29#include "assym.h" 30#endif /* !lint */ 31#include <sys/asm_linkage.h> 32#include <sys/privregs.h> 33#include <sys/sun4asi.h> 34#include <sys/spitregs.h> 35#include <sys/cheetahregs.h> 36#include <sys/machtrap.h> 37#include <sys/machthread.h> 38#include <sys/pcb.h> 39#include <sys/pte.h> 40#include <sys/mmu.h> 41#include <sys/machpcb.h> 42#include <sys/async.h> 43#include <sys/intreg.h> 44#include <sys/scb.h> 45#include <sys/psr_compat.h> 46#include <sys/syscall.h> 47#include <sys/machparam.h> 48#include <sys/traptrace.h> 49#include <vm/hat_sfmmu.h> 50#include <sys/archsystm.h> 51#include <sys/utrap.h> 52#include <sys/clock.h> 53#include <sys/intr.h> 54#include <sys/fpu/fpu_simulator.h> 55#include <vm/seg_spt.h> 56 57/* 58 * WARNING: If you add a fast trap handler which can be invoked by a 59 * non-privileged user, you may have to use the FAST_TRAP_DONE macro 60 * instead of "done" instruction to return back to the user mode. See 61 * comments for the "fast_trap_done" entry point for more information. 62 * 63 * An alternate FAST_TRAP_DONE_CHK_INTR macro should be used for the 64 * cases where you always want to process any pending interrupts before 65 * returning back to the user mode. 66 */ 67#define FAST_TRAP_DONE \ 68 ba,a fast_trap_done 69 70#define FAST_TRAP_DONE_CHK_INTR \ 71 ba,a fast_trap_done_chk_intr 72 73/* 74 * SPARC V9 Trap Table 75 * 76 * Most of the trap handlers are made from common building 77 * blocks, and some are instantiated multiple times within 78 * the trap table. So, I build a bunch of macros, then 79 * populate the table using only the macros. 80 * 81 * Many macros branch to sys_trap. Its calling convention is: 82 * %g1 kernel trap handler 83 * %g2, %g3 args for above 84 * %g4 desire %pil 85 */ 86 87#ifdef TRAPTRACE 88 89/* 90 * Tracing macro. Adds two instructions if TRAPTRACE is defined. 91 */ 92#define TT_TRACE(label) \ 93 ba label ;\ 94 rd %pc, %g7 95#define TT_TRACE_INS 2 96 97#define TT_TRACE_L(label) \ 98 ba label ;\ 99 rd %pc, %l4 ;\ 100 clr %l4 101#define TT_TRACE_L_INS 3 102 103#else 104 105#define TT_TRACE(label) 106#define TT_TRACE_INS 0 107 108#define TT_TRACE_L(label) 109#define TT_TRACE_L_INS 0 110 111#endif 112 113/* 114 * This macro is used to update per cpu mmu stats in perf critical 115 * paths. It is only enabled in debug kernels or if SFMMU_STAT_GATHER 116 * is defined. 117 */ 118#if defined(DEBUG) || defined(SFMMU_STAT_GATHER) 119#define HAT_PERCPU_DBSTAT(stat) \ 120 mov stat, %g1 ;\ 121 ba stat_mmu ;\ 122 rd %pc, %g7 123#else 124#define HAT_PERCPU_DBSTAT(stat) 125#endif /* DEBUG || SFMMU_STAT_GATHER */ 126 127/* 128 * This first set are funneled to trap() with %tt as the type. 129 * Trap will then either panic or send the user a signal. 130 */ 131/* 132 * NOT is used for traps that just shouldn't happen. 133 * It comes in both single and quadruple flavors. 134 */ 135#if !defined(lint) 136 .global trap 137#endif /* !lint */ 138#define NOT \ 139 TT_TRACE(trace_gen) ;\ 140 set trap, %g1 ;\ 141 rdpr %tt, %g3 ;\ 142 ba,pt %xcc, sys_trap ;\ 143 sub %g0, 1, %g4 ;\ 144 .align 32 145#define NOT4 NOT; NOT; NOT; NOT 146/* 147 * RED is for traps that use the red mode handler. 148 * We should never see these either. 149 */ 150#define RED NOT 151/* 152 * BAD is used for trap vectors we don't have a kernel 153 * handler for. 154 * It also comes in single and quadruple versions. 155 */ 156#define BAD NOT 157#define BAD4 NOT4 158 159#define DONE \ 160 done; \ 161 .align 32 162 163/* 164 * TRAP vectors to the trap() function. 165 * It's main use is for user errors. 166 */ 167#if !defined(lint) 168 .global trap 169#endif /* !lint */ 170#define TRAP(arg) \ 171 TT_TRACE(trace_gen) ;\ 172 set trap, %g1 ;\ 173 mov arg, %g3 ;\ 174 ba,pt %xcc, sys_trap ;\ 175 sub %g0, 1, %g4 ;\ 176 .align 32 177 178/* 179 * SYSCALL is used for system calls on both ILP32 and LP64 kernels 180 * depending on the "which" parameter (should be syscall_trap, 181 * syscall_trap32, or nosys for unused system call traps). 182 */ 183#define SYSCALL(which) \ 184 TT_TRACE(trace_gen) ;\ 185 set (which), %g1 ;\ 186 ba,pt %xcc, sys_trap ;\ 187 sub %g0, 1, %g4 ;\ 188 .align 32 189 190#define FLUSHW() \ 191 set trap, %g1 ;\ 192 mov T_FLUSHW, %g3 ;\ 193 sub %g0, 1, %g4 ;\ 194 save ;\ 195 flushw ;\ 196 restore ;\ 197 FAST_TRAP_DONE ;\ 198 .align 32 199 200/* 201 * GOTO just jumps to a label. 202 * It's used for things that can be fixed without going thru sys_trap. 203 */ 204#define GOTO(label) \ 205 .global label ;\ 206 ba,a label ;\ 207 .empty ;\ 208 .align 32 209 210/* 211 * GOTO_TT just jumps to a label. 212 * correctable ECC error traps at level 0 and 1 will use this macro. 213 * It's used for things that can be fixed without going thru sys_trap. 214 */ 215#define GOTO_TT(label, ttlabel) \ 216 .global label ;\ 217 TT_TRACE(ttlabel) ;\ 218 ba,a label ;\ 219 .empty ;\ 220 .align 32 221 222/* 223 * Privileged traps 224 * Takes breakpoint if privileged, calls trap() if not. 225 */ 226#define PRIV(label) \ 227 rdpr %tstate, %g1 ;\ 228 btst TSTATE_PRIV, %g1 ;\ 229 bnz label ;\ 230 rdpr %tt, %g3 ;\ 231 set trap, %g1 ;\ 232 ba,pt %xcc, sys_trap ;\ 233 sub %g0, 1, %g4 ;\ 234 .align 32 235 236 237/* 238 * DTrace traps. 239 */ 240#define DTRACE_PID \ 241 .global dtrace_pid_probe ;\ 242 set dtrace_pid_probe, %g1 ;\ 243 ba,pt %xcc, user_trap ;\ 244 sub %g0, 1, %g4 ;\ 245 .align 32 246 247#define DTRACE_RETURN \ 248 .global dtrace_return_probe ;\ 249 set dtrace_return_probe, %g1 ;\ 250 ba,pt %xcc, user_trap ;\ 251 sub %g0, 1, %g4 ;\ 252 .align 32 253 254/* 255 * REGISTER WINDOW MANAGEMENT MACROS 256 */ 257 258/* 259 * various convenient units of padding 260 */ 261#define SKIP(n) .skip 4*(n) 262 263/* 264 * CLEAN_WINDOW is the simple handler for cleaning a register window. 265 */ 266#define CLEAN_WINDOW \ 267 TT_TRACE_L(trace_win) ;\ 268 rdpr %cleanwin, %l0; inc %l0; wrpr %l0, %cleanwin ;\ 269 clr %l0; clr %l1; clr %l2; clr %l3 ;\ 270 clr %l4; clr %l5; clr %l6; clr %l7 ;\ 271 clr %o0; clr %o1; clr %o2; clr %o3 ;\ 272 clr %o4; clr %o5; clr %o6; clr %o7 ;\ 273 retry; .align 128 274 275#if !defined(lint) 276 277/* 278 * If we get an unresolved tlb miss while in a window handler, the fault 279 * handler will resume execution at the last instruction of the window 280 * hander, instead of delivering the fault to the kernel. Spill handlers 281 * use this to spill windows into the wbuf. 282 * 283 * The mixed handler works by checking %sp, and branching to the correct 284 * handler. This is done by branching back to label 1: for 32b frames, 285 * or label 2: for 64b frames; which implies the handler order is: 32b, 286 * 64b, mixed. The 1: and 2: labels are offset into the routines to 287 * allow the branchs' delay slots to contain useful instructions. 288 */ 289 290/* 291 * SPILL_32bit spills a 32-bit-wide kernel register window. It 292 * assumes that the kernel context and the nucleus context are the 293 * same. The stack pointer is required to be eight-byte aligned even 294 * though this code only needs it to be four-byte aligned. 295 */ 296#define SPILL_32bit(tail) \ 297 srl %sp, 0, %sp ;\ 2981: st %l0, [%sp + 0] ;\ 299 st %l1, [%sp + 4] ;\ 300 st %l2, [%sp + 8] ;\ 301 st %l3, [%sp + 12] ;\ 302 st %l4, [%sp + 16] ;\ 303 st %l5, [%sp + 20] ;\ 304 st %l6, [%sp + 24] ;\ 305 st %l7, [%sp + 28] ;\ 306 st %i0, [%sp + 32] ;\ 307 st %i1, [%sp + 36] ;\ 308 st %i2, [%sp + 40] ;\ 309 st %i3, [%sp + 44] ;\ 310 st %i4, [%sp + 48] ;\ 311 st %i5, [%sp + 52] ;\ 312 st %i6, [%sp + 56] ;\ 313 st %i7, [%sp + 60] ;\ 314 TT_TRACE_L(trace_win) ;\ 315 saved ;\ 316 retry ;\ 317 SKIP(31-19-TT_TRACE_L_INS) ;\ 318 ba,a,pt %xcc, fault_32bit_/**/tail ;\ 319 .empty 320 321/* 322 * SPILL_32bit_asi spills a 32-bit-wide register window into a 32-bit 323 * wide address space via the designated asi. It is used to spill 324 * non-kernel windows. The stack pointer is required to be eight-byte 325 * aligned even though this code only needs it to be four-byte 326 * aligned. 327 */ 328#define SPILL_32bit_asi(asi_num, tail) \ 329 srl %sp, 0, %sp ;\ 3301: sta %l0, [%sp + %g0]asi_num ;\ 331 mov 4, %g1 ;\ 332 sta %l1, [%sp + %g1]asi_num ;\ 333 mov 8, %g2 ;\ 334 sta %l2, [%sp + %g2]asi_num ;\ 335 mov 12, %g3 ;\ 336 sta %l3, [%sp + %g3]asi_num ;\ 337 add %sp, 16, %g4 ;\ 338 sta %l4, [%g4 + %g0]asi_num ;\ 339 sta %l5, [%g4 + %g1]asi_num ;\ 340 sta %l6, [%g4 + %g2]asi_num ;\ 341 sta %l7, [%g4 + %g3]asi_num ;\ 342 add %g4, 16, %g4 ;\ 343 sta %i0, [%g4 + %g0]asi_num ;\ 344 sta %i1, [%g4 + %g1]asi_num ;\ 345 sta %i2, [%g4 + %g2]asi_num ;\ 346 sta %i3, [%g4 + %g3]asi_num ;\ 347 add %g4, 16, %g4 ;\ 348 sta %i4, [%g4 + %g0]asi_num ;\ 349 sta %i5, [%g4 + %g1]asi_num ;\ 350 sta %i6, [%g4 + %g2]asi_num ;\ 351 sta %i7, [%g4 + %g3]asi_num ;\ 352 TT_TRACE_L(trace_win) ;\ 353 saved ;\ 354 retry ;\ 355 SKIP(31-25-TT_TRACE_L_INS) ;\ 356 ba,a,pt %xcc, fault_32bit_/**/tail ;\ 357 .empty 358 359/* 360 * SPILL_32bit_tt1 spills a 32-bit-wide register window into a 32-bit 361 * wide address space via the designated asi. It is used to spill 362 * windows at tl>1 where performance isn't the primary concern and 363 * where we don't want to use unnecessary registers. The stack 364 * pointer is required to be eight-byte aligned even though this code 365 * only needs it to be four-byte aligned. 366 */ 367#define SPILL_32bit_tt1(asi_num, tail) \ 368 mov asi_num, %asi ;\ 3691: srl %sp, 0, %sp ;\ 370 sta %l0, [%sp + 0]%asi ;\ 371 sta %l1, [%sp + 4]%asi ;\ 372 sta %l2, [%sp + 8]%asi ;\ 373 sta %l3, [%sp + 12]%asi ;\ 374 sta %l4, [%sp + 16]%asi ;\ 375 sta %l5, [%sp + 20]%asi ;\ 376 sta %l6, [%sp + 24]%asi ;\ 377 sta %l7, [%sp + 28]%asi ;\ 378 sta %i0, [%sp + 32]%asi ;\ 379 sta %i1, [%sp + 36]%asi ;\ 380 sta %i2, [%sp + 40]%asi ;\ 381 sta %i3, [%sp + 44]%asi ;\ 382 sta %i4, [%sp + 48]%asi ;\ 383 sta %i5, [%sp + 52]%asi ;\ 384 sta %i6, [%sp + 56]%asi ;\ 385 sta %i7, [%sp + 60]%asi ;\ 386 TT_TRACE_L(trace_win) ;\ 387 saved ;\ 388 retry ;\ 389 SKIP(31-20-TT_TRACE_L_INS) ;\ 390 ba,a,pt %xcc, fault_32bit_/**/tail ;\ 391 .empty 392 393 394/* 395 * FILL_32bit fills a 32-bit-wide kernel register window. It assumes 396 * that the kernel context and the nucleus context are the same. The 397 * stack pointer is required to be eight-byte aligned even though this 398 * code only needs it to be four-byte aligned. 399 */ 400#define FILL_32bit(tail) \ 401 srl %sp, 0, %sp ;\ 4021: TT_TRACE_L(trace_win) ;\ 403 ld [%sp + 0], %l0 ;\ 404 ld [%sp + 4], %l1 ;\ 405 ld [%sp + 8], %l2 ;\ 406 ld [%sp + 12], %l3 ;\ 407 ld [%sp + 16], %l4 ;\ 408 ld [%sp + 20], %l5 ;\ 409 ld [%sp + 24], %l6 ;\ 410 ld [%sp + 28], %l7 ;\ 411 ld [%sp + 32], %i0 ;\ 412 ld [%sp + 36], %i1 ;\ 413 ld [%sp + 40], %i2 ;\ 414 ld [%sp + 44], %i3 ;\ 415 ld [%sp + 48], %i4 ;\ 416 ld [%sp + 52], %i5 ;\ 417 ld [%sp + 56], %i6 ;\ 418 ld [%sp + 60], %i7 ;\ 419 restored ;\ 420 retry ;\ 421 SKIP(31-19-TT_TRACE_L_INS) ;\ 422 ba,a,pt %xcc, fault_32bit_/**/tail ;\ 423 .empty 424 425/* 426 * FILL_32bit_asi fills a 32-bit-wide register window from a 32-bit 427 * wide address space via the designated asi. It is used to fill 428 * non-kernel windows. The stack pointer is required to be eight-byte 429 * aligned even though this code only needs it to be four-byte 430 * aligned. 431 */ 432#define FILL_32bit_asi(asi_num, tail) \ 433 srl %sp, 0, %sp ;\ 4341: TT_TRACE_L(trace_win) ;\ 435 mov 4, %g1 ;\ 436 lda [%sp + %g0]asi_num, %l0 ;\ 437 mov 8, %g2 ;\ 438 lda [%sp + %g1]asi_num, %l1 ;\ 439 mov 12, %g3 ;\ 440 lda [%sp + %g2]asi_num, %l2 ;\ 441 lda [%sp + %g3]asi_num, %l3 ;\ 442 add %sp, 16, %g4 ;\ 443 lda [%g4 + %g0]asi_num, %l4 ;\ 444 lda [%g4 + %g1]asi_num, %l5 ;\ 445 lda [%g4 + %g2]asi_num, %l6 ;\ 446 lda [%g4 + %g3]asi_num, %l7 ;\ 447 add %g4, 16, %g4 ;\ 448 lda [%g4 + %g0]asi_num, %i0 ;\ 449 lda [%g4 + %g1]asi_num, %i1 ;\ 450 lda [%g4 + %g2]asi_num, %i2 ;\ 451 lda [%g4 + %g3]asi_num, %i3 ;\ 452 add %g4, 16, %g4 ;\ 453 lda [%g4 + %g0]asi_num, %i4 ;\ 454 lda [%g4 + %g1]asi_num, %i5 ;\ 455 lda [%g4 + %g2]asi_num, %i6 ;\ 456 lda [%g4 + %g3]asi_num, %i7 ;\ 457 restored ;\ 458 retry ;\ 459 SKIP(31-25-TT_TRACE_L_INS) ;\ 460 ba,a,pt %xcc, fault_32bit_/**/tail ;\ 461 .empty 462 463/* 464 * FILL_32bit_tt1 fills a 32-bit-wide register window from a 32-bit 465 * wide address space via the designated asi. It is used to fill 466 * windows at tl>1 where performance isn't the primary concern and 467 * where we don't want to use unnecessary registers. The stack 468 * pointer is required to be eight-byte aligned even though this code 469 * only needs it to be four-byte aligned. 470 */ 471#define FILL_32bit_tt1(asi_num, tail) \ 472 mov asi_num, %asi ;\ 4731: srl %sp, 0, %sp ;\ 474 TT_TRACE_L(trace_win) ;\ 475 lda [%sp + 0]%asi, %l0 ;\ 476 lda [%sp + 4]%asi, %l1 ;\ 477 lda [%sp + 8]%asi, %l2 ;\ 478 lda [%sp + 12]%asi, %l3 ;\ 479 lda [%sp + 16]%asi, %l4 ;\ 480 lda [%sp + 20]%asi, %l5 ;\ 481 lda [%sp + 24]%asi, %l6 ;\ 482 lda [%sp + 28]%asi, %l7 ;\ 483 lda [%sp + 32]%asi, %i0 ;\ 484 lda [%sp + 36]%asi, %i1 ;\ 485 lda [%sp + 40]%asi, %i2 ;\ 486 lda [%sp + 44]%asi, %i3 ;\ 487 lda [%sp + 48]%asi, %i4 ;\ 488 lda [%sp + 52]%asi, %i5 ;\ 489 lda [%sp + 56]%asi, %i6 ;\ 490 lda [%sp + 60]%asi, %i7 ;\ 491 restored ;\ 492 retry ;\ 493 SKIP(31-20-TT_TRACE_L_INS) ;\ 494 ba,a,pt %xcc, fault_32bit_/**/tail ;\ 495 .empty 496 497 498/* 499 * SPILL_64bit spills a 64-bit-wide kernel register window. It 500 * assumes that the kernel context and the nucleus context are the 501 * same. The stack pointer is required to be eight-byte aligned. 502 */ 503#define SPILL_64bit(tail) \ 5042: stx %l0, [%sp + V9BIAS64 + 0] ;\ 505 stx %l1, [%sp + V9BIAS64 + 8] ;\ 506 stx %l2, [%sp + V9BIAS64 + 16] ;\ 507 stx %l3, [%sp + V9BIAS64 + 24] ;\ 508 stx %l4, [%sp + V9BIAS64 + 32] ;\ 509 stx %l5, [%sp + V9BIAS64 + 40] ;\ 510 stx %l6, [%sp + V9BIAS64 + 48] ;\ 511 stx %l7, [%sp + V9BIAS64 + 56] ;\ 512 stx %i0, [%sp + V9BIAS64 + 64] ;\ 513 stx %i1, [%sp + V9BIAS64 + 72] ;\ 514 stx %i2, [%sp + V9BIAS64 + 80] ;\ 515 stx %i3, [%sp + V9BIAS64 + 88] ;\ 516 stx %i4, [%sp + V9BIAS64 + 96] ;\ 517 stx %i5, [%sp + V9BIAS64 + 104] ;\ 518 stx %i6, [%sp + V9BIAS64 + 112] ;\ 519 stx %i7, [%sp + V9BIAS64 + 120] ;\ 520 TT_TRACE_L(trace_win) ;\ 521 saved ;\ 522 retry ;\ 523 SKIP(31-18-TT_TRACE_L_INS) ;\ 524 ba,a,pt %xcc, fault_64bit_/**/tail ;\ 525 .empty 526 527/* 528 * SPILL_64bit_asi spills a 64-bit-wide register window into a 64-bit 529 * wide address space via the designated asi. It is used to spill 530 * non-kernel windows. The stack pointer is required to be eight-byte 531 * aligned. 532 */ 533#define SPILL_64bit_asi(asi_num, tail) \ 534 mov 0 + V9BIAS64, %g1 ;\ 5352: stxa %l0, [%sp + %g1]asi_num ;\ 536 mov 8 + V9BIAS64, %g2 ;\ 537 stxa %l1, [%sp + %g2]asi_num ;\ 538 mov 16 + V9BIAS64, %g3 ;\ 539 stxa %l2, [%sp + %g3]asi_num ;\ 540 mov 24 + V9BIAS64, %g4 ;\ 541 stxa %l3, [%sp + %g4]asi_num ;\ 542 add %sp, 32, %g5 ;\ 543 stxa %l4, [%g5 + %g1]asi_num ;\ 544 stxa %l5, [%g5 + %g2]asi_num ;\ 545 stxa %l6, [%g5 + %g3]asi_num ;\ 546 stxa %l7, [%g5 + %g4]asi_num ;\ 547 add %g5, 32, %g5 ;\ 548 stxa %i0, [%g5 + %g1]asi_num ;\ 549 stxa %i1, [%g5 + %g2]asi_num ;\ 550 stxa %i2, [%g5 + %g3]asi_num ;\ 551 stxa %i3, [%g5 + %g4]asi_num ;\ 552 add %g5, 32, %g5 ;\ 553 stxa %i4, [%g5 + %g1]asi_num ;\ 554 stxa %i5, [%g5 + %g2]asi_num ;\ 555 stxa %i6, [%g5 + %g3]asi_num ;\ 556 stxa %i7, [%g5 + %g4]asi_num ;\ 557 TT_TRACE_L(trace_win) ;\ 558 saved ;\ 559 retry ;\ 560 SKIP(31-25-TT_TRACE_L_INS) ;\ 561 ba,a,pt %xcc, fault_64bit_/**/tail ;\ 562 .empty 563 564/* 565 * SPILL_64bit_tt1 spills a 64-bit-wide register window into a 64-bit 566 * wide address space via the designated asi. It is used to spill 567 * windows at tl>1 where performance isn't the primary concern and 568 * where we don't want to use unnecessary registers. The stack 569 * pointer is required to be eight-byte aligned. 570 */ 571#define SPILL_64bit_tt1(asi_num, tail) \ 572 mov asi_num, %asi ;\ 5732: stxa %l0, [%sp + V9BIAS64 + 0]%asi ;\ 574 stxa %l1, [%sp + V9BIAS64 + 8]%asi ;\ 575 stxa %l2, [%sp + V9BIAS64 + 16]%asi ;\ 576 stxa %l3, [%sp + V9BIAS64 + 24]%asi ;\ 577 stxa %l4, [%sp + V9BIAS64 + 32]%asi ;\ 578 stxa %l5, [%sp + V9BIAS64 + 40]%asi ;\ 579 stxa %l6, [%sp + V9BIAS64 + 48]%asi ;\ 580 stxa %l7, [%sp + V9BIAS64 + 56]%asi ;\ 581 stxa %i0, [%sp + V9BIAS64 + 64]%asi ;\ 582 stxa %i1, [%sp + V9BIAS64 + 72]%asi ;\ 583 stxa %i2, [%sp + V9BIAS64 + 80]%asi ;\ 584 stxa %i3, [%sp + V9BIAS64 + 88]%asi ;\ 585 stxa %i4, [%sp + V9BIAS64 + 96]%asi ;\ 586 stxa %i5, [%sp + V9BIAS64 + 104]%asi ;\ 587 stxa %i6, [%sp + V9BIAS64 + 112]%asi ;\ 588 stxa %i7, [%sp + V9BIAS64 + 120]%asi ;\ 589 TT_TRACE_L(trace_win) ;\ 590 saved ;\ 591 retry ;\ 592 SKIP(31-19-TT_TRACE_L_INS) ;\ 593 ba,a,pt %xcc, fault_64bit_/**/tail ;\ 594 .empty 595 596 597/* 598 * FILL_64bit fills a 64-bit-wide kernel register window. It assumes 599 * that the kernel context and the nucleus context are the same. The 600 * stack pointer is required to be eight-byte aligned. 601 */ 602#define FILL_64bit(tail) \ 6032: TT_TRACE_L(trace_win) ;\ 604 ldx [%sp + V9BIAS64 + 0], %l0 ;\ 605 ldx [%sp + V9BIAS64 + 8], %l1 ;\ 606 ldx [%sp + V9BIAS64 + 16], %l2 ;\ 607 ldx [%sp + V9BIAS64 + 24], %l3 ;\ 608 ldx [%sp + V9BIAS64 + 32], %l4 ;\ 609 ldx [%sp + V9BIAS64 + 40], %l5 ;\ 610 ldx [%sp + V9BIAS64 + 48], %l6 ;\ 611 ldx [%sp + V9BIAS64 + 56], %l7 ;\ 612 ldx [%sp + V9BIAS64 + 64], %i0 ;\ 613 ldx [%sp + V9BIAS64 + 72], %i1 ;\ 614 ldx [%sp + V9BIAS64 + 80], %i2 ;\ 615 ldx [%sp + V9BIAS64 + 88], %i3 ;\ 616 ldx [%sp + V9BIAS64 + 96], %i4 ;\ 617 ldx [%sp + V9BIAS64 + 104], %i5 ;\ 618 ldx [%sp + V9BIAS64 + 112], %i6 ;\ 619 ldx [%sp + V9BIAS64 + 120], %i7 ;\ 620 restored ;\ 621 retry ;\ 622 SKIP(31-18-TT_TRACE_L_INS) ;\ 623 ba,a,pt %xcc, fault_64bit_/**/tail ;\ 624 .empty 625 626/* 627 * FILL_64bit_asi fills a 64-bit-wide register window from a 64-bit 628 * wide address space via the designated asi. It is used to fill 629 * non-kernel windows. The stack pointer is required to be eight-byte 630 * aligned. 631 */ 632#define FILL_64bit_asi(asi_num, tail) \ 633 mov V9BIAS64 + 0, %g1 ;\ 6342: TT_TRACE_L(trace_win) ;\ 635 ldxa [%sp + %g1]asi_num, %l0 ;\ 636 mov V9BIAS64 + 8, %g2 ;\ 637 ldxa [%sp + %g2]asi_num, %l1 ;\ 638 mov V9BIAS64 + 16, %g3 ;\ 639 ldxa [%sp + %g3]asi_num, %l2 ;\ 640 mov V9BIAS64 + 24, %g4 ;\ 641 ldxa [%sp + %g4]asi_num, %l3 ;\ 642 add %sp, 32, %g5 ;\ 643 ldxa [%g5 + %g1]asi_num, %l4 ;\ 644 ldxa [%g5 + %g2]asi_num, %l5 ;\ 645 ldxa [%g5 + %g3]asi_num, %l6 ;\ 646 ldxa [%g5 + %g4]asi_num, %l7 ;\ 647 add %g5, 32, %g5 ;\ 648 ldxa [%g5 + %g1]asi_num, %i0 ;\ 649 ldxa [%g5 + %g2]asi_num, %i1 ;\ 650 ldxa [%g5 + %g3]asi_num, %i2 ;\ 651 ldxa [%g5 + %g4]asi_num, %i3 ;\ 652 add %g5, 32, %g5 ;\ 653 ldxa [%g5 + %g1]asi_num, %i4 ;\ 654 ldxa [%g5 + %g2]asi_num, %i5 ;\ 655 ldxa [%g5 + %g3]asi_num, %i6 ;\ 656 ldxa [%g5 + %g4]asi_num, %i7 ;\ 657 restored ;\ 658 retry ;\ 659 SKIP(31-25-TT_TRACE_L_INS) ;\ 660 ba,a,pt %xcc, fault_64bit_/**/tail ;\ 661 .empty 662 663/* 664 * FILL_64bit_tt1 fills a 64-bit-wide register window from a 64-bit 665 * wide address space via the designated asi. It is used to fill 666 * windows at tl>1 where performance isn't the primary concern and 667 * where we don't want to use unnecessary registers. The stack 668 * pointer is required to be eight-byte aligned. 669 */ 670#define FILL_64bit_tt1(asi_num, tail) \ 671 mov asi_num, %asi ;\ 672 TT_TRACE_L(trace_win) ;\ 673 ldxa [%sp + V9BIAS64 + 0]%asi, %l0 ;\ 674 ldxa [%sp + V9BIAS64 + 8]%asi, %l1 ;\ 675 ldxa [%sp + V9BIAS64 + 16]%asi, %l2 ;\ 676 ldxa [%sp + V9BIAS64 + 24]%asi, %l3 ;\ 677 ldxa [%sp + V9BIAS64 + 32]%asi, %l4 ;\ 678 ldxa [%sp + V9BIAS64 + 40]%asi, %l5 ;\ 679 ldxa [%sp + V9BIAS64 + 48]%asi, %l6 ;\ 680 ldxa [%sp + V9BIAS64 + 56]%asi, %l7 ;\ 681 ldxa [%sp + V9BIAS64 + 64]%asi, %i0 ;\ 682 ldxa [%sp + V9BIAS64 + 72]%asi, %i1 ;\ 683 ldxa [%sp + V9BIAS64 + 80]%asi, %i2 ;\ 684 ldxa [%sp + V9BIAS64 + 88]%asi, %i3 ;\ 685 ldxa [%sp + V9BIAS64 + 96]%asi, %i4 ;\ 686 ldxa [%sp + V9BIAS64 + 104]%asi, %i5 ;\ 687 ldxa [%sp + V9BIAS64 + 112]%asi, %i6 ;\ 688 ldxa [%sp + V9BIAS64 + 120]%asi, %i7 ;\ 689 restored ;\ 690 retry ;\ 691 SKIP(31-19-TT_TRACE_L_INS) ;\ 692 ba,a,pt %xcc, fault_64bit_/**/tail ;\ 693 .empty 694 695#endif /* !lint */ 696 697/* 698 * SPILL_mixed spills either size window, depending on 699 * whether %sp is even or odd, to a 32-bit address space. 700 * This may only be used in conjunction with SPILL_32bit/ 701 * SPILL_64bit. New versions of SPILL_mixed_{tt1,asi} would be 702 * needed for use with SPILL_{32,64}bit_{tt1,asi}. Particular 703 * attention should be paid to the instructions that belong 704 * in the delay slots of the branches depending on the type 705 * of spill handler being branched to. 706 * Clear upper 32 bits of %sp if it is odd. 707 * We won't need to clear them in 64 bit kernel. 708 */ 709#define SPILL_mixed \ 710 btst 1, %sp ;\ 711 bz,a,pt %xcc, 1b ;\ 712 srl %sp, 0, %sp ;\ 713 ba,pt %xcc, 2b ;\ 714 nop ;\ 715 .align 128 716 717/* 718 * FILL_mixed(ASI) fills either size window, depending on 719 * whether %sp is even or odd, from a 32-bit address space. 720 * This may only be used in conjunction with FILL_32bit/ 721 * FILL_64bit. New versions of FILL_mixed_{tt1,asi} would be 722 * needed for use with FILL_{32,64}bit_{tt1,asi}. Particular 723 * attention should be paid to the instructions that belong 724 * in the delay slots of the branches depending on the type 725 * of fill handler being branched to. 726 * Clear upper 32 bits of %sp if it is odd. 727 * We won't need to clear them in 64 bit kernel. 728 */ 729#define FILL_mixed \ 730 btst 1, %sp ;\ 731 bz,a,pt %xcc, 1b ;\ 732 srl %sp, 0, %sp ;\ 733 ba,pt %xcc, 2b ;\ 734 nop ;\ 735 .align 128 736 737 738/* 739 * SPILL_32clean/SPILL_64clean spill 32-bit and 64-bit register windows, 740 * respectively, into the address space via the designated asi. The 741 * unbiased stack pointer is required to be eight-byte aligned (even for 742 * the 32-bit case even though this code does not require such strict 743 * alignment). 744 * 745 * With SPARC v9 the spill trap takes precedence over the cleanwin trap 746 * so when cansave == 0, canrestore == 6, and cleanwin == 6 the next save 747 * will cause cwp + 2 to be spilled but will not clean cwp + 1. That 748 * window may contain kernel data so in user_rtt we set wstate to call 749 * these spill handlers on the first user spill trap. These handler then 750 * spill the appropriate window but also back up a window and clean the 751 * window that didn't get a cleanwin trap. 752 */ 753#define SPILL_32clean(asi_num, tail) \ 754 srl %sp, 0, %sp ;\ 755 sta %l0, [%sp + %g0]asi_num ;\ 756 mov 4, %g1 ;\ 757 sta %l1, [%sp + %g1]asi_num ;\ 758 mov 8, %g2 ;\ 759 sta %l2, [%sp + %g2]asi_num ;\ 760 mov 12, %g3 ;\ 761 sta %l3, [%sp + %g3]asi_num ;\ 762 add %sp, 16, %g4 ;\ 763 sta %l4, [%g4 + %g0]asi_num ;\ 764 sta %l5, [%g4 + %g1]asi_num ;\ 765 sta %l6, [%g4 + %g2]asi_num ;\ 766 sta %l7, [%g4 + %g3]asi_num ;\ 767 add %g4, 16, %g4 ;\ 768 sta %i0, [%g4 + %g0]asi_num ;\ 769 sta %i1, [%g4 + %g1]asi_num ;\ 770 sta %i2, [%g4 + %g2]asi_num ;\ 771 sta %i3, [%g4 + %g3]asi_num ;\ 772 add %g4, 16, %g4 ;\ 773 sta %i4, [%g4 + %g0]asi_num ;\ 774 sta %i5, [%g4 + %g1]asi_num ;\ 775 sta %i6, [%g4 + %g2]asi_num ;\ 776 sta %i7, [%g4 + %g3]asi_num ;\ 777 TT_TRACE_L(trace_win) ;\ 778 b .spill_clean ;\ 779 mov WSTATE_USER32, %g7 ;\ 780 SKIP(31-25-TT_TRACE_L_INS) ;\ 781 ba,a,pt %xcc, fault_32bit_/**/tail ;\ 782 .empty 783 784#define SPILL_64clean(asi_num, tail) \ 785 mov 0 + V9BIAS64, %g1 ;\ 786 stxa %l0, [%sp + %g1]asi_num ;\ 787 mov 8 + V9BIAS64, %g2 ;\ 788 stxa %l1, [%sp + %g2]asi_num ;\ 789 mov 16 + V9BIAS64, %g3 ;\ 790 stxa %l2, [%sp + %g3]asi_num ;\ 791 mov 24 + V9BIAS64, %g4 ;\ 792 stxa %l3, [%sp + %g4]asi_num ;\ 793 add %sp, 32, %g5 ;\ 794 stxa %l4, [%g5 + %g1]asi_num ;\ 795 stxa %l5, [%g5 + %g2]asi_num ;\ 796 stxa %l6, [%g5 + %g3]asi_num ;\ 797 stxa %l7, [%g5 + %g4]asi_num ;\ 798 add %g5, 32, %g5 ;\ 799 stxa %i0, [%g5 + %g1]asi_num ;\ 800 stxa %i1, [%g5 + %g2]asi_num ;\ 801 stxa %i2, [%g5 + %g3]asi_num ;\ 802 stxa %i3, [%g5 + %g4]asi_num ;\ 803 add %g5, 32, %g5 ;\ 804 stxa %i4, [%g5 + %g1]asi_num ;\ 805 stxa %i5, [%g5 + %g2]asi_num ;\ 806 stxa %i6, [%g5 + %g3]asi_num ;\ 807 stxa %i7, [%g5 + %g4]asi_num ;\ 808 TT_TRACE_L(trace_win) ;\ 809 b .spill_clean ;\ 810 mov WSTATE_USER64, %g7 ;\ 811 SKIP(31-25-TT_TRACE_L_INS) ;\ 812 ba,a,pt %xcc, fault_64bit_/**/tail ;\ 813 .empty 814 815 816/* 817 * Floating point disabled. 818 */ 819#define FP_DISABLED_TRAP \ 820 TT_TRACE(trace_gen) ;\ 821 ba,pt %xcc,.fp_disabled ;\ 822 nop ;\ 823 .align 32 824 825/* 826 * Floating point exceptions. 827 */ 828#define FP_IEEE_TRAP \ 829 TT_TRACE(trace_gen) ;\ 830 ba,pt %xcc,.fp_ieee_exception ;\ 831 nop ;\ 832 .align 32 833 834#define FP_TRAP \ 835 TT_TRACE(trace_gen) ;\ 836 ba,pt %xcc,.fp_exception ;\ 837 nop ;\ 838 .align 32 839 840#if !defined(lint) 841/* 842 * asynchronous traps at level 0 and level 1 843 * 844 * The first instruction must be a membar for UltraSPARC-III 845 * to stop RED state entry if the store queue has many 846 * pending bad stores (PRM, Chapter 11). 847 */ 848#define ASYNC_TRAP(ttype, ttlabel, table_name)\ 849 .global table_name ;\ 850table_name: ;\ 851 membar #Sync ;\ 852 TT_TRACE(ttlabel) ;\ 853 ba async_err ;\ 854 mov ttype, %g5 ;\ 855 .align 32 856 857/* 858 * Defaults to BAD entry, but establishes label to be used for 859 * architecture-specific overwrite of trap table entry. 860 */ 861#define LABELED_BAD(table_name) \ 862 .global table_name ;\ 863table_name: ;\ 864 BAD 865 866#endif /* !lint */ 867 868/* 869 * illegal instruction trap 870 */ 871#define ILLTRAP_INSTR \ 872 membar #Sync ;\ 873 TT_TRACE(trace_gen) ;\ 874 or %g0, P_UTRAP4, %g2 ;\ 875 or %g0, T_UNIMP_INSTR, %g3 ;\ 876 sethi %hi(.check_v9utrap), %g4 ;\ 877 jmp %g4 + %lo(.check_v9utrap) ;\ 878 nop ;\ 879 .align 32 880 881/* 882 * tag overflow trap 883 */ 884#define TAG_OVERFLOW \ 885 TT_TRACE(trace_gen) ;\ 886 or %g0, P_UTRAP10, %g2 ;\ 887 or %g0, T_TAG_OVERFLOW, %g3 ;\ 888 sethi %hi(.check_v9utrap), %g4 ;\ 889 jmp %g4 + %lo(.check_v9utrap) ;\ 890 nop ;\ 891 .align 32 892 893/* 894 * divide by zero trap 895 */ 896#define DIV_BY_ZERO \ 897 TT_TRACE(trace_gen) ;\ 898 or %g0, P_UTRAP11, %g2 ;\ 899 or %g0, T_IDIV0, %g3 ;\ 900 sethi %hi(.check_v9utrap), %g4 ;\ 901 jmp %g4 + %lo(.check_v9utrap) ;\ 902 nop ;\ 903 .align 32 904 905/* 906 * trap instruction for V9 user trap handlers 907 */ 908#define TRAP_INSTR \ 909 TT_TRACE(trace_gen) ;\ 910 or %g0, T_SOFTWARE_TRAP, %g3 ;\ 911 sethi %hi(.check_v9utrap), %g4 ;\ 912 jmp %g4 + %lo(.check_v9utrap) ;\ 913 nop ;\ 914 .align 32 915#define TRP4 TRAP_INSTR; TRAP_INSTR; TRAP_INSTR; TRAP_INSTR 916 917/* 918 * LEVEL_INTERRUPT is for level N interrupts. 919 * VECTOR_INTERRUPT is for the vector trap. 920 */ 921#define LEVEL_INTERRUPT(level) \ 922 .global tt_pil/**/level ;\ 923tt_pil/**/level: ;\ 924 ba,pt %xcc, pil_interrupt ;\ 925 mov level, %g4 ;\ 926 .align 32 927 928#define LEVEL14_INTERRUPT \ 929 ba pil14_interrupt ;\ 930 mov PIL_14, %g4 ;\ 931 .align 32 932 933#define VECTOR_INTERRUPT \ 934 ldxa [%g0]ASI_INTR_RECEIVE_STATUS, %g1 ;\ 935 btst IRSR_BUSY, %g1 ;\ 936 bnz,pt %xcc, vec_interrupt ;\ 937 nop ;\ 938 ba,a,pt %xcc, vec_intr_spurious ;\ 939 .empty ;\ 940 .align 32 941 942/* 943 * MMU Trap Handlers. 944 */ 945#define SWITCH_GLOBALS /* mmu->alt, alt->mmu */ \ 946 rdpr %pstate, %g5 ;\ 947 wrpr %g5, PSTATE_MG | PSTATE_AG, %pstate 948 949#define IMMU_EXCEPTION \ 950 membar #Sync ;\ 951 SWITCH_GLOBALS ;\ 952 wr %g0, ASI_IMMU, %asi ;\ 953 rdpr %tpc, %g2 ;\ 954 ldxa [MMU_SFSR]%asi, %g3 ;\ 955 ba,pt %xcc, .mmu_exception_end ;\ 956 mov T_INSTR_EXCEPTION, %g1 ;\ 957 .align 32 958 959#define DMMU_EXCEPTION \ 960 SWITCH_GLOBALS ;\ 961 wr %g0, ASI_DMMU, %asi ;\ 962 ldxa [MMU_TAG_ACCESS]%asi, %g2 ;\ 963 ldxa [MMU_SFSR]%asi, %g3 ;\ 964 ba,pt %xcc, .mmu_exception_end ;\ 965 mov T_DATA_EXCEPTION, %g1 ;\ 966 .align 32 967 968#define DMMU_EXC_AG_PRIV \ 969 wr %g0, ASI_DMMU, %asi ;\ 970 ldxa [MMU_SFAR]%asi, %g2 ;\ 971 ba,pt %xcc, .mmu_priv_exception ;\ 972 ldxa [MMU_SFSR]%asi, %g3 ;\ 973 .align 32 974 975#define DMMU_EXC_AG_NOT_ALIGNED \ 976 wr %g0, ASI_DMMU, %asi ;\ 977 ldxa [MMU_SFAR]%asi, %g2 ;\ 978 ba,pt %xcc, .mmu_exception_not_aligned ;\ 979 ldxa [MMU_SFSR]%asi, %g3 ;\ 980 .align 32 981 982/* 983 * SPARC V9 IMPL. DEP. #109(1) and (2) and #110(1) and (2) 984 */ 985#define DMMU_EXC_LDDF_NOT_ALIGNED \ 986 btst 1, %sp ;\ 987 bnz,pt %xcc, .lddf_exception_not_aligned ;\ 988 wr %g0, ASI_DMMU, %asi ;\ 989 ldxa [MMU_SFAR]%asi, %g2 ;\ 990 ba,pt %xcc, .mmu_exception_not_aligned ;\ 991 ldxa [MMU_SFSR]%asi, %g3 ;\ 992 .align 32 993 994#define DMMU_EXC_STDF_NOT_ALIGNED \ 995 btst 1, %sp ;\ 996 bnz,pt %xcc, .stdf_exception_not_aligned ;\ 997 wr %g0, ASI_DMMU, %asi ;\ 998 ldxa [MMU_SFAR]%asi, %g2 ;\ 999 ba,pt %xcc, .mmu_exception_not_aligned ;\ 1000 ldxa [MMU_SFSR]%asi, %g3 ;\ 1001 .align 32 1002 1003/* 1004 * Flush the TLB using either the primary, secondary, or nucleus flush 1005 * operation based on whether the ctx from the tag access register matches 1006 * the primary or secondary context (flush the nucleus if neither matches). 1007 * 1008 * Requires a membar #Sync before next ld/st. 1009 * exits with: 1010 * g2 = tag access register 1011 * g3 = ctx number 1012 */ 1013#if TAGACC_CTX_MASK != CTXREG_CTX_MASK 1014#error "TAGACC_CTX_MASK != CTXREG_CTX_MASK" 1015#endif 1016#define DTLB_DEMAP_ENTRY \ 1017 mov MMU_TAG_ACCESS, %g1 ;\ 1018 mov MMU_PCONTEXT, %g5 ;\ 1019 ldxa [%g1]ASI_DMMU, %g2 ;\ 1020 sethi %hi(TAGACC_CTX_MASK), %g4 ;\ 1021 or %g4, %lo(TAGACC_CTX_MASK), %g4 ;\ 1022 and %g2, %g4, %g3 /* g3 = ctx */ ;\ 1023 ldxa [%g5]ASI_DMMU, %g6 /* g6 = primary ctx */ ;\ 1024 and %g6, %g4, %g6 /* &= CTXREG_CTX_MASK */ ;\ 1025 cmp %g3, %g6 ;\ 1026 be,pt %xcc, 1f ;\ 1027 andn %g2, %g4, %g1 /* ctx = primary */ ;\ 1028 mov MMU_SCONTEXT, %g5 ;\ 1029 ldxa [%g5]ASI_DMMU, %g6 /* g6 = secondary ctx */ ;\ 1030 and %g6, %g4, %g6 /* &= CTXREG_CTX_MASK */ ;\ 1031 cmp %g3, %g6 ;\ 1032 be,a,pt %xcc, 1f ;\ 1033 or %g1, DEMAP_SECOND, %g1 ;\ 1034 or %g1, DEMAP_NUCLEUS, %g1 ;\ 10351: stxa %g0, [%g1]ASI_DTLB_DEMAP /* MMU_DEMAP_PAGE */ ;\ 1036 membar #Sync 1037 1038#if defined(cscope) 1039/* 1040 * Define labels to direct cscope quickly to labels that 1041 * are generated by macro expansion of DTLB_MISS(). 1042 */ 1043 .global tt0_dtlbmiss 1044tt0_dtlbmiss: 1045 .global tt1_dtlbmiss 1046tt1_dtlbmiss: 1047 nop 1048#endif 1049 1050/* 1051 * Needs to be exactly 32 instructions 1052 * 1053 * UTLB NOTE: If we don't hit on the 8k pointer then we branch 1054 * to a special 4M tsb handler. It would be nice if that handler 1055 * could live in this file but currently it seems better to allow 1056 * it to fall thru to sfmmu_tsb_miss. 1057 */ 1058#ifdef UTSB_PHYS 1059#define DTLB_MISS(table_name) ;\ 1060 .global table_name/**/_dtlbmiss ;\ 1061table_name/**/_dtlbmiss: ;\ 1062 HAT_PERCPU_DBSTAT(TSBMISS_DTLBMISS) /* 3 instr ifdef DEBUG */ ;\ 1063 mov MMU_TAG_ACCESS, %g6 /* select tag acc */ ;\ 1064 ldxa [%g0]ASI_DMMU_TSB_8K, %g1 /* g1 = tsbe ptr */ ;\ 1065 ldxa [%g6]ASI_DMMU, %g2 /* g2 = tag access */ ;\ 1066 sllx %g2, TAGACC_CTX_LSHIFT, %g3 ;\ 1067 srlx %g3, TAGACC_CTX_LSHIFT, %g3 /* g3 = ctx */ ;\ 1068 cmp %g3, INVALID_CONTEXT ;\ 1069 ble,pn %xcc, sfmmu_kdtlb_miss ;\ 1070 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\ 1071 mov SCRATCHPAD_UTSBREG, %g3 ;\ 1072 ldxa [%g3]ASI_SCRATCHPAD, %g3 /* g3 = 2nd tsb reg */ ;\ 1073 brgez,pn %g3, sfmmu_udtlb_slowpath /* branch if 2 TSBs */ ;\ 1074 nop ;\ 1075 ldda [%g1]ASI_QUAD_LDD_PHYS, %g4 /* g4 = tag, %g5 data */;\ 1076 cmp %g4, %g7 ;\ 1077 bne,pn %xcc, sfmmu_tsb_miss_tt /* no 4M TSB, miss */ ;\ 1078 mov %g0, %g3 /* clear 4M tsbe ptr */ ;\ 1079 TT_TRACE(trace_tsbhit) /* 2 instr ifdef TRAPTRACE */ ;\ 1080 stxa %g5, [%g0]ASI_DTLB_IN /* trapstat expects TTE */ ;\ 1081 retry /* in %g5 */ ;\ 1082 unimp 0 ;\ 1083 unimp 0 ;\ 1084 unimp 0 ;\ 1085 unimp 0 ;\ 1086 unimp 0 ;\ 1087 unimp 0 ;\ 1088 unimp 0 ;\ 1089 unimp 0 ;\ 1090 unimp 0 ;\ 1091 .align 128 1092#else /* UTSB_PHYS */ 1093#define DTLB_MISS(table_name) ;\ 1094 .global table_name/**/_dtlbmiss ;\ 1095table_name/**/_dtlbmiss: ;\ 1096 HAT_PERCPU_DBSTAT(TSBMISS_DTLBMISS) /* 3 instr ifdef DEBUG */ ;\ 1097 mov MMU_TAG_ACCESS, %g6 /* select tag acc */ ;\ 1098 ldxa [%g0]ASI_DMMU_TSB_8K, %g1 /* g1 = tsbe ptr */ ;\ 1099 ldxa [%g6]ASI_DMMU, %g2 /* g2 = tag access */ ;\ 1100 sllx %g2, TAGACC_CTX_LSHIFT, %g3 ;\ 1101 srlx %g3, TAGACC_CTX_LSHIFT, %g3 /* g3 = ctx */ ;\ 1102 cmp %g3, INVALID_CONTEXT ;\ 1103 ble,pn %xcc, sfmmu_kdtlb_miss ;\ 1104 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\ 1105 brlz,pn %g1, sfmmu_udtlb_slowpath ;\ 1106 nop ;\ 1107 ldda [%g1]ASI_NQUAD_LD, %g4 /* g4 = tag, %g5 data */ ;\ 1108 cmp %g4, %g7 ;\ 1109 bne,pn %xcc, sfmmu_tsb_miss_tt /* no 4M TSB, miss */ ;\ 1110 mov %g0, %g3 /* clear 4M tsbe ptr */ ;\ 1111 TT_TRACE(trace_tsbhit) /* 2 instr ifdef TRAPTRACE */ ;\ 1112 stxa %g5, [%g0]ASI_DTLB_IN /* trapstat expects TTE */ ;\ 1113 retry /* in %g5 */ ;\ 1114 unimp 0 ;\ 1115 unimp 0 ;\ 1116 unimp 0 ;\ 1117 unimp 0 ;\ 1118 unimp 0 ;\ 1119 unimp 0 ;\ 1120 unimp 0 ;\ 1121 unimp 0 ;\ 1122 unimp 0 ;\ 1123 unimp 0 ;\ 1124 unimp 0 ;\ 1125 .align 128 1126#endif /* UTSB_PHYS */ 1127 1128#if defined(cscope) 1129/* 1130 * Define labels to direct cscope quickly to labels that 1131 * are generated by macro expansion of ITLB_MISS(). 1132 */ 1133 .global tt0_itlbmiss 1134tt0_itlbmiss: 1135 .global tt1_itlbmiss 1136tt1_itlbmiss: 1137 nop 1138#endif 1139 1140/* 1141 * Instruction miss handler. 1142 * ldda instructions will have their ASI patched 1143 * by sfmmu_patch_ktsb at runtime. 1144 * MUST be EXACTLY 32 instructions or we'll break. 1145 */ 1146#ifdef UTSB_PHYS 1147#define ITLB_MISS(table_name) \ 1148 .global table_name/**/_itlbmiss ;\ 1149table_name/**/_itlbmiss: ;\ 1150 HAT_PERCPU_DBSTAT(TSBMISS_ITLBMISS) /* 3 instr ifdef DEBUG */ ;\ 1151 mov MMU_TAG_ACCESS, %g6 /* select tag acc */ ;\ 1152 ldxa [%g0]ASI_IMMU_TSB_8K, %g1 /* g1 = tsbe ptr */ ;\ 1153 ldxa [%g6]ASI_IMMU, %g2 /* g2 = tag access */ ;\ 1154 sllx %g2, TAGACC_CTX_LSHIFT, %g3 ;\ 1155 srlx %g3, TAGACC_CTX_LSHIFT, %g3 /* g3 = ctx */ ;\ 1156 cmp %g3, INVALID_CONTEXT ;\ 1157 ble,pn %xcc, sfmmu_kitlb_miss ;\ 1158 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\ 1159 mov SCRATCHPAD_UTSBREG, %g3 ;\ 1160 ldxa [%g3]ASI_SCRATCHPAD, %g3 /* g3 = 2nd tsb reg */ ;\ 1161 brgez,pn %g3, sfmmu_uitlb_slowpath /* branch if 2 TSBs */ ;\ 1162 nop ;\ 1163 ldda [%g1]ASI_QUAD_LDD_PHYS, %g4 /* g4 = tag, g5 = data */ ;\ 1164 cmp %g4, %g7 ;\ 1165 bne,pn %xcc, sfmmu_tsb_miss_tt /* br if 8k ptr miss */ ;\ 1166 mov %g0, %g3 /* no 4M TSB */ ;\ 1167 andcc %g5, TTE_EXECPRM_INT, %g0 /* check execute bit */ ;\ 1168 bz,pn %icc, exec_fault ;\ 1169 nop ;\ 1170 TT_TRACE(trace_tsbhit) /* 2 instr ifdef TRAPTRACE */ ;\ 1171 stxa %g5, [%g0]ASI_ITLB_IN /* trapstat expects %g5 */ ;\ 1172 retry ;\ 1173 unimp 0 ;\ 1174 unimp 0 ;\ 1175 unimp 0 ;\ 1176 unimp 0 ;\ 1177 unimp 0 ;\ 1178 unimp 0 ;\ 1179 .align 128 1180#else /* UTSB_PHYS */ 1181#define ITLB_MISS(table_name) \ 1182 .global table_name/**/_itlbmiss ;\ 1183table_name/**/_itlbmiss: ;\ 1184 HAT_PERCPU_DBSTAT(TSBMISS_ITLBMISS) /* 3 instr ifdef DEBUG */ ;\ 1185 mov MMU_TAG_ACCESS, %g6 /* select tag acc */ ;\ 1186 ldxa [%g0]ASI_IMMU_TSB_8K, %g1 /* g1 = tsbe ptr */ ;\ 1187 ldxa [%g6]ASI_IMMU, %g2 /* g2 = tag access */ ;\ 1188 sllx %g2, TAGACC_CTX_LSHIFT, %g3 ;\ 1189 srlx %g3, TAGACC_CTX_LSHIFT, %g3 /* g3 = ctx */ ;\ 1190 cmp %g3, INVALID_CONTEXT ;\ 1191 ble,pn %xcc, sfmmu_kitlb_miss ;\ 1192 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\ 1193 brlz,pn %g1, sfmmu_uitlb_slowpath /* if >1 TSB branch */ ;\ 1194 nop ;\ 1195 ldda [%g1]ASI_NQUAD_LD, %g4 /* g4 = tag, g5 = data */ ;\ 1196 cmp %g4, %g7 ;\ 1197 bne,pn %xcc, sfmmu_tsb_miss_tt /* br if 8k ptr miss */ ;\ 1198 mov %g0, %g3 /* no 4M TSB */ ;\ 1199 andcc %g5, TTE_EXECPRM_INT, %g0 /* check execute bit */ ;\ 1200 bz,pn %icc, exec_fault ;\ 1201 nop ;\ 1202 TT_TRACE(trace_tsbhit) /* 2 instr ifdef TRAPTRACE */ ;\ 1203 stxa %g5, [%g0]ASI_ITLB_IN /* trapstat expects %g5 */ ;\ 1204 retry ;\ 1205 unimp 0 ;\ 1206 unimp 0 ;\ 1207 unimp 0 ;\ 1208 unimp 0 ;\ 1209 unimp 0 ;\ 1210 unimp 0 ;\ 1211 unimp 0 ;\ 1212 unimp 0 ;\ 1213 .align 128 1214#endif /* UTSB_PHYS */ 1215 1216 1217/* 1218 * This macro is the first level handler for fast protection faults. 1219 * It first demaps the tlb entry which generated the fault and then 1220 * attempts to set the modify bit on the hash. It needs to be 1221 * exactly 32 instructions. 1222 */ 1223#define DTLB_PROT \ 1224 DTLB_DEMAP_ENTRY /* 20 instructions */ ;\ 1225 /* ;\ 1226 * At this point: ;\ 1227 * g1 = ???? ;\ 1228 * g2 = tag access register ;\ 1229 * g3 = ctx number ;\ 1230 * g4 = ???? ;\ 1231 */ ;\ 1232 TT_TRACE(trace_dataprot) /* 2 instr ifdef TRAPTRACE */ ;\ 1233 /* clobbers g1 and g6 */ ;\ 1234 ldxa [%g0]ASI_DMMU_TSB_8K, %g1 /* g1 = tsbe ptr */ ;\ 1235 brnz,pt %g3, sfmmu_uprot_trap /* user trap */ ;\ 1236 nop ;\ 1237 ba,a,pt %xcc, sfmmu_kprot_trap /* kernel trap */ ;\ 1238 unimp 0 ;\ 1239 unimp 0 ;\ 1240 unimp 0 ;\ 1241 unimp 0 ;\ 1242 unimp 0 ;\ 1243 unimp 0 ;\ 1244 .align 128 1245 1246#define DMMU_EXCEPTION_TL1 ;\ 1247 SWITCH_GLOBALS ;\ 1248 ba,a,pt %xcc, mmu_trap_tl1 ;\ 1249 nop ;\ 1250 .align 32 1251 1252#define MISALIGN_ADDR_TL1 ;\ 1253 ba,a,pt %xcc, mmu_trap_tl1 ;\ 1254 nop ;\ 1255 .align 32 1256 1257/* 1258 * Trace a tsb hit 1259 * g1 = tsbe pointer (in/clobbered) 1260 * g2 = tag access register (in) 1261 * g3 - g4 = scratch (clobbered) 1262 * g5 = tsbe data (in) 1263 * g6 = scratch (clobbered) 1264 * g7 = pc we jumped here from (in) 1265 * ttextra = value to OR in to trap type (%tt) (in) 1266 */ 1267#ifdef TRAPTRACE 1268#define TRACE_TSBHIT(ttextra) \ 1269 membar #Sync ;\ 1270 sethi %hi(FLUSH_ADDR), %g6 ;\ 1271 flush %g6 ;\ 1272 TRACE_PTR(%g3, %g6) ;\ 1273 GET_TRACE_TICK(%g6) ;\ 1274 stxa %g6, [%g3 + TRAP_ENT_TICK]%asi ;\ 1275 stxa %g2, [%g3 + TRAP_ENT_SP]%asi /* tag access */ ;\ 1276 stxa %g5, [%g3 + TRAP_ENT_F1]%asi /* tsb data */ ;\ 1277 rdpr %tnpc, %g6 ;\ 1278 stxa %g6, [%g3 + TRAP_ENT_F2]%asi ;\ 1279 stxa %g1, [%g3 + TRAP_ENT_F3]%asi /* tsb pointer */ ;\ 1280 stxa %g0, [%g3 + TRAP_ENT_F4]%asi ;\ 1281 rdpr %tpc, %g6 ;\ 1282 stxa %g6, [%g3 + TRAP_ENT_TPC]%asi ;\ 1283 rdpr %tl, %g6 ;\ 1284 stha %g6, [%g3 + TRAP_ENT_TL]%asi ;\ 1285 rdpr %tt, %g6 ;\ 1286 or %g6, (ttextra), %g6 ;\ 1287 stha %g6, [%g3 + TRAP_ENT_TT]%asi ;\ 1288 ldxa [%g0]ASI_IMMU, %g1 /* tag target */ ;\ 1289 ldxa [%g0]ASI_DMMU, %g4 ;\ 1290 cmp %g6, FAST_IMMU_MISS_TT ;\ 1291 movne %icc, %g4, %g1 ;\ 1292 stxa %g1, [%g3 + TRAP_ENT_TSTATE]%asi /* tsb tag */ ;\ 1293 stxa %g0, [%g3 + TRAP_ENT_TR]%asi ;\ 1294 TRACE_NEXT(%g3, %g4, %g6) 1295#else 1296#define TRACE_TSBHIT(ttextra) 1297#endif 1298 1299#if defined(lint) 1300 1301struct scb trap_table; 1302struct scb scb; /* trap_table/scb are the same object */ 1303 1304#else /* lint */ 1305 1306/* 1307 * ======================================================================= 1308 * SPARC V9 TRAP TABLE 1309 * 1310 * The trap table is divided into two halves: the first half is used when 1311 * taking traps when TL=0; the second half is used when taking traps from 1312 * TL>0. Note that handlers in the second half of the table might not be able 1313 * to make the same assumptions as handlers in the first half of the table. 1314 * 1315 * Worst case trap nesting so far: 1316 * 1317 * at TL=0 client issues software trap requesting service 1318 * at TL=1 nucleus wants a register window 1319 * at TL=2 register window clean/spill/fill takes a TLB miss 1320 * at TL=3 processing TLB miss 1321 * at TL=4 handle asynchronous error 1322 * 1323 * Note that a trap from TL=4 to TL=5 places Spitfire in "RED mode". 1324 * 1325 * ======================================================================= 1326 */ 1327 .section ".text" 1328 .align 4 1329 .global trap_table, scb, trap_table0, trap_table1, etrap_table 1330 .type trap_table, #object 1331 .type scb, #object 1332trap_table: 1333scb: 1334trap_table0: 1335 /* hardware traps */ 1336 NOT; /* 000 reserved */ 1337 RED; /* 001 power on reset */ 1338 RED; /* 002 watchdog reset */ 1339 RED; /* 003 externally initiated reset */ 1340 RED; /* 004 software initiated reset */ 1341 RED; /* 005 red mode exception */ 1342 NOT; NOT; /* 006 - 007 reserved */ 1343 IMMU_EXCEPTION; /* 008 instruction access exception */ 1344 NOT; /* 009 instruction access MMU miss */ 1345 ASYNC_TRAP(T_INSTR_ERROR, trace_gen, tt0_iae); 1346 /* 00A instruction access error */ 1347 NOT; NOT4; /* 00B - 00F reserved */ 1348 ILLTRAP_INSTR; /* 010 illegal instruction */ 1349 TRAP(T_PRIV_INSTR); /* 011 privileged opcode */ 1350 NOT; /* 012 unimplemented LDD */ 1351 NOT; /* 013 unimplemented STD */ 1352 NOT4; NOT4; NOT4; /* 014 - 01F reserved */ 1353 FP_DISABLED_TRAP; /* 020 fp disabled */ 1354 FP_IEEE_TRAP; /* 021 fp exception ieee 754 */ 1355 FP_TRAP; /* 022 fp exception other */ 1356 TAG_OVERFLOW; /* 023 tag overflow */ 1357 CLEAN_WINDOW; /* 024 - 027 clean window */ 1358 DIV_BY_ZERO; /* 028 division by zero */ 1359 NOT; /* 029 internal processor error */ 1360 NOT; NOT; NOT4; /* 02A - 02F reserved */ 1361 DMMU_EXCEPTION; /* 030 data access exception */ 1362 NOT; /* 031 data access MMU miss */ 1363 ASYNC_TRAP(T_DATA_ERROR, trace_gen, tt0_dae); 1364 /* 032 data access error */ 1365 NOT; /* 033 data access protection */ 1366 DMMU_EXC_AG_NOT_ALIGNED; /* 034 mem address not aligned */ 1367 DMMU_EXC_LDDF_NOT_ALIGNED; /* 035 LDDF mem address not aligned */ 1368 DMMU_EXC_STDF_NOT_ALIGNED; /* 036 STDF mem address not aligned */ 1369 DMMU_EXC_AG_PRIV; /* 037 privileged action */ 1370 NOT; /* 038 LDQF mem address not aligned */ 1371 NOT; /* 039 STQF mem address not aligned */ 1372 NOT; NOT; NOT4; /* 03A - 03F reserved */ 1373 LABELED_BAD(tt0_asdat); /* 040 async data error */ 1374 LEVEL_INTERRUPT(1); /* 041 interrupt level 1 */ 1375 LEVEL_INTERRUPT(2); /* 042 interrupt level 2 */ 1376 LEVEL_INTERRUPT(3); /* 043 interrupt level 3 */ 1377 LEVEL_INTERRUPT(4); /* 044 interrupt level 4 */ 1378 LEVEL_INTERRUPT(5); /* 045 interrupt level 5 */ 1379 LEVEL_INTERRUPT(6); /* 046 interrupt level 6 */ 1380 LEVEL_INTERRUPT(7); /* 047 interrupt level 7 */ 1381 LEVEL_INTERRUPT(8); /* 048 interrupt level 8 */ 1382 LEVEL_INTERRUPT(9); /* 049 interrupt level 9 */ 1383 LEVEL_INTERRUPT(10); /* 04A interrupt level 10 */ 1384 LEVEL_INTERRUPT(11); /* 04B interrupt level 11 */ 1385 LEVEL_INTERRUPT(12); /* 04C interrupt level 12 */ 1386 LEVEL_INTERRUPT(13); /* 04D interrupt level 13 */ 1387 LEVEL14_INTERRUPT; /* 04E interrupt level 14 */ 1388 LEVEL_INTERRUPT(15); /* 04F interrupt level 15 */ 1389 NOT4; NOT4; NOT4; NOT4; /* 050 - 05F reserved */ 1390 VECTOR_INTERRUPT; /* 060 interrupt vector */ 1391 GOTO(kmdb_trap); /* 061 PA watchpoint */ 1392 GOTO(kmdb_trap); /* 062 VA watchpoint */ 1393 GOTO_TT(ce_err, trace_gen); /* 063 corrected ECC error */ 1394 ITLB_MISS(tt0); /* 064 instruction access MMU miss */ 1395 DTLB_MISS(tt0); /* 068 data access MMU miss */ 1396 DTLB_PROT; /* 06C data access protection */ 1397 LABELED_BAD(tt0_fecc); /* 070 fast ecache ECC error */ 1398 LABELED_BAD(tt0_dperr); /* 071 Cheetah+ dcache parity error */ 1399 LABELED_BAD(tt0_iperr); /* 072 Cheetah+ icache parity error */ 1400 NOT; /* 073 reserved */ 1401 NOT4; NOT4; NOT4; /* 074 - 07F reserved */ 1402 NOT4; /* 080 spill 0 normal */ 1403 SPILL_32bit_asi(ASI_AIUP,sn0); /* 084 spill 1 normal */ 1404 SPILL_64bit_asi(ASI_AIUP,sn0); /* 088 spill 2 normal */ 1405 SPILL_32clean(ASI_AIUP,sn0); /* 08C spill 3 normal */ 1406 SPILL_64clean(ASI_AIUP,sn0); /* 090 spill 4 normal */ 1407 SPILL_32bit(not); /* 094 spill 5 normal */ 1408 SPILL_64bit(not); /* 098 spill 6 normal */ 1409 SPILL_mixed; /* 09C spill 7 normal */ 1410 NOT4; /* 0A0 spill 0 other */ 1411 SPILL_32bit_asi(ASI_AIUS,so0); /* 0A4 spill 1 other */ 1412 SPILL_64bit_asi(ASI_AIUS,so0); /* 0A8 spill 2 other */ 1413 SPILL_32bit_asi(ASI_AIUS,so0); /* 0AC spill 3 other */ 1414 SPILL_64bit_asi(ASI_AIUS,so0); /* 0B0 spill 4 other */ 1415 NOT4; /* 0B4 spill 5 other */ 1416 NOT4; /* 0B8 spill 6 other */ 1417 NOT4; /* 0BC spill 7 other */ 1418 NOT4; /* 0C0 fill 0 normal */ 1419 FILL_32bit_asi(ASI_AIUP,fn0); /* 0C4 fill 1 normal */ 1420 FILL_64bit_asi(ASI_AIUP,fn0); /* 0C8 fill 2 normal */ 1421 FILL_32bit_asi(ASI_AIUP,fn0); /* 0CC fill 3 normal */ 1422 FILL_64bit_asi(ASI_AIUP,fn0); /* 0D0 fill 4 normal */ 1423 FILL_32bit(not); /* 0D4 fill 5 normal */ 1424 FILL_64bit(not); /* 0D8 fill 6 normal */ 1425 FILL_mixed; /* 0DC fill 7 normal */ 1426 NOT4; /* 0E0 fill 0 other */ 1427 NOT4; /* 0E4 fill 1 other */ 1428 NOT4; /* 0E8 fill 2 other */ 1429 NOT4; /* 0EC fill 3 other */ 1430 NOT4; /* 0F0 fill 4 other */ 1431 NOT4; /* 0F4 fill 5 other */ 1432 NOT4; /* 0F8 fill 6 other */ 1433 NOT4; /* 0FC fill 7 other */ 1434 /* user traps */ 1435 GOTO(syscall_trap_4x); /* 100 old system call */ 1436 TRAP(T_BREAKPOINT); /* 101 user breakpoint */ 1437 TRAP(T_DIV0); /* 102 user divide by zero */ 1438 FLUSHW(); /* 103 flush windows */ 1439 GOTO(.clean_windows); /* 104 clean windows */ 1440 BAD; /* 105 range check ?? */ 1441 GOTO(.fix_alignment); /* 106 do unaligned references */ 1442 BAD; /* 107 unused */ 1443 SYSCALL(syscall_trap32); /* 108 ILP32 system call on LP64 */ 1444 GOTO(set_trap0_addr); /* 109 set trap0 address */ 1445 BAD; BAD; BAD4; /* 10A - 10F unused */ 1446 TRP4; TRP4; TRP4; TRP4; /* 110 - 11F V9 user trap handlers */ 1447 GOTO(.getcc); /* 120 get condition codes */ 1448 GOTO(.setcc); /* 121 set condition codes */ 1449 GOTO(.getpsr); /* 122 get psr */ 1450 GOTO(.setpsr); /* 123 set psr (some fields) */ 1451 GOTO(get_timestamp); /* 124 get timestamp */ 1452 GOTO(get_virtime); /* 125 get lwp virtual time */ 1453 PRIV(self_xcall); /* 126 self xcall */ 1454 GOTO(get_hrestime); /* 127 get hrestime */ 1455 BAD; /* 128 ST_SETV9STACK */ 1456 GOTO(.getlgrp); /* 129 get lgrpid */ 1457 BAD; BAD; BAD4; /* 12A - 12F unused */ 1458 BAD4; BAD4; /* 130 - 137 unused */ 1459 DTRACE_PID; /* 138 dtrace pid tracing provider */ 1460 BAD; /* 139 unused */ 1461 DTRACE_RETURN; /* 13A dtrace pid return probe */ 1462 BAD; BAD4; /* 13B - 13F unused */ 1463 SYSCALL(syscall_trap) /* 140 LP64 system call */ 1464 SYSCALL(nosys); /* 141 unused system call trap */ 1465#ifdef DEBUG_USER_TRAPTRACECTL 1466 GOTO(.traptrace_freeze); /* 142 freeze traptrace */ 1467 GOTO(.traptrace_unfreeze); /* 143 unfreeze traptrace */ 1468#else 1469 SYSCALL(nosys); /* 142 unused system call trap */ 1470 SYSCALL(nosys); /* 143 unused system call trap */ 1471#endif 1472 BAD4; BAD4; BAD4; /* 144 - 14F unused */ 1473 BAD4; BAD4; BAD4; BAD4; /* 150 - 15F unused */ 1474 BAD4; BAD4; BAD4; BAD4; /* 160 - 16F unused */ 1475 BAD; /* 170 - unused */ 1476 BAD; /* 171 - unused */ 1477 BAD; BAD; /* 172 - 173 unused */ 1478 BAD4; BAD4; /* 174 - 17B unused */ 1479#ifdef PTL1_PANIC_DEBUG 1480 mov PTL1_BAD_DEBUG, %g1; GOTO(ptl1_panic); 1481 /* 17C test ptl1_panic */ 1482#else 1483 BAD; /* 17C unused */ 1484#endif /* PTL1_PANIC_DEBUG */ 1485 PRIV(kmdb_trap); /* 17D kmdb enter (L1-A) */ 1486 PRIV(kmdb_trap); /* 17E kmdb breakpoint */ 1487 PRIV(kctx_obp_bpt); /* 17F obp breakpoint */ 1488 /* reserved */ 1489 NOT4; NOT4; NOT4; NOT4; /* 180 - 18F reserved */ 1490 NOT4; NOT4; NOT4; NOT4; /* 190 - 19F reserved */ 1491 NOT4; NOT4; NOT4; NOT4; /* 1A0 - 1AF reserved */ 1492 NOT4; NOT4; NOT4; NOT4; /* 1B0 - 1BF reserved */ 1493 NOT4; NOT4; NOT4; NOT4; /* 1C0 - 1CF reserved */ 1494 NOT4; NOT4; NOT4; NOT4; /* 1D0 - 1DF reserved */ 1495 NOT4; NOT4; NOT4; NOT4; /* 1E0 - 1EF reserved */ 1496 NOT4; NOT4; NOT4; NOT4; /* 1F0 - 1FF reserved */ 1497trap_table1: 1498 NOT4; NOT4; NOT; NOT; /* 000 - 009 unused */ 1499 ASYNC_TRAP(T_INSTR_ERROR + T_TL1, trace_gen, tt1_iae); 1500 /* 00A instruction access error */ 1501 NOT; NOT4; /* 00B - 00F unused */ 1502 NOT4; NOT4; NOT4; NOT4; /* 010 - 01F unused */ 1503 NOT4; /* 020 - 023 unused */ 1504 CLEAN_WINDOW; /* 024 - 027 clean window */ 1505 NOT4; NOT4; /* 028 - 02F unused */ 1506 DMMU_EXCEPTION_TL1; /* 030 data access exception */ 1507 NOT; /* 031 unused */ 1508 ASYNC_TRAP(T_DATA_ERROR + T_TL1, trace_gen, tt1_dae); 1509 /* 032 data access error */ 1510 NOT; /* 033 unused */ 1511 MISALIGN_ADDR_TL1; /* 034 mem address not aligned */ 1512 NOT; NOT; NOT; NOT4; NOT4 /* 035 - 03F unused */ 1513 LABELED_BAD(tt1_asdat); /* 040 async data error */ 1514 NOT; NOT; NOT; /* 041 - 043 unused */ 1515 NOT4; NOT4; NOT4; /* 044 - 04F unused */ 1516 NOT4; NOT4; NOT4; NOT4; /* 050 - 05F unused */ 1517 NOT; /* 060 unused */ 1518 GOTO(kmdb_trap_tl1); /* 061 PA watchpoint */ 1519 GOTO(kmdb_trap_tl1); /* 062 VA watchpoint */ 1520 GOTO_TT(ce_err_tl1, trace_gen); /* 063 corrected ECC error */ 1521 ITLB_MISS(tt1); /* 064 instruction access MMU miss */ 1522 DTLB_MISS(tt1); /* 068 data access MMU miss */ 1523 DTLB_PROT; /* 06C data access protection */ 1524 LABELED_BAD(tt1_fecc); /* 070 fast ecache ECC error */ 1525 LABELED_BAD(tt1_dperr); /* 071 Cheetah+ dcache parity error */ 1526 LABELED_BAD(tt1_iperr); /* 072 Cheetah+ icache parity error */ 1527 NOT; /* 073 reserved */ 1528 NOT4; NOT4; NOT4; /* 074 - 07F reserved */ 1529 NOT4; /* 080 spill 0 normal */ 1530 SPILL_32bit_tt1(ASI_AIUP,sn1); /* 084 spill 1 normal */ 1531 SPILL_64bit_tt1(ASI_AIUP,sn1); /* 088 spill 2 normal */ 1532 SPILL_32bit_tt1(ASI_AIUP,sn1); /* 08C spill 3 normal */ 1533 SPILL_64bit_tt1(ASI_AIUP,sn1); /* 090 spill 4 normal */ 1534 SPILL_32bit(not); /* 094 spill 5 normal */ 1535 SPILL_64bit(not); /* 098 spill 6 normal */ 1536 SPILL_mixed; /* 09C spill 7 normal */ 1537 NOT4; /* 0A0 spill 0 other */ 1538 SPILL_32bit_tt1(ASI_AIUS,so1); /* 0A4 spill 1 other */ 1539 SPILL_64bit_tt1(ASI_AIUS,so1); /* 0A8 spill 2 other */ 1540 SPILL_32bit_tt1(ASI_AIUS,so1); /* 0AC spill 3 other */ 1541 SPILL_64bit_tt1(ASI_AIUS,so1); /* 0B0 spill 4 other */ 1542 NOT4; /* 0B4 spill 5 other */ 1543 NOT4; /* 0B8 spill 6 other */ 1544 NOT4; /* 0BC spill 7 other */ 1545 NOT4; /* 0C0 fill 0 normal */ 1546 FILL_32bit_tt1(ASI_AIUP,fn1); /* 0C4 fill 1 normal */ 1547 FILL_64bit_tt1(ASI_AIUP,fn1); /* 0C8 fill 2 normal */ 1548 FILL_32bit_tt1(ASI_AIUP,fn1); /* 0CC fill 3 normal */ 1549 FILL_64bit_tt1(ASI_AIUP,fn1); /* 0D0 fill 4 normal */ 1550 FILL_32bit(not); /* 0D4 fill 5 normal */ 1551 FILL_64bit(not); /* 0D8 fill 6 normal */ 1552 FILL_mixed; /* 0DC fill 7 normal */ 1553 NOT4; NOT4; NOT4; NOT4; /* 0E0 - 0EF unused */ 1554 NOT4; NOT4; NOT4; NOT4; /* 0F0 - 0FF unused */ 1555 LABELED_BAD(tt1_swtrap0); /* 100 fast ecache ECC error (cont) */ 1556 LABELED_BAD(tt1_swtrap1); /* 101 Ch+ D$ parity error (cont) */ 1557 LABELED_BAD(tt1_swtrap2); /* 102 Ch+ I$ parity error (cont) */ 1558 NOT; /* 103 reserved */ 1559/* 1560 * We only reserve the above four special case soft traps for code running 1561 * at TL>0, so we can truncate the trap table here. 1562 */ 1563etrap_table: 1564 .size trap_table, (.-trap_table) 1565 .size scb, (.-scb) 1566 1567/* 1568 * We get to exec_fault in the case of an instruction miss and tte 1569 * has no execute bit set. We go to tl0 to handle it. 1570 * 1571 * g1 = tsbe pointer (in/clobbered) 1572 * g2 = tag access register (in) 1573 * g3 - g4 = scratch (clobbered) 1574 * g5 = tsbe data (in) 1575 * g6 = scratch (clobbered) 1576 */ 1577 ALTENTRY(exec_fault) 1578 TRACE_TSBHIT(0x200) 1579 SWITCH_GLOBALS 1580 mov MMU_TAG_ACCESS, %g4 1581 ldxa [%g4]ASI_IMMU, %g2 ! arg1 = addr 1582 mov T_INSTR_MMU_MISS, %g3 ! arg2 = traptype 1583 set trap, %g1 1584 ba,pt %xcc, sys_trap 1585 mov -1, %g4 1586 1587.mmu_exception_not_aligned: 1588 rdpr %tstate, %g1 1589 btst TSTATE_PRIV, %g1 1590 bnz,pn %icc, 2f 1591 nop 1592 CPU_ADDR(%g1, %g4) ! load CPU struct addr 1593 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer 1594 ldn [%g1 + T_PROCP], %g1 ! load proc pointer 1595 ldn [%g1 + P_UTRAPS], %g5 ! are there utraps? 1596 brz,pt %g5, 2f 1597 nop 1598 ldn [%g5 + P_UTRAP15], %g5 ! unaligned utrap? 1599 brz,pn %g5, 2f 1600 nop 1601 btst 1, %sp 1602 bz,pt %xcc, 1f ! 32 bit user program 1603 nop 1604 ba,pt %xcc, .setup_v9utrap ! 64 bit user program 1605 nop 16061: 1607 ba,pt %xcc, .setup_utrap 1608 or %g2, %g0, %g7 16092: 1610 ba,pt %xcc, .mmu_exception_end 1611 mov T_ALIGNMENT, %g1 1612 1613.mmu_priv_exception: 1614 rdpr %tstate, %g1 1615 btst TSTATE_PRIV, %g1 1616 bnz,pn %icc, 1f 1617 nop 1618 CPU_ADDR(%g1, %g4) ! load CPU struct addr 1619 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer 1620 ldn [%g1 + T_PROCP], %g1 ! load proc pointer 1621 ldn [%g1 + P_UTRAPS], %g5 ! are there utraps? 1622 brz,pt %g5, 1f 1623 nop 1624 ldn [%g5 + P_UTRAP16], %g5 1625 brnz,pt %g5, .setup_v9utrap 1626 nop 16271: 1628 mov T_PRIV_INSTR, %g1 1629 1630.mmu_exception_end: 1631 CPU_INDEX(%g4, %g5) 1632 set cpu_core, %g5 1633 sllx %g4, CPU_CORE_SHIFT, %g4 1634 add %g4, %g5, %g4 1635 lduh [%g4 + CPUC_DTRACE_FLAGS], %g5 1636 andcc %g5, CPU_DTRACE_NOFAULT, %g0 1637 bz %xcc, .mmu_exception_tlb_chk 1638 or %g5, CPU_DTRACE_BADADDR, %g5 1639 stuh %g5, [%g4 + CPUC_DTRACE_FLAGS] 1640 done 1641 1642.mmu_exception_tlb_chk: 1643 GET_CPU_IMPL(%g5) ! check SFSR.FT to see if this 1644 cmp %g5, PANTHER_IMPL ! is a TLB parity error. But 1645 bne 2f ! we only do this check while 1646 mov 1, %g4 ! running on Panther CPUs 1647 sllx %g4, PN_SFSR_PARITY_SHIFT, %g4 ! since US-I/II use the same 1648 andcc %g3, %g4, %g0 ! bit for something else which 1649 bz 2f ! will be handled later. 1650 nop 1651.mmu_exception_is_tlb_parity: 1652 .weak itlb_parity_trap 1653 .weak dtlb_parity_trap 1654 set itlb_parity_trap, %g4 1655 cmp %g1, T_INSTR_EXCEPTION ! branch to the itlb or 1656 be 3f ! dtlb parity handler 1657 nop ! if this trap is due 1658 set dtlb_parity_trap, %g4 1659 cmp %g1, T_DATA_EXCEPTION ! to a IMMU exception 1660 be 3f ! or DMMU exception. 1661 nop 16622: 1663 sllx %g3, 32, %g3 1664 or %g3, %g1, %g3 1665 set trap, %g1 1666 ba,pt %xcc, sys_trap 1667 sub %g0, 1, %g4 16683: 1669 jmp %g4 ! off to the appropriate 1670 nop ! TLB parity handler 1671 1672.fp_disabled: 1673 CPU_ADDR(%g1, %g4) ! load CPU struct addr 1674 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer 1675#ifdef SF_ERRATA_30 /* call causes fp-disabled */ 1676 brz,a,pn %g1, 2f 1677 nop 1678#endif 1679 rdpr %tstate, %g4 1680 btst TSTATE_PRIV, %g4 1681#ifdef SF_ERRATA_30 /* call causes fp-disabled */ 1682 bnz,pn %icc, 2f 1683 nop 1684#else 1685 bnz,a,pn %icc, ptl1_panic 1686 mov PTL1_BAD_FPTRAP, %g1 1687#endif 1688 ldn [%g1 + T_PROCP], %g1 ! load proc pointer 1689 ldn [%g1 + P_UTRAPS], %g5 ! are there utraps? 1690 brz,a,pt %g5, 2f 1691 nop 1692 ldn [%g5 + P_UTRAP7], %g5 ! fp_disabled utrap? 1693 brz,a,pn %g5, 2f 1694 nop 1695 btst 1, %sp 1696 bz,a,pt %xcc, 1f ! 32 bit user program 1697 nop 1698 ba,a,pt %xcc, .setup_v9utrap ! 64 bit user program 1699 nop 17001: 1701 ba,pt %xcc, .setup_utrap 1702 or %g0, %g0, %g7 17032: 1704 set fp_disabled, %g1 1705 ba,pt %xcc, sys_trap 1706 sub %g0, 1, %g4 1707 1708.fp_ieee_exception: 1709 rdpr %tstate, %g1 1710 btst TSTATE_PRIV, %g1 1711 bnz,a,pn %icc, ptl1_panic 1712 mov PTL1_BAD_FPTRAP, %g1 1713 CPU_ADDR(%g1, %g4) ! load CPU struct addr 1714 stx %fsr, [%g1 + CPU_TMP1] 1715 ldx [%g1 + CPU_TMP1], %g2 1716 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer 1717 ldn [%g1 + T_PROCP], %g1 ! load proc pointer 1718 ldn [%g1 + P_UTRAPS], %g5 ! are there utraps? 1719 brz,a,pt %g5, 1f 1720 nop 1721 ldn [%g5 + P_UTRAP8], %g5 1722 brnz,a,pt %g5, .setup_v9utrap 1723 nop 17241: 1725 set _fp_ieee_exception, %g1 1726 ba,pt %xcc, sys_trap 1727 sub %g0, 1, %g4 1728 1729/* 1730 * Register Inputs: 1731 * %g5 user trap handler 1732 * %g7 misaligned addr - for alignment traps only 1733 */ 1734.setup_utrap: 1735 set trap, %g1 ! setup in case we go 1736 mov T_FLUSH_PCB, %g3 ! through sys_trap on 1737 sub %g0, 1, %g4 ! the save instruction below 1738 1739 /* 1740 * If the DTrace pid provider is single stepping a copied-out 1741 * instruction, t->t_dtrace_step will be set. In that case we need 1742 * to abort the single-stepping (since execution of the instruction 1743 * was interrupted) and use the value of t->t_dtrace_npc as the %npc. 1744 */ 1745 save %sp, -SA(MINFRAME32), %sp ! window for trap handler 1746 CPU_ADDR(%g1, %g4) ! load CPU struct addr 1747 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer 1748 ldub [%g1 + T_DTRACE_STEP], %g2 ! load t->t_dtrace_step 1749 rdpr %tnpc, %l2 ! arg1 == tnpc 1750 brz,pt %g2, 1f 1751 rdpr %tpc, %l1 ! arg0 == tpc 1752 1753 ldub [%g1 + T_DTRACE_AST], %g2 ! load t->t_dtrace_ast 1754 ldn [%g1 + T_DTRACE_NPC], %l2 ! arg1 = t->t_dtrace_npc (step) 1755 brz,pt %g2, 1f 1756 st %g0, [%g1 + T_DTRACE_FT] ! zero all pid provider flags 1757 stub %g2, [%g1 + T_ASTFLAG] ! aston(t) if t->t_dtrace_ast 17581: 1759 mov %g7, %l3 ! arg2 == misaligned address 1760 1761 rdpr %tstate, %g1 ! cwp for trap handler 1762 rdpr %cwp, %g4 1763 bclr TSTATE_CWP_MASK, %g1 1764 wrpr %g1, %g4, %tstate 1765 wrpr %g0, %g5, %tnpc ! trap handler address 1766 FAST_TRAP_DONE 1767 /* NOTREACHED */ 1768 1769.check_v9utrap: 1770 rdpr %tstate, %g1 1771 btst TSTATE_PRIV, %g1 1772 bnz,a,pn %icc, 3f 1773 nop 1774 CPU_ADDR(%g4, %g1) ! load CPU struct addr 1775 ldn [%g4 + CPU_THREAD], %g5 ! load thread pointer 1776 ldn [%g5 + T_PROCP], %g5 ! load proc pointer 1777 ldn [%g5 + P_UTRAPS], %g5 ! are there utraps? 1778 1779 cmp %g3, T_SOFTWARE_TRAP 1780 bne,a,pt %icc, 1f 1781 nop 1782 1783 brz,pt %g5, 3f ! if p_utraps == NULL goto trap() 1784 rdpr %tt, %g3 ! delay - get actual hw trap type 1785 1786 sub %g3, 254, %g1 ! UT_TRAP_INSTRUCTION_16 = p_utraps[18] 1787 ba,pt %icc, 2f 1788 smul %g1, CPTRSIZE, %g2 17891: 1790 brz,a,pt %g5, 3f ! if p_utraps == NULL goto trap() 1791 nop 1792 1793 cmp %g3, T_UNIMP_INSTR 1794 bne,a,pt %icc, 2f 1795 nop 1796 1797 mov 1, %g1 1798 st %g1, [%g4 + CPU_TL1_HDLR] ! set CPU_TL1_HDLR 1799 rdpr %tpc, %g1 ! ld trapping instruction using 1800 lduwa [%g1]ASI_AIUP, %g1 ! "AS IF USER" ASI which could fault 1801 st %g0, [%g4 + CPU_TL1_HDLR] ! clr CPU_TL1_HDLR 1802 1803 sethi %hi(0xc1c00000), %g4 ! setup mask for illtrap instruction 1804 andcc %g1, %g4, %g4 ! and instruction with mask 1805 bnz,a,pt %icc, 3f ! if %g4 == zero, %g1 is an ILLTRAP 1806 nop ! fall thru to setup 18072: 1808 ldn [%g5 + %g2], %g5 1809 brnz,a,pt %g5, .setup_v9utrap 1810 nop 18113: 1812 set trap, %g1 1813 ba,pt %xcc, sys_trap 1814 sub %g0, 1, %g4 1815 /* NOTREACHED */ 1816 1817/* 1818 * Register Inputs: 1819 * %g5 user trap handler 1820 */ 1821.setup_v9utrap: 1822 set trap, %g1 ! setup in case we go 1823 mov T_FLUSH_PCB, %g3 ! through sys_trap on 1824 sub %g0, 1, %g4 ! the save instruction below 1825 1826 /* 1827 * If the DTrace pid provider is single stepping a copied-out 1828 * instruction, t->t_dtrace_step will be set. In that case we need 1829 * to abort the single-stepping (since execution of the instruction 1830 * was interrupted) and use the value of t->t_dtrace_npc as the %npc. 1831 */ 1832 save %sp, -SA(MINFRAME64), %sp ! window for trap handler 1833 CPU_ADDR(%g1, %g4) ! load CPU struct addr 1834 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer 1835 ldub [%g1 + T_DTRACE_STEP], %g2 ! load t->t_dtrace_step 1836 rdpr %tnpc, %l7 ! arg1 == tnpc 1837 brz,pt %g2, 1f 1838 rdpr %tpc, %l6 ! arg0 == tpc 1839 1840 ldub [%g1 + T_DTRACE_AST], %g2 ! load t->t_dtrace_ast 1841 ldn [%g1 + T_DTRACE_NPC], %l7 ! arg1 == t->t_dtrace_npc (step) 1842 brz,pt %g2, 1f 1843 st %g0, [%g1 + T_DTRACE_FT] ! zero all pid provider flags 1844 stub %g2, [%g1 + T_ASTFLAG] ! aston(t) if t->t_dtrace_ast 18451: 1846 rdpr %tstate, %g2 ! cwp for trap handler 1847 rdpr %cwp, %g4 1848 bclr TSTATE_CWP_MASK, %g2 1849 wrpr %g2, %g4, %tstate 1850 1851 ldn [%g1 + T_PROCP], %g4 ! load proc pointer 1852 ldn [%g4 + P_AS], %g4 ! load as pointer 1853 ldn [%g4 + A_USERLIMIT], %g4 ! load as userlimit 1854 cmp %l7, %g4 ! check for single-step set 1855 bne,pt %xcc, 4f 1856 nop 1857 ldn [%g1 + T_LWP], %g1 ! load klwp pointer 1858 ld [%g1 + PCB_STEP], %g4 ! load single-step flag 1859 cmp %g4, STEP_ACTIVE ! step flags set in pcb? 1860 bne,pt %icc, 4f 1861 nop 1862 stn %g5, [%g1 + PCB_TRACEPC] ! save trap handler addr in pcb 1863 mov %l7, %g4 ! on entry to precise user trap 1864 add %l6, 4, %l7 ! handler, %l6 == pc, %l7 == npc 1865 ! at time of trap 1866 wrpr %g0, %g4, %tnpc ! generate FLTBOUNDS, 1867 ! %g4 == userlimit 1868 FAST_TRAP_DONE 1869 /* NOTREACHED */ 18704: 1871 wrpr %g0, %g5, %tnpc ! trap handler address 1872 FAST_TRAP_DONE_CHK_INTR 1873 /* NOTREACHED */ 1874 1875.fp_exception: 1876 CPU_ADDR(%g1, %g4) 1877 stx %fsr, [%g1 + CPU_TMP1] 1878 ldx [%g1 + CPU_TMP1], %g2 1879 1880 /* 1881 * Cheetah takes unfinished_FPop trap for certain range of operands 1882 * to the "fitos" instruction. Instead of going through the slow 1883 * software emulation path, we try to simulate the "fitos" instruction 1884 * via "fitod" and "fdtos" provided the following conditions are met: 1885 * 1886 * fpu_exists is set (if DEBUG) 1887 * not in privileged mode 1888 * ftt is unfinished_FPop 1889 * NXM IEEE trap is not enabled 1890 * instruction at %tpc is "fitos" 1891 * 1892 * Usage: 1893 * %g1 per cpu address 1894 * %g2 %fsr 1895 * %g6 user instruction 1896 * 1897 * Note that we can take a memory access related trap while trying 1898 * to fetch the user instruction. Therefore, we set CPU_TL1_HDLR 1899 * flag to catch those traps and let the SFMMU code deal with page 1900 * fault and data access exception. 1901 */ 1902#if defined(DEBUG) || defined(NEED_FPU_EXISTS) 1903 sethi %hi(fpu_exists), %g7 1904 ld [%g7 + %lo(fpu_exists)], %g7 1905 brz,pn %g7, .fp_exception_cont 1906 nop 1907#endif 1908 rdpr %tstate, %g7 ! branch if in privileged mode 1909 btst TSTATE_PRIV, %g7 1910 bnz,pn %xcc, .fp_exception_cont 1911 srl %g2, FSR_FTT_SHIFT, %g7 ! extract ftt from %fsr 1912 and %g7, (FSR_FTT>>FSR_FTT_SHIFT), %g7 1913 cmp %g7, FTT_UNFIN 1914 set FSR_TEM_NX, %g5 1915 bne,pn %xcc, .fp_exception_cont ! branch if NOT unfinished_FPop 1916 andcc %g2, %g5, %g0 1917 bne,pn %xcc, .fp_exception_cont ! branch if FSR_TEM_NX enabled 1918 rdpr %tpc, %g5 ! get faulting PC 1919 1920 or %g0, 1, %g7 1921 st %g7, [%g1 + CPU_TL1_HDLR] ! set tl1_hdlr flag 1922 lda [%g5]ASI_USER, %g6 ! get user's instruction 1923 st %g0, [%g1 + CPU_TL1_HDLR] ! clear tl1_hdlr flag 1924 1925 set FITOS_INSTR_MASK, %g7 1926 and %g6, %g7, %g7 1927 set FITOS_INSTR, %g5 1928 cmp %g7, %g5 1929 bne,pn %xcc, .fp_exception_cont ! branch if not FITOS_INSTR 1930 nop 1931 1932 /* 1933 * This is unfinished FPops trap for "fitos" instruction. We 1934 * need to simulate "fitos" via "fitod" and "fdtos" instruction 1935 * sequence. 1936 * 1937 * We need a temporary FP register to do the conversion. Since 1938 * both source and destination operands for the "fitos" instruction 1939 * have to be within %f0-%f31, we use an FP register from the upper 1940 * half to guarantee that it won't collide with the source or the 1941 * dest operand. However, we do have to save and restore its value. 1942 * 1943 * We use %d62 as a temporary FP register for the conversion and 1944 * branch to appropriate instruction within the conversion tables 1945 * based upon the rs2 and rd values. 1946 */ 1947 1948 std %d62, [%g1 + CPU_TMP1] ! save original value 1949 1950 srl %g6, FITOS_RS2_SHIFT, %g7 1951 and %g7, FITOS_REG_MASK, %g7 1952 set _fitos_fitod_table, %g4 1953 sllx %g7, 2, %g7 1954 jmp %g4 + %g7 1955 ba,pt %xcc, _fitos_fitod_done 1956 .empty 1957 1958_fitos_fitod_table: 1959 fitod %f0, %d62 1960 fitod %f1, %d62 1961 fitod %f2, %d62 1962 fitod %f3, %d62 1963 fitod %f4, %d62 1964 fitod %f5, %d62 1965 fitod %f6, %d62 1966 fitod %f7, %d62 1967 fitod %f8, %d62 1968 fitod %f9, %d62 1969 fitod %f10, %d62 1970 fitod %f11, %d62 1971 fitod %f12, %d62 1972 fitod %f13, %d62 1973 fitod %f14, %d62 1974 fitod %f15, %d62 1975 fitod %f16, %d62 1976 fitod %f17, %d62 1977 fitod %f18, %d62 1978 fitod %f19, %d62 1979 fitod %f20, %d62 1980 fitod %f21, %d62 1981 fitod %f22, %d62 1982 fitod %f23, %d62 1983 fitod %f24, %d62 1984 fitod %f25, %d62 1985 fitod %f26, %d62 1986 fitod %f27, %d62 1987 fitod %f28, %d62 1988 fitod %f29, %d62 1989 fitod %f30, %d62 1990 fitod %f31, %d62 1991_fitos_fitod_done: 1992 1993 /* 1994 * Now convert data back into single precision 1995 */ 1996 srl %g6, FITOS_RD_SHIFT, %g7 1997 and %g7, FITOS_REG_MASK, %g7 1998 set _fitos_fdtos_table, %g4 1999 sllx %g7, 2, %g7 2000 jmp %g4 + %g7 2001 ba,pt %xcc, _fitos_fdtos_done 2002 .empty 2003 2004_fitos_fdtos_table: 2005 fdtos %d62, %f0 2006 fdtos %d62, %f1 2007 fdtos %d62, %f2 2008 fdtos %d62, %f3 2009 fdtos %d62, %f4 2010 fdtos %d62, %f5 2011 fdtos %d62, %f6 2012 fdtos %d62, %f7 2013 fdtos %d62, %f8 2014 fdtos %d62, %f9 2015 fdtos %d62, %f10 2016 fdtos %d62, %f11 2017 fdtos %d62, %f12 2018 fdtos %d62, %f13 2019 fdtos %d62, %f14 2020 fdtos %d62, %f15 2021 fdtos %d62, %f16 2022 fdtos %d62, %f17 2023 fdtos %d62, %f18 2024 fdtos %d62, %f19 2025 fdtos %d62, %f20 2026 fdtos %d62, %f21 2027 fdtos %d62, %f22 2028 fdtos %d62, %f23 2029 fdtos %d62, %f24 2030 fdtos %d62, %f25 2031 fdtos %d62, %f26 2032 fdtos %d62, %f27 2033 fdtos %d62, %f28 2034 fdtos %d62, %f29 2035 fdtos %d62, %f30 2036 fdtos %d62, %f31 2037_fitos_fdtos_done: 2038 2039 ldd [%g1 + CPU_TMP1], %d62 ! restore %d62 2040 2041#if DEBUG 2042 /* 2043 * Update FPop_unfinished trap kstat 2044 */ 2045 set fpustat+FPUSTAT_UNFIN_KSTAT, %g7 2046 ldx [%g7], %g5 20471: 2048 add %g5, 1, %g6 2049 2050 casxa [%g7] ASI_N, %g5, %g6 2051 cmp %g5, %g6 2052 bne,a,pn %xcc, 1b 2053 or %g0, %g6, %g5 2054 2055 /* 2056 * Update fpu_sim_fitos kstat 2057 */ 2058 set fpuinfo+FPUINFO_FITOS_KSTAT, %g7 2059 ldx [%g7], %g5 20601: 2061 add %g5, 1, %g6 2062 2063 casxa [%g7] ASI_N, %g5, %g6 2064 cmp %g5, %g6 2065 bne,a,pn %xcc, 1b 2066 or %g0, %g6, %g5 2067#endif /* DEBUG */ 2068 2069 FAST_TRAP_DONE 2070 2071.fp_exception_cont: 2072 /* 2073 * Let _fp_exception deal with simulating FPop instruction. 2074 * Note that we need to pass %fsr in %g2 (already read above). 2075 */ 2076 2077 set _fp_exception, %g1 2078 ba,pt %xcc, sys_trap 2079 sub %g0, 1, %g4 2080 2081.clean_windows: 2082 set trap, %g1 2083 mov T_FLUSH_PCB, %g3 2084 sub %g0, 1, %g4 2085 save 2086 flushw 2087 restore 2088 wrpr %g0, %g0, %cleanwin ! no clean windows 2089 2090 CPU_ADDR(%g4, %g5) 2091 ldn [%g4 + CPU_MPCB], %g4 2092 brz,a,pn %g4, 1f 2093 nop 2094 ld [%g4 + MPCB_WSTATE], %g5 2095 add %g5, WSTATE_CLEAN_OFFSET, %g5 2096 wrpr %g0, %g5, %wstate 20971: FAST_TRAP_DONE 2098 2099/* 2100 * .spill_clean: clean the previous window, restore the wstate, and 2101 * "done". 2102 * 2103 * Entry: %g7 contains new wstate 2104 */ 2105.spill_clean: 2106 sethi %hi(nwin_minus_one), %g5 2107 ld [%g5 + %lo(nwin_minus_one)], %g5 ! %g5 = nwin - 1 2108 rdpr %cwp, %g6 ! %g6 = %cwp 2109 deccc %g6 ! %g6-- 2110 movneg %xcc, %g5, %g6 ! if (%g6<0) %g6 = nwin-1 2111 wrpr %g6, %cwp 2112 TT_TRACE_L(trace_win) 2113 clr %l0 2114 clr %l1 2115 clr %l2 2116 clr %l3 2117 clr %l4 2118 clr %l5 2119 clr %l6 2120 clr %l7 2121 wrpr %g0, %g7, %wstate 2122 saved 2123 retry ! restores correct %cwp 2124 2125.fix_alignment: 2126 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2 2127 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer 2128 ldn [%g1 + T_PROCP], %g1 2129 mov 1, %g2 2130 stb %g2, [%g1 + P_FIXALIGNMENT] 2131 FAST_TRAP_DONE 2132 2133#define STDF_REG(REG, ADDR, TMP) \ 2134 sll REG, 3, REG ;\ 2135mark1: set start1, TMP ;\ 2136 jmp REG + TMP ;\ 2137 nop ;\ 2138start1: ba,pt %xcc, done1 ;\ 2139 std %f0, [ADDR + CPU_TMP1] ;\ 2140 ba,pt %xcc, done1 ;\ 2141 std %f32, [ADDR + CPU_TMP1] ;\ 2142 ba,pt %xcc, done1 ;\ 2143 std %f2, [ADDR + CPU_TMP1] ;\ 2144 ba,pt %xcc, done1 ;\ 2145 std %f34, [ADDR + CPU_TMP1] ;\ 2146 ba,pt %xcc, done1 ;\ 2147 std %f4, [ADDR + CPU_TMP1] ;\ 2148 ba,pt %xcc, done1 ;\ 2149 std %f36, [ADDR + CPU_TMP1] ;\ 2150 ba,pt %xcc, done1 ;\ 2151 std %f6, [ADDR + CPU_TMP1] ;\ 2152 ba,pt %xcc, done1 ;\ 2153 std %f38, [ADDR + CPU_TMP1] ;\ 2154 ba,pt %xcc, done1 ;\ 2155 std %f8, [ADDR + CPU_TMP1] ;\ 2156 ba,pt %xcc, done1 ;\ 2157 std %f40, [ADDR + CPU_TMP1] ;\ 2158 ba,pt %xcc, done1 ;\ 2159 std %f10, [ADDR + CPU_TMP1] ;\ 2160 ba,pt %xcc, done1 ;\ 2161 std %f42, [ADDR + CPU_TMP1] ;\ 2162 ba,pt %xcc, done1 ;\ 2163 std %f12, [ADDR + CPU_TMP1] ;\ 2164 ba,pt %xcc, done1 ;\ 2165 std %f44, [ADDR + CPU_TMP1] ;\ 2166 ba,pt %xcc, done1 ;\ 2167 std %f14, [ADDR + CPU_TMP1] ;\ 2168 ba,pt %xcc, done1 ;\ 2169 std %f46, [ADDR + CPU_TMP1] ;\ 2170 ba,pt %xcc, done1 ;\ 2171 std %f16, [ADDR + CPU_TMP1] ;\ 2172 ba,pt %xcc, done1 ;\ 2173 std %f48, [ADDR + CPU_TMP1] ;\ 2174 ba,pt %xcc, done1 ;\ 2175 std %f18, [ADDR + CPU_TMP1] ;\ 2176 ba,pt %xcc, done1 ;\ 2177 std %f50, [ADDR + CPU_TMP1] ;\ 2178 ba,pt %xcc, done1 ;\ 2179 std %f20, [ADDR + CPU_TMP1] ;\ 2180 ba,pt %xcc, done1 ;\ 2181 std %f52, [ADDR + CPU_TMP1] ;\ 2182 ba,pt %xcc, done1 ;\ 2183 std %f22, [ADDR + CPU_TMP1] ;\ 2184 ba,pt %xcc, done1 ;\ 2185 std %f54, [ADDR + CPU_TMP1] ;\ 2186 ba,pt %xcc, done1 ;\ 2187 std %f24, [ADDR + CPU_TMP1] ;\ 2188 ba,pt %xcc, done1 ;\ 2189 std %f56, [ADDR + CPU_TMP1] ;\ 2190 ba,pt %xcc, done1 ;\ 2191 std %f26, [ADDR + CPU_TMP1] ;\ 2192 ba,pt %xcc, done1 ;\ 2193 std %f58, [ADDR + CPU_TMP1] ;\ 2194 ba,pt %xcc, done1 ;\ 2195 std %f28, [ADDR + CPU_TMP1] ;\ 2196 ba,pt %xcc, done1 ;\ 2197 std %f60, [ADDR + CPU_TMP1] ;\ 2198 ba,pt %xcc, done1 ;\ 2199 std %f30, [ADDR + CPU_TMP1] ;\ 2200 ba,pt %xcc, done1 ;\ 2201 std %f62, [ADDR + CPU_TMP1] ;\ 2202done1: 2203 2204#define LDDF_REG(REG, ADDR, TMP) \ 2205 sll REG, 3, REG ;\ 2206mark2: set start2, TMP ;\ 2207 jmp REG + TMP ;\ 2208 nop ;\ 2209start2: ba,pt %xcc, done2 ;\ 2210 ldd [ADDR + CPU_TMP1], %f0 ;\ 2211 ba,pt %xcc, done2 ;\ 2212 ldd [ADDR + CPU_TMP1], %f32 ;\ 2213 ba,pt %xcc, done2 ;\ 2214 ldd [ADDR + CPU_TMP1], %f2 ;\ 2215 ba,pt %xcc, done2 ;\ 2216 ldd [ADDR + CPU_TMP1], %f34 ;\ 2217 ba,pt %xcc, done2 ;\ 2218 ldd [ADDR + CPU_TMP1], %f4 ;\ 2219 ba,pt %xcc, done2 ;\ 2220 ldd [ADDR + CPU_TMP1], %f36 ;\ 2221 ba,pt %xcc, done2 ;\ 2222 ldd [ADDR + CPU_TMP1], %f6 ;\ 2223 ba,pt %xcc, done2 ;\ 2224 ldd [ADDR + CPU_TMP1], %f38 ;\ 2225 ba,pt %xcc, done2 ;\ 2226 ldd [ADDR + CPU_TMP1], %f8 ;\ 2227 ba,pt %xcc, done2 ;\ 2228 ldd [ADDR + CPU_TMP1], %f40 ;\ 2229 ba,pt %xcc, done2 ;\ 2230 ldd [ADDR + CPU_TMP1], %f10 ;\ 2231 ba,pt %xcc, done2 ;\ 2232 ldd [ADDR + CPU_TMP1], %f42 ;\ 2233 ba,pt %xcc, done2 ;\ 2234 ldd [ADDR + CPU_TMP1], %f12 ;\ 2235 ba,pt %xcc, done2 ;\ 2236 ldd [ADDR + CPU_TMP1], %f44 ;\ 2237 ba,pt %xcc, done2 ;\ 2238 ldd [ADDR + CPU_TMP1], %f14 ;\ 2239 ba,pt %xcc, done2 ;\ 2240 ldd [ADDR + CPU_TMP1], %f46 ;\ 2241 ba,pt %xcc, done2 ;\ 2242 ldd [ADDR + CPU_TMP1], %f16 ;\ 2243 ba,pt %xcc, done2 ;\ 2244 ldd [ADDR + CPU_TMP1], %f48 ;\ 2245 ba,pt %xcc, done2 ;\ 2246 ldd [ADDR + CPU_TMP1], %f18 ;\ 2247 ba,pt %xcc, done2 ;\ 2248 ldd [ADDR + CPU_TMP1], %f50 ;\ 2249 ba,pt %xcc, done2 ;\ 2250 ldd [ADDR + CPU_TMP1], %f20 ;\ 2251 ba,pt %xcc, done2 ;\ 2252 ldd [ADDR + CPU_TMP1], %f52 ;\ 2253 ba,pt %xcc, done2 ;\ 2254 ldd [ADDR + CPU_TMP1], %f22 ;\ 2255 ba,pt %xcc, done2 ;\ 2256 ldd [ADDR + CPU_TMP1], %f54 ;\ 2257 ba,pt %xcc, done2 ;\ 2258 ldd [ADDR + CPU_TMP1], %f24 ;\ 2259 ba,pt %xcc, done2 ;\ 2260 ldd [ADDR + CPU_TMP1], %f56 ;\ 2261 ba,pt %xcc, done2 ;\ 2262 ldd [ADDR + CPU_TMP1], %f26 ;\ 2263 ba,pt %xcc, done2 ;\ 2264 ldd [ADDR + CPU_TMP1], %f58 ;\ 2265 ba,pt %xcc, done2 ;\ 2266 ldd [ADDR + CPU_TMP1], %f28 ;\ 2267 ba,pt %xcc, done2 ;\ 2268 ldd [ADDR + CPU_TMP1], %f60 ;\ 2269 ba,pt %xcc, done2 ;\ 2270 ldd [ADDR + CPU_TMP1], %f30 ;\ 2271 ba,pt %xcc, done2 ;\ 2272 ldd [ADDR + CPU_TMP1], %f62 ;\ 2273done2: 2274 2275.lddf_exception_not_aligned: 2276 /* 2277 * Cheetah overwrites SFAR on a DTLB miss, hence read it now. 2278 */ 2279 ldxa [MMU_SFAR]%asi, %g5 ! misaligned vaddr in %g5 2280 2281#if defined(DEBUG) || defined(NEED_FPU_EXISTS) 2282 sethi %hi(fpu_exists), %g2 ! check fpu_exists 2283 ld [%g2 + %lo(fpu_exists)], %g2 2284 brz,a,pn %g2, 4f 2285 nop 2286#endif 2287 CPU_ADDR(%g1, %g4) 2288 or %g0, 1, %g4 2289 st %g4, [%g1 + CPU_TL1_HDLR] ! set tl1_hdlr flag 2290 2291 rdpr %tpc, %g2 2292 lda [%g2]ASI_AIUP, %g6 ! get the user's lddf instruction 2293 srl %g6, 23, %g1 ! using ldda or not? 2294 and %g1, 1, %g1 2295 brz,a,pt %g1, 2f ! check for ldda instruction 2296 nop 2297 srl %g6, 13, %g1 ! check immflag 2298 and %g1, 1, %g1 2299 rdpr %tstate, %g2 ! %tstate in %g2 2300 brnz,a,pn %g1, 1f 2301 srl %g2, 31, %g1 ! get asi from %tstate 2302 srl %g6, 5, %g1 ! get asi from instruction 2303 and %g1, 0xFF, %g1 ! imm_asi field 23041: 2305 cmp %g1, ASI_P ! primary address space 2306 be,a,pt %icc, 2f 2307 nop 2308 cmp %g1, ASI_PNF ! primary no fault address space 2309 be,a,pt %icc, 2f 2310 nop 2311 cmp %g1, ASI_S ! secondary address space 2312 be,a,pt %icc, 2f 2313 nop 2314 cmp %g1, ASI_SNF ! secondary no fault address space 2315 bne,a,pn %icc, 3f 2316 nop 23172: 2318 lduwa [%g5]ASI_USER, %g7 ! get first half of misaligned data 2319 add %g5, 4, %g5 ! increment misaligned data address 2320 lduwa [%g5]ASI_USER, %g5 ! get second half of misaligned data 2321 2322 sllx %g7, 32, %g7 2323 or %g5, %g7, %g5 ! combine data 2324 CPU_ADDR(%g7, %g1) ! save data on a per-cpu basis 2325 stx %g5, [%g7 + CPU_TMP1] ! save in cpu_tmp1 2326 2327 srl %g6, 25, %g3 ! %g6 has the instruction 2328 and %g3, 0x1F, %g3 ! %g3 has rd 2329 LDDF_REG(%g3, %g7, %g4) 2330 2331 CPU_ADDR(%g1, %g4) 2332 st %g0, [%g1 + CPU_TL1_HDLR] ! clear tl1_hdlr flag 2333 FAST_TRAP_DONE 23343: 2335 CPU_ADDR(%g1, %g4) 2336 st %g0, [%g1 + CPU_TL1_HDLR] ! clear tl1_hdlr flag 23374: 2338 set T_USER, %g3 ! trap type in %g3 2339 or %g3, T_LDDF_ALIGN, %g3 2340 mov %g5, %g2 ! misaligned vaddr in %g2 2341 set fpu_trap, %g1 ! goto C for the little and 2342 ba,pt %xcc, sys_trap ! no fault little asi's 2343 sub %g0, 1, %g4 2344 2345.stdf_exception_not_aligned: 2346 /* 2347 * Cheetah overwrites SFAR on a DTLB miss, hence read it now. 2348 */ 2349 ldxa [MMU_SFAR]%asi, %g5 ! misaligned vaddr in %g5 2350 2351#if defined(DEBUG) || defined(NEED_FPU_EXISTS) 2352 sethi %hi(fpu_exists), %g7 ! check fpu_exists 2353 ld [%g7 + %lo(fpu_exists)], %g3 2354 brz,a,pn %g3, 4f 2355 nop 2356#endif 2357 CPU_ADDR(%g1, %g4) 2358 or %g0, 1, %g4 2359 st %g4, [%g1 + CPU_TL1_HDLR] ! set tl1_hdlr flag 2360 2361 rdpr %tpc, %g2 2362 lda [%g2]ASI_AIUP, %g6 ! get the user's stdf instruction 2363 2364 srl %g6, 23, %g1 ! using stda or not? 2365 and %g1, 1, %g1 2366 brz,a,pt %g1, 2f ! check for stda instruction 2367 nop 2368 srl %g6, 13, %g1 ! check immflag 2369 and %g1, 1, %g1 2370 rdpr %tstate, %g2 ! %tstate in %g2 2371 brnz,a,pn %g1, 1f 2372 srl %g2, 31, %g1 ! get asi from %tstate 2373 srl %g6, 5, %g1 ! get asi from instruction 2374 and %g1, 0xFF, %g1 ! imm_asi field 23751: 2376 cmp %g1, ASI_P ! primary address space 2377 be,a,pt %icc, 2f 2378 nop 2379 cmp %g1, ASI_S ! secondary address space 2380 bne,a,pn %icc, 3f 2381 nop 23822: 2383 srl %g6, 25, %g6 2384 and %g6, 0x1F, %g6 ! %g6 has rd 2385 CPU_ADDR(%g7, %g1) 2386 STDF_REG(%g6, %g7, %g4) ! STDF_REG(REG, ADDR, TMP) 2387 2388 ldx [%g7 + CPU_TMP1], %g6 2389 srlx %g6, 32, %g7 2390 stuwa %g7, [%g5]ASI_USER ! first half 2391 add %g5, 4, %g5 ! increment misaligned data address 2392 stuwa %g6, [%g5]ASI_USER ! second half 2393 2394 CPU_ADDR(%g1, %g4) 2395 st %g0, [%g1 + CPU_TL1_HDLR] ! clear tl1_hdlr flag 2396 FAST_TRAP_DONE 23973: 2398 CPU_ADDR(%g1, %g4) 2399 st %g0, [%g1 + CPU_TL1_HDLR] ! clear tl1_hdlr flag 24004: 2401 set T_USER, %g3 ! trap type in %g3 2402 or %g3, T_STDF_ALIGN, %g3 2403 mov %g5, %g2 ! misaligned vaddr in %g2 2404 set fpu_trap, %g1 ! goto C for the little and 2405 ba,pt %xcc, sys_trap ! nofault little asi's 2406 sub %g0, 1, %g4 2407 2408#ifdef DEBUG_USER_TRAPTRACECTL 2409 2410.traptrace_freeze: 2411 mov %l0, %g1 ; mov %l1, %g2 ; mov %l2, %g3 ; mov %l4, %g4 2412 TT_TRACE_L(trace_win) 2413 mov %g4, %l4 ; mov %g3, %l2 ; mov %g2, %l1 ; mov %g1, %l0 2414 set trap_freeze, %g1 2415 mov 1, %g2 2416 st %g2, [%g1] 2417 FAST_TRAP_DONE 2418 2419.traptrace_unfreeze: 2420 set trap_freeze, %g1 2421 st %g0, [%g1] 2422 mov %l0, %g1 ; mov %l1, %g2 ; mov %l2, %g3 ; mov %l4, %g4 2423 TT_TRACE_L(trace_win) 2424 mov %g4, %l4 ; mov %g3, %l2 ; mov %g2, %l1 ; mov %g1, %l0 2425 FAST_TRAP_DONE 2426 2427#endif /* DEBUG_USER_TRAPTRACECTL */ 2428 2429.getcc: 2430 CPU_ADDR(%g1, %g2) 2431 stx %o0, [%g1 + CPU_TMP1] ! save %o0 2432 stx %o1, [%g1 + CPU_TMP2] ! save %o1 2433 rdpr %tstate, %g3 ! get tstate 2434 srlx %g3, PSR_TSTATE_CC_SHIFT, %o0 ! shift ccr to V8 psr 2435 set PSR_ICC, %g2 2436 and %o0, %g2, %o0 ! mask out the rest 2437 srl %o0, PSR_ICC_SHIFT, %o0 ! right justify 2438 rdpr %pstate, %o1 2439 wrpr %o1, PSTATE_AG, %pstate ! get into normal globals 2440 mov %o0, %g1 ! move ccr to normal %g1 2441 wrpr %g0, %o1, %pstate ! back into alternate globals 2442 ldx [%g1 + CPU_TMP1], %o0 ! restore %o0 2443 ldx [%g1 + CPU_TMP2], %o1 ! restore %o1 2444 FAST_TRAP_DONE 2445 2446.setcc: 2447 CPU_ADDR(%g1, %g2) 2448 stx %o0, [%g1 + CPU_TMP1] ! save %o0 2449 stx %o1, [%g1 + CPU_TMP2] ! save %o1 2450 rdpr %pstate, %o0 2451 wrpr %o0, PSTATE_AG, %pstate ! get into normal globals 2452 mov %g1, %o1 2453 wrpr %g0, %o0, %pstate ! back to alternates 2454 sll %o1, PSR_ICC_SHIFT, %g2 2455 set PSR_ICC, %g3 2456 and %g2, %g3, %g2 ! mask out rest 2457 sllx %g2, PSR_TSTATE_CC_SHIFT, %g2 2458 rdpr %tstate, %g3 ! get tstate 2459 srl %g3, 0, %g3 ! clear upper word 2460 or %g3, %g2, %g3 ! or in new bits 2461 wrpr %g3, %tstate 2462 ldx [%g1 + CPU_TMP1], %o0 ! restore %o0 2463 ldx [%g1 + CPU_TMP2], %o1 ! restore %o1 2464 FAST_TRAP_DONE 2465 2466/* 2467 * getpsr(void) 2468 * Note that the xcc part of the ccr is not provided. 2469 * The V8 code shows why the V9 trap is not faster: 2470 * #define GETPSR_TRAP() \ 2471 * mov %psr, %i0; jmp %l2; rett %l2+4; nop; 2472 */ 2473 2474 .type .getpsr, #function 2475.getpsr: 2476 rdpr %tstate, %g1 ! get tstate 2477 srlx %g1, PSR_TSTATE_CC_SHIFT, %o0 ! shift ccr to V8 psr 2478 set PSR_ICC, %g2 2479 and %o0, %g2, %o0 ! mask out the rest 2480 2481 rd %fprs, %g1 ! get fprs 2482 and %g1, FPRS_FEF, %g2 ! mask out dirty upper/lower 2483 sllx %g2, PSR_FPRS_FEF_SHIFT, %g2 ! shift fef to V8 psr.ef 2484 or %o0, %g2, %o0 ! or result into psr.ef 2485 2486 set V9_PSR_IMPLVER, %g2 ! SI assigned impl/ver: 0xef 2487 or %o0, %g2, %o0 ! or psr.impl/ver 2488 FAST_TRAP_DONE 2489 SET_SIZE(.getpsr) 2490 2491/* 2492 * setpsr(newpsr) 2493 * Note that there is no support for ccr.xcc in the V9 code. 2494 */ 2495 2496 .type .setpsr, #function 2497.setpsr: 2498 rdpr %tstate, %g1 ! get tstate 2499! setx TSTATE_V8_UBITS, %g2 2500 or %g0, CCR_ICC, %g3 2501 sllx %g3, TSTATE_CCR_SHIFT, %g2 2502 2503 andn %g1, %g2, %g1 ! zero current user bits 2504 set PSR_ICC, %g2 2505 and %g2, %o0, %g2 ! clear all but psr.icc bits 2506 sllx %g2, PSR_TSTATE_CC_SHIFT, %g3 ! shift to tstate.ccr.icc 2507 wrpr %g1, %g3, %tstate ! write tstate 2508 2509 set PSR_EF, %g2 2510 and %g2, %o0, %g2 ! clear all but fp enable bit 2511 srlx %g2, PSR_FPRS_FEF_SHIFT, %g4 ! shift ef to V9 fprs.fef 2512 wr %g0, %g4, %fprs ! write fprs 2513 2514 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 2515 ldn [%g1 + CPU_THREAD], %g2 ! load thread pointer 2516 ldn [%g2 + T_LWP], %g3 ! load klwp pointer 2517 ldn [%g3 + LWP_FPU], %g2 ! get lwp_fpu pointer 2518 stuw %g4, [%g2 + FPU_FPRS] ! write fef value to fpu_fprs 2519 srlx %g4, 2, %g4 ! shift fef value to bit 0 2520 stub %g4, [%g2 + FPU_EN] ! write fef value to fpu_en 2521 FAST_TRAP_DONE 2522 SET_SIZE(.setpsr) 2523 2524/* 2525 * getlgrp 2526 * get home lgrpid on which the calling thread is currently executing. 2527 */ 2528 .type .getlgrp, #function 2529.getlgrp: 2530 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2 2531 ld [%g1 + CPU_ID], %o0 ! load cpu_id 2532 ldn [%g1 + CPU_THREAD], %g2 ! load thread pointer 2533 ldn [%g2 + T_LPL], %g2 ! load lpl pointer 2534 ld [%g2 + LPL_LGRPID], %g1 ! load lpl_lgrpid 2535 sra %g1, 0, %o1 2536 FAST_TRAP_DONE 2537 SET_SIZE(.getlgrp) 2538 2539/* 2540 * Entry for old 4.x trap (trap 0). 2541 */ 2542 ENTRY_NP(syscall_trap_4x) 2543 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2 2544 ldn [%g1 + CPU_THREAD], %g2 ! load thread pointer 2545 ldn [%g2 + T_LWP], %g2 ! load klwp pointer 2546 ld [%g2 + PCB_TRAP0], %g2 ! lwp->lwp_pcb.pcb_trap0addr 2547 brz,pn %g2, 1f ! has it been set? 2548 st %l0, [%g1 + CPU_TMP1] ! delay - save some locals 2549 st %l1, [%g1 + CPU_TMP2] 2550 rdpr %tnpc, %l1 ! save old tnpc 2551 wrpr %g0, %g2, %tnpc ! setup tnpc 2552 2553 rdpr %pstate, %l0 2554 wrpr %l0, PSTATE_AG, %pstate ! switch to normal globals 2555 mov %l1, %g6 ! pass tnpc to user code in %g6 2556 wrpr %l0, %g0, %pstate ! switch back to alternate globals 2557 2558 ! Note that %g1 still contains CPU struct addr 2559 ld [%g1 + CPU_TMP2], %l1 ! restore locals 2560 ld [%g1 + CPU_TMP1], %l0 2561 FAST_TRAP_DONE_CHK_INTR 25621: 2563 mov %g1, %l0 2564 st %l1, [%g1 + CPU_TMP2] 2565 rdpr %pstate, %l1 2566 wrpr %l1, PSTATE_AG, %pstate 2567 ! 2568 ! check for old syscall mmap which is the only different one which 2569 ! must be the same. Others are handled in the compatibility library. 2570 ! 2571 cmp %g1, OSYS_mmap ! compare to old 4.x mmap 2572 movz %icc, SYS_mmap, %g1 2573 wrpr %g0, %l1, %pstate 2574 ld [%l0 + CPU_TMP2], %l1 ! restore locals 2575 ld [%l0 + CPU_TMP1], %l0 2576 SYSCALL(syscall_trap32) 2577 SET_SIZE(syscall_trap_4x) 2578 2579/* 2580 * Handler for software trap 9. 2581 * Set trap0 emulation address for old 4.x system call trap. 2582 * XXX - this should be a system call. 2583 */ 2584 ENTRY_NP(set_trap0_addr) 2585 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2 2586 ldn [%g1 + CPU_THREAD], %g2 ! load thread pointer 2587 ldn [%g2 + T_LWP], %g2 ! load klwp pointer 2588 st %l0, [%g1 + CPU_TMP1] ! save some locals 2589 st %l1, [%g1 + CPU_TMP2] 2590 rdpr %pstate, %l0 2591 wrpr %l0, PSTATE_AG, %pstate 2592 mov %g1, %l1 2593 wrpr %g0, %l0, %pstate 2594 andn %l1, 3, %l1 ! force alignment 2595 st %l1, [%g2 + PCB_TRAP0] ! lwp->lwp_pcb.pcb_trap0addr 2596 ld [%g1 + CPU_TMP1], %l0 ! restore locals 2597 ld [%g1 + CPU_TMP2], %l1 2598 FAST_TRAP_DONE 2599 SET_SIZE(set_trap0_addr) 2600 2601/* 2602 * mmu_trap_tl1 2603 * trap handler for unexpected mmu traps. 2604 * simply checks if the trap was a user lddf/stdf alignment trap, in which 2605 * case we go to fpu_trap or a user trap from the window handler, in which 2606 * case we go save the state on the pcb. Otherwise, we go to ptl1_panic. 2607 */ 2608 .type mmu_trap_tl1, #function 2609mmu_trap_tl1: 2610#ifdef TRAPTRACE 2611 TRACE_PTR(%g5, %g6) 2612 GET_TRACE_TICK(%g6) 2613 stxa %g6, [%g5 + TRAP_ENT_TICK]%asi 2614 rdpr %tl, %g6 2615 stha %g6, [%g5 + TRAP_ENT_TL]%asi 2616 rdpr %tt, %g6 2617 stha %g6, [%g5 + TRAP_ENT_TT]%asi 2618 rdpr %tstate, %g6 2619 stxa %g6, [%g5 + TRAP_ENT_TSTATE]%asi 2620 stna %sp, [%g5 + TRAP_ENT_SP]%asi 2621 stna %g0, [%g5 + TRAP_ENT_TR]%asi 2622 rdpr %tpc, %g6 2623 stna %g6, [%g5 + TRAP_ENT_TPC]%asi 2624 set MMU_SFAR, %g6 2625 ldxa [%g6]ASI_DMMU, %g6 2626 stxa %g6, [%g5 + TRAP_ENT_F1]%asi 2627 CPU_PADDR(%g7, %g6); 2628 add %g7, CPU_TL1_HDLR, %g7 2629 lda [%g7]ASI_MEM, %g6 2630 stxa %g6, [%g5 + TRAP_ENT_F2]%asi 2631 set 0xdeadbeef, %g6 2632 stna %g6, [%g5 + TRAP_ENT_F3]%asi 2633 stna %g6, [%g5 + TRAP_ENT_F4]%asi 2634 TRACE_NEXT(%g5, %g6, %g7) 2635#endif /* TRAPTRACE */ 2636 2637 GET_CPU_IMPL(%g5) 2638 cmp %g5, PANTHER_IMPL 2639 bne mmu_trap_tl1_4 2640 nop 2641 rdpr %tt, %g5 2642 cmp %g5, T_DATA_EXCEPTION 2643 bne mmu_trap_tl1_4 2644 nop 2645 wr %g0, ASI_DMMU, %asi 2646 ldxa [MMU_SFSR]%asi, %g5 2647 mov 1, %g6 2648 sllx %g6, PN_SFSR_PARITY_SHIFT, %g6 2649 andcc %g5, %g6, %g0 2650 bz mmu_trap_tl1_4 2651 2652 /* 2653 * We are running on a Panther and have hit a DTLB parity error. 2654 */ 2655 ldxa [MMU_TAG_ACCESS]%asi, %g2 2656 mov %g5, %g3 2657 ba,pt %xcc, .mmu_exception_is_tlb_parity 2658 mov T_DATA_EXCEPTION, %g1 2659 2660mmu_trap_tl1_4: 2661 CPU_PADDR(%g7, %g6); 2662 add %g7, CPU_TL1_HDLR, %g7 ! %g7 = &cpu_m.tl1_hdlr (PA) 2663 /* 2664 * AM is cleared on trap, so addresses are 64 bit 2665 */ 2666 lda [%g7]ASI_MEM, %g6 2667 brz,a,pt %g6, 1f 2668 nop 2669 /* 2670 * We are going to update cpu_m.tl1_hdlr using physical address. 2671 * Flush the D$ line, so that stale data won't be accessed later. 2672 */ 2673 CPU_ADDR(%g6, %g5) 2674 add %g6, CPU_TL1_HDLR, %g6 ! %g6 = &cpu_m.tl1_hdlr (VA) 2675 GET_CPU_IMPL(%g5) 2676 cmp %g5, CHEETAH_IMPL 2677 bl,pt %icc, 3f 2678 cmp %g5, SPITFIRE_IMPL 2679 stxa %g0, [%g7]ASI_DC_INVAL 2680 membar #Sync 2681 ba,pt %xcc, 2f 2682 nop 26833: 2684 bl,pt %icc, 2f 2685 sethi %hi(dcache_line_mask), %g5 2686 ld [%g5 + %lo(dcache_line_mask)], %g5 2687 and %g6, %g5, %g5 2688 stxa %g0, [%g5]ASI_DC_TAG 2689 membar #Sync 26902: 2691 sta %g0, [%g7]ASI_MEM 2692 SWITCH_GLOBALS ! back to mmu globals 2693 ba,a,pt %xcc, sfmmu_mmu_trap ! handle page faults 26941: 2695 rdpr %tt, %g5 2696 rdpr %tl, %g7 2697 sub %g7, 1, %g6 2698 wrpr %g6, %tl 2699 rdpr %tt, %g6 2700 wrpr %g7, %tl 2701 and %g6, WTRAP_TTMASK, %g6 2702 cmp %g6, WTRAP_TYPE 2703 bne,a,pn %xcc, ptl1_panic 2704 mov PTL1_BAD_MMUTRAP, %g1 2705 rdpr %tpc, %g7 2706 /* tpc should be in the trap table */ 2707 set trap_table, %g6 2708 cmp %g7, %g6 2709 blt,a,pn %xcc, ptl1_panic 2710 mov PTL1_BAD_MMUTRAP, %g1 2711 set etrap_table, %g6 2712 cmp %g7, %g6 2713 bge,a,pn %xcc, ptl1_panic 2714 mov PTL1_BAD_MMUTRAP, %g1 2715 cmp %g5, T_ALIGNMENT 2716 move %icc, MMU_SFAR, %g6 2717 movne %icc, MMU_TAG_ACCESS, %g6 2718 ldxa [%g6]ASI_DMMU, %g6 2719 andn %g7, WTRAP_ALIGN, %g7 /* 128 byte aligned */ 2720 add %g7, WTRAP_FAULTOFF, %g7 2721 wrpr %g0, %g7, %tnpc 2722 done 2723 SET_SIZE(mmu_trap_tl1) 2724 2725/* 2726 * Several traps use kmdb_trap and kmdb_trap_tl1 as their handlers. These 2727 * traps are valid only when kmdb is loaded. When the debugger is active, 2728 * the code below is rewritten to transfer control to the appropriate 2729 * debugger entry points. 2730 */ 2731 .global kmdb_trap 2732 .align 8 2733kmdb_trap: 2734 ba,a trap_table0 2735 jmp %g1 + 0 2736 nop 2737 2738 .global kmdb_trap_tl1 2739 .align 8 2740kmdb_trap_tl1: 2741 ba,a trap_table0 2742 jmp %g1 + 0 2743 nop 2744 2745/* 2746 * This entry is copied from OBP's trap table during boot. 2747 */ 2748 .global obp_bpt 2749 .align 8 2750obp_bpt: 2751 NOT 2752 2753/* 2754 * if kernel, set PCONTEXT to 0 for debuggers 2755 * if user, clear nucleus page sizes 2756 */ 2757 .global kctx_obp_bpt 2758kctx_obp_bpt: 2759 set obp_bpt, %g2 27601: 2761 mov MMU_PCONTEXT, %g1 2762 ldxa [%g1]ASI_DMMU, %g1 2763 srlx %g1, CTXREG_NEXT_SHIFT, %g3 2764 brz,pt %g3, 3f ! nucleus pgsz is 0, no problem 2765 sllx %g3, CTXREG_NEXT_SHIFT, %g3 2766 set CTXREG_CTX_MASK, %g4 ! check Pcontext 2767 btst %g4, %g1 2768 bz,a,pt %xcc, 2f 2769 clr %g3 ! kernel: PCONTEXT=0 2770 xor %g3, %g1, %g3 ! user: clr N_pgsz0/1 bits 27712: 2772 set DEMAP_ALL_TYPE, %g1 2773 stxa %g0, [%g1]ASI_DTLB_DEMAP 2774 stxa %g0, [%g1]ASI_ITLB_DEMAP 2775 mov MMU_PCONTEXT, %g1 2776 stxa %g3, [%g1]ASI_DMMU 2777 membar #Sync 2778 sethi %hi(FLUSH_ADDR), %g1 2779 flush %g1 ! flush required by immu 27803: 2781 jmp %g2 2782 nop 2783 2784 2785#ifdef TRAPTRACE 2786/* 2787 * TRAPTRACE support. 2788 * labels here are branched to with "rd %pc, %g7" in the delay slot. 2789 * Return is done by "jmp %g7 + 4". 2790 */ 2791 2792trace_gen: 2793 TRACE_PTR(%g3, %g6) 2794 GET_TRACE_TICK(%g6) 2795 stxa %g6, [%g3 + TRAP_ENT_TICK]%asi 2796 rdpr %tl, %g6 2797 stha %g6, [%g3 + TRAP_ENT_TL]%asi 2798 rdpr %tt, %g6 2799 stha %g6, [%g3 + TRAP_ENT_TT]%asi 2800 rdpr %tstate, %g6 2801 stxa %g6, [%g3 + TRAP_ENT_TSTATE]%asi 2802 stna %sp, [%g3 + TRAP_ENT_SP]%asi 2803 rdpr %tpc, %g6 2804 stna %g6, [%g3 + TRAP_ENT_TPC]%asi 2805 TRACE_NEXT(%g3, %g4, %g5) 2806 jmp %g7 + 4 2807 nop 2808 2809trace_win: 2810 TRACE_WIN_INFO(0, %l0, %l1, %l2) 2811 ! Keep the locals as clean as possible, caller cleans %l4 2812 clr %l2 2813 clr %l1 2814 jmp %l4 + 4 2815 clr %l0 2816 2817/* 2818 * Trace a tsb hit 2819 * g1 = tsbe pointer (in/clobbered) 2820 * g2 = tag access register (in) 2821 * g3 - g4 = scratch (clobbered) 2822 * g5 = tsbe data (in) 2823 * g6 = scratch (clobbered) 2824 * g7 = pc we jumped here from (in) 2825 */ 2826 2827 ! Do not disturb %g5, it will be used after the trace 2828 ALTENTRY(trace_tsbhit) 2829 TRACE_TSBHIT(0) 2830 jmp %g7 + 4 2831 nop 2832 2833/* 2834 * Trace a TSB miss 2835 * 2836 * g1 = tsb8k pointer (in) 2837 * g2 = tag access register (in) 2838 * g3 = tsb4m pointer (in) 2839 * g4 = tsbe tag (in/clobbered) 2840 * g5 - g6 = scratch (clobbered) 2841 * g7 = pc we jumped here from (in) 2842 */ 2843 .global trace_tsbmiss 2844trace_tsbmiss: 2845 membar #Sync 2846 sethi %hi(FLUSH_ADDR), %g6 2847 flush %g6 2848 TRACE_PTR(%g5, %g6) 2849 GET_TRACE_TICK(%g6) 2850 stxa %g6, [%g5 + TRAP_ENT_TICK]%asi 2851 stxa %g2, [%g5 + TRAP_ENT_SP]%asi ! tag access 2852 stxa %g4, [%g5 + TRAP_ENT_F1]%asi ! tsb tag 2853 rdpr %tnpc, %g6 2854 stxa %g6, [%g5 + TRAP_ENT_F2]%asi 2855 stna %g1, [%g5 + TRAP_ENT_F3]%asi ! tsb8k pointer 2856 srlx %g1, 32, %g6 2857 stna %g6, [%g5 + TRAP_ENT_F4]%asi ! huh? 2858 rdpr %tpc, %g6 2859 stna %g6, [%g5 + TRAP_ENT_TPC]%asi 2860 rdpr %tl, %g6 2861 stha %g6, [%g5 + TRAP_ENT_TL]%asi 2862 rdpr %tt, %g6 2863 or %g6, TT_MMU_MISS, %g4 2864 stha %g4, [%g5 + TRAP_ENT_TT]%asi 2865 cmp %g6, FAST_IMMU_MISS_TT 2866 be,a %icc, 1f 2867 ldxa [%g0]ASI_IMMU, %g6 2868 ldxa [%g0]ASI_DMMU, %g6 28691: stxa %g6, [%g5 + TRAP_ENT_TSTATE]%asi ! tag target 2870 stxa %g3, [%g5 + TRAP_ENT_TR]%asi ! tsb4m pointer 2871 TRACE_NEXT(%g5, %g4, %g6) 2872 jmp %g7 + 4 2873 nop 2874 2875/* 2876 * g2 = tag access register (in) 2877 * g3 = ctx number (in) 2878 */ 2879trace_dataprot: 2880 membar #Sync 2881 sethi %hi(FLUSH_ADDR), %g6 2882 flush %g6 2883 TRACE_PTR(%g1, %g6) 2884 GET_TRACE_TICK(%g6) 2885 stxa %g6, [%g1 + TRAP_ENT_TICK]%asi 2886 rdpr %tpc, %g6 2887 stna %g6, [%g1 + TRAP_ENT_TPC]%asi 2888 rdpr %tstate, %g6 2889 stxa %g6, [%g1 + TRAP_ENT_TSTATE]%asi 2890 stxa %g2, [%g1 + TRAP_ENT_SP]%asi ! tag access reg 2891 stxa %g0, [%g1 + TRAP_ENT_TR]%asi 2892 stxa %g0, [%g1 + TRAP_ENT_F1]%asi 2893 stxa %g0, [%g1 + TRAP_ENT_F2]%asi 2894 stxa %g0, [%g1 + TRAP_ENT_F3]%asi 2895 stxa %g0, [%g1 + TRAP_ENT_F4]%asi 2896 rdpr %tl, %g6 2897 stha %g6, [%g1 + TRAP_ENT_TL]%asi 2898 rdpr %tt, %g6 2899 stha %g6, [%g1 + TRAP_ENT_TT]%asi 2900 TRACE_NEXT(%g1, %g4, %g5) 2901 jmp %g7 + 4 2902 nop 2903 2904#endif /* TRAPTRACE */ 2905 2906/* 2907 * expects offset into tsbmiss area in %g1 and return pc in %g7 2908 */ 2909stat_mmu: 2910 CPU_INDEX(%g5, %g6) 2911 sethi %hi(tsbmiss_area), %g6 2912 sllx %g5, TSBMISS_SHIFT, %g5 2913 or %g6, %lo(tsbmiss_area), %g6 2914 add %g6, %g5, %g6 /* g6 = tsbmiss area */ 2915 ld [%g6 + %g1], %g5 2916 add %g5, 1, %g5 2917 jmp %g7 + 4 2918 st %g5, [%g6 + %g1] 2919 2920 2921/* 2922 * fast_trap_done, fast_trap_done_chk_intr: 2923 * 2924 * Due to the design of UltraSPARC pipeline, pending interrupts are not 2925 * taken immediately after a RETRY or DONE instruction which causes IE to 2926 * go from 0 to 1. Instead, the instruction at %tpc or %tnpc is allowed 2927 * to execute first before taking any interrupts. If that instruction 2928 * results in other traps, and if the corresponding trap handler runs 2929 * entirely at TL=1 with interrupts disabled, then pending interrupts 2930 * won't be taken until after yet another instruction following the %tpc 2931 * or %tnpc. 2932 * 2933 * A malicious user program can use this feature to block out interrupts 2934 * for extended durations, which can result in send_mondo_timeout kernel 2935 * panic. 2936 * 2937 * This problem is addressed by servicing any pending interrupts via 2938 * sys_trap before returning back to the user mode from a fast trap 2939 * handler. The "done" instruction within a fast trap handler, which 2940 * runs entirely at TL=1 with interrupts disabled, is replaced with the 2941 * FAST_TRAP_DONE macro, which branches control to this fast_trap_done 2942 * entry point. 2943 * 2944 * We check for any pending interrupts here and force a sys_trap to 2945 * service those interrupts, if any. To minimize overhead, pending 2946 * interrupts are checked if the %tpc happens to be at 16K boundary, 2947 * which allows a malicious program to execute at most 4K consecutive 2948 * instructions before we service any pending interrupts. If a worst 2949 * case fast trap handler takes about 2 usec, then interrupts will be 2950 * blocked for at most 8 msec, less than a clock tick. 2951 * 2952 * For the cases where we don't know if the %tpc will cross a 16K 2953 * boundary, we can't use the above optimization and always process 2954 * any pending interrupts via fast_frap_done_chk_intr entry point. 2955 * 2956 * Entry Conditions: 2957 * %pstate am:0 priv:1 ie:0 2958 * globals are AG (not normal globals) 2959 */ 2960 2961 .global fast_trap_done, fast_trap_done_chk_intr 2962fast_trap_done: 2963 rdpr %tpc, %g5 2964 sethi %hi(0xffffc000), %g6 ! 1's complement of 0x3fff 2965 andncc %g5, %g6, %g0 ! check lower 14 bits of %tpc 2966 bz,a,pn %icc, 1f ! branch if zero (lower 32 bits only) 2967 ldxa [%g0]ASI_INTR_RECEIVE_STATUS, %g5 2968 done 2969 2970fast_trap_done_chk_intr: 2971 ldxa [%g0]ASI_INTR_RECEIVE_STATUS, %g5 2972 29731: rd SOFTINT, %g6 2974 and %g5, IRSR_BUSY, %g5 2975 orcc %g5, %g6, %g0 2976 bnz,pn %xcc, 2f ! branch if any pending intr 2977 nop 2978 done 2979 29802: 2981 /* 2982 * We get here if there are any pending interrupts. 2983 * Adjust %tpc/%tnpc as we'll be resuming via "retry" 2984 * instruction. 2985 */ 2986 rdpr %tnpc, %g5 2987 wrpr %g0, %g5, %tpc 2988 add %g5, 4, %g5 2989 wrpr %g0, %g5, %tnpc 2990 2991 /* 2992 * Force a dummy sys_trap call so that interrupts can be serviced. 2993 */ 2994 set fast_trap_dummy_call, %g1 2995 ba,pt %xcc, sys_trap 2996 mov -1, %g4 2997 2998fast_trap_dummy_call: 2999 retl 3000 nop 3001 3002#endif /* lint */ 3003