1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_PX_LIB4U_H 28 #define _SYS_PX_LIB4U_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* 37 * Errors returned. 38 */ 39 #define H_EOK 0 /* Successful return */ 40 #define H_ENOINTR 1 /* Invalid interrupt id */ 41 #define H_EINVAL 2 /* Invalid argument */ 42 #define H_ENOACCESS 3 /* No access to resource */ 43 #define H_EIO 4 /* I/O error */ 44 #define H_ENOTSUPPORTED 5 /* Function not supported */ 45 #define H_ENOMAP 6 /* Mapping is not valid, */ 46 /* no translation exists */ 47 48 /* 49 * SUN4U px specific data structure. 50 */ 51 typedef struct pxu { 52 uint32_t chip_id; 53 uint8_t portid; 54 uint16_t tsb_cookie; 55 uint32_t tsb_size; 56 uint64_t *tsb_vaddr; 57 void *msiq_mapped_p; 58 59 /* Soft state for suspend/resume */ 60 uint64_t *pec_config_state; 61 uint64_t *mmu_config_state; 62 uint64_t *ib_intr_map; 63 uint64_t *ib_config_state; 64 uint64_t *xcb_config_state; 65 uint64_t *msiq_config_state; 66 } pxu_t; 67 68 /* 69 * Event Queue data structure. 70 */ 71 typedef struct eq_rec { 72 uint64_t eq_rec_rsvd0 : 1, /* DW 0 - 63 */ 73 eq_rec_fmt_type : 7, /* DW 0 - 62:56 */ 74 eq_rec_len : 10, /* DW 0 - 55:46 */ 75 eq_rec_addr0 : 14, /* DW 0 - 45:32 */ 76 eq_rec_rid : 16, /* DW 0 - 31:16 */ 77 eq_rec_data0 : 16; /* DW 0 - 15:00 */ 78 uint64_t eq_rec_addr1 : 48, /* DW 1 - 63:16 */ 79 eq_rec_data1 : 16; /* DW 1 - 15:0 */ 80 uint64_t eq_rec_rsvd[6]; /* DW 2-7 */ 81 } eq_rec_t; 82 83 /* 84 * EQ record type 85 * 86 * Upper 4 bits of eq_rec_fmt_type is used 87 * to identify the EQ record type. 88 */ 89 #define EQ_REC_MSG 0x6 /* MSG - 0x3X */ 90 #define EQ_REC_MSI32 0xB /* MSI32 - 0x58 */ 91 #define EQ_REC_MSI64 0xF /* MSI64 - 0x78 */ 92 93 /* EQ State */ 94 #define EQ_IDLE_STATE 0x1 /* IDLE */ 95 #define EQ_ACTIVE_STATE 0x2 /* ACTIVE */ 96 #define EQ_ERROR_STATE 0x4 /* ERROR */ 97 98 #define MMU_INVALID_TTE 0ull 99 #define MMU_TTE_VALID(tte) (((tte) & MMU_TTE_V) == MMU_TTE_V) 100 #define MMU_TTETOPA(x) ((x & 0x7ffffffffff) >> MMU_PAGE_SHIFT) 101 102 /* 103 * control register decoding 104 */ 105 /* tsb size: 0=1k 1=2k 2=4k 3=8k 4=16k 5=32k 6=64k 7=128k */ 106 #define MMU_CTL_TO_TSBSIZE(ctl) ((ctl) >> 16) 107 #define MMU_TSBSIZE_TO_TSBENTRIES(s) ((1 << (s)) << (13 - 3)) 108 109 /* 110 * For mmu bypass addresses, bit 43 specifies cacheability. 111 */ 112 #define MMU_BYPASS_NONCACHE (1ull << 43) 113 114 /* 115 * The following macros define the address ranges supported for DVMA 116 * and mmu bypass transfers. 117 */ 118 #define MMU_BYPASS_BASE 0xFFFC000000000000ull 119 #define MMU_BYPASS_END 0xFFFC01FFFFFFFFFFull 120 121 /* 122 * The following macros are for loading and unloading io tte 123 * entries. 124 */ 125 #define MMU_TTE_SIZE 8 126 #define MMU_TTE_V (1ull << 63) 127 #define MMU_TTE_W (1ull << 1) 128 129 #define INO_BITS 6 /* INO#s are 6 bits long */ 130 #define IGN_BITS 5 /* IGN#s are 5 bits long */ 131 #define INO_MASK 0x3F /* INO#s mask */ 132 #define IGN_MASK 0x1F /* IGN#s mask */ 133 134 #define ID_TO_IGN(portid) ((uint16_t)((portid) & IGN_MASK)) 135 #define ID_TO_NODEID(portid) ((uint16_t)((portid) >> IGN_BITS)) 136 #define DEVINO_TO_SYSINO(portid, devino) \ 137 ((ID_TO_NODEID(portid) << (IGN_BITS + INO_BITS)) | \ 138 ((ID_TO_IGN(portid) << INO_BITS) | (devino & INO_MASK))) 139 #define SYSINO_TO_DEVINO(sysino) (sysino & INO_MASK) 140 141 /* Interrupt states */ 142 #define INTERRUPT_IDLE_STATE 0 143 #define INTERRUPT_RECEIVED_STATE 1 144 #define INTERRUPT_PENDING_STATE 3 145 146 /* 147 * Interrupt directives needed for reading proper interrupt diag register for 148 * given ino. 149 */ 150 #define PX_INTR_DIAG_REG(CSRBASE, INO) \ 151 (INO <= 32 ? CSRBASE + INTERRUPT_STATE_STATUS_1 : \ 152 CSRBASE + INTERRUPT_STATE_STATUS_2) 153 154 #define PX_INTR_STAT_BITMAP(INO) (0x3 << (INO & 0x1f)) 155 #define PX_INTR_STATUS(INTRDIAG_REG, INO) (((*INTRDIAG_REG) \ 156 & PX_INTR_STAT_BITMAP(INO)) >> (INO & 0x1f)) 157 158 /* 159 * Defines for link width and max packet size for ACKBAK Latency Threshold Timer 160 * and TxLink Replay Timer Latency Table array sizes 161 * Num Link Width Packet Size 162 * 0 1 128 163 * 1 4 256 164 * 2 8 512 165 * 3 16 1024 166 * 4 - 2048 167 * 5 - 4096 168 */ 169 #define LINK_WIDTH_ARR_SIZE 4 170 #define LINK_MAX_PKT_ARR_SIZE 6 171 172 /* 173 * Defines for registers which have multi-bit fields. 174 */ 175 #define TLU_LINK_CONTROL_ASPM_DISABLED 0x0 176 #define TLU_LINK_CONTROL_ASPM_L0S_EN 0x1 177 #define TLU_LINK_CONTROL_ASPM_L1_EN 0x2 178 #define TLU_LINK_CONTROL_ASPM_L0S_L1_EN 0x3 179 180 #define TLU_CONTROL_CONFIG_DEFAULT 0x1 181 #define TLU_CONTROL_L0S_TIM_DEFAULT 0xdaull 182 #define TLU_CONTROL_MPS_MASK 0x1C 183 #define TLU_CONTROL_MPS_SHIFT 2 184 185 #define LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_0 0x0 186 #define LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_1 0x1 187 #define LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_2 0x2 188 #define LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_3 0x3 189 190 #define LPU_TXLINK_RETRY_FIFO_POINTER_RTRY_FIFO_TLPTR_DEFAULT 0xFFFFull 191 #define LPU_TXLINK_RETRY_FIFO_POINTER_RTRY_FIFO_HDPTR_DEFAULT 0x0ull 192 193 #define LPU_TXLINK_SEQUENCE_COUNTER_ACK_SEQ_CNTR_DEFAULT 0xFFF 194 #define LPU_TXLINK_SEQUENCE_COUNTER_NXT_TX_SEQ_CNTR_DEFAULT 0x0 195 #define LPU_TXLINK_SEQUENCE_COUNT_FIFO_MAX_ADDR_SEQ_CNT_MAX_ADDR_DEF 0x157 196 197 #define LPU_TXLINK_SEQUENCE_COUNT_FIFO_POINTERS_SEQ_CNT_TLPTR_DEFAULT 0xFFF 198 #define LPU_TXLINK_SEQUENCE_COUNT_FIFO_POINTERS_SEQ_CNT_HDPTR_DEFAULT 0x0 199 200 #define LPU_LTSSM_CONFIG1_LTSSM_8_TO_DEFAULT 0x2 201 #define LPU_LTSSM_CONFIG1_LTSSM_20_TO_DEFAULT 0x5 202 #define LPU_LTSSM_CONFIG2_LTSSM_12_TO_DEFAULT 0x2DC6C0 203 #define LPU_LTSSM_CONFIG3_LTSSM_2_TO_DEFAULT 0x7A120 204 /* 205 * XXX fix LPU_LTSSM_CONFIG4_DATA_RATE_DEFAULT & 206 * LPU_LTSSM_CONFIG4_N_FTS_DEFAULT in px_pec.h 207 */ 208 #define LPU_LTSSM_CONFIG4_DATA_RATE_DEFAULT 0x2 209 #define LPU_LTSSM_CONFIG4_N_FTS_DEFAULT 0x8c 210 211 /* 212 * The sequence of the chip_type appearance is significant. 213 * There are code depending on it: PX_CHIP_TYPE(pxu_p) < PX_CHIP_FIRE. 214 */ 215 typedef enum { 216 PX_CHIP_UNIDENTIFIED = 0, 217 PX_CHIP_FIRE = 1 218 } px_chip_id_t; 219 220 /* 221 * [msb] [lsb] 222 * 0x00 <chip_type> <version#> <module-revision#> 223 */ 224 #define PX_CHIP_ID(t, v, m) (((t) << 16) | ((v) << 8) | (m)) 225 #define PX_ID_CHIP_TYPE(id) ((id) >> 16) 226 #define PX_CHIP_TYPE(pxu_p) PX_ID_CHIP_TYPE(PX_CHIP_ID((pxu_p)->chip_id)) 227 #define PX_CHIP_REV(pxu_p) PX_CHIP_ID(((pxu_p)->chip_id) & 0xFF) 228 #define PX_CHIP_VER(pxu_p) PX_CHIP_ID((((pxu_p)->chip_id) >> 8) & 0xFF) 229 230 /* 231 * Fire hardware specific version definitions. 232 */ 233 #define FIRE_VER_10 PX_CHIP_ID(PX_CHIP_FIRE, 0x01, 0x00) 234 #define FIRE_VER_20 PX_CHIP_ID(PX_CHIP_FIRE, 0x03, 0x00) 235 236 extern void hvio_cb_init(caddr_t xbc_csr_base, pxu_t *pxu_p); 237 extern void hvio_ib_init(caddr_t csr_base, pxu_t *pxu_p); 238 extern void hvio_mmu_init(caddr_t csr_base, pxu_t *pxu_p); 239 extern void hvio_pec_init(caddr_t csr_base, pxu_t *pxu_p); 240 241 #ifdef VPCI_CONFIG_ACCESS 242 extern uint64_t hvio_config_get(devhandle_t dev_hdl, pci_device_t bdf, 243 pci_config_offset_t off, pci_config_size_t size, pci_cfg_data_t *data_p); 244 extern uint64_t hvio_config_put(devhandle_t dev_hdl, pci_device_t bdf, 245 pci_config_offset_t off, pci_config_size_t size, pci_cfg_data_t data); 246 #endif /* VPCI_CONFIG_ACCESS */ 247 248 extern uint64_t hvio_intr_devino_to_sysino(devhandle_t dev_hdl, pxu_t *pxu_p, 249 devino_t devino, sysino_t *sysino); 250 extern uint64_t hvio_intr_getvalid(devhandle_t dev_hdl, sysino_t sysino, 251 intr_valid_state_t *intr_valid_state); 252 extern uint64_t hvio_intr_setvalid(devhandle_t dev_hdl, sysino_t sysino, 253 intr_valid_state_t intr_valid_state); 254 extern uint64_t hvio_intr_getstate(devhandle_t dev_hdl, sysino_t sysino, 255 intr_state_t *intr_state); 256 extern uint64_t hvio_intr_setstate(devhandle_t dev_hdl, sysino_t sysino, 257 intr_state_t intr_state); 258 extern uint64_t hvio_intr_gettarget(devhandle_t dev_hdl, sysino_t sysino, 259 cpuid_t *cpuid); 260 extern uint64_t hvio_intr_settarget(devhandle_t dev_hdl, sysino_t sysino, 261 cpuid_t cpuid); 262 263 extern uint64_t hvio_iommu_map(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid, 264 pages_t pages, io_attributes_t io_attributes, 265 void *addr, size_t pfn_index, int flag); 266 extern uint64_t hvio_iommu_demap(devhandle_t dev_hdl, pxu_t *pxu_p, 267 tsbid_t tsbid, pages_t pages); 268 extern uint64_t hvio_iommu_getmap(devhandle_t dev_hdl, pxu_t *pxu_p, 269 tsbid_t tsbid, io_attributes_t *attributes_p, r_addr_t *r_addr_p); 270 extern uint64_t hvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra, 271 io_attributes_t io_attributes, io_addr_t *io_addr_p); 272 273 /* 274 * MSIQ Functions: 275 */ 276 extern uint64_t hvio_msiq_init(devhandle_t dev_hdl, pxu_t *pxu_p); 277 extern uint64_t hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 278 pci_msiq_valid_state_t *msiq_valid_state); 279 extern uint64_t hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 280 pci_msiq_valid_state_t msiq_valid_state); 281 extern uint64_t hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id, 282 pci_msiq_state_t *msiq_state); 283 extern uint64_t hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id, 284 pci_msiq_state_t msiq_state); 285 extern uint64_t hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id, 286 msiqhead_t *msiq_head); 287 extern uint64_t hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id, 288 msiqhead_t msiq_head); 289 extern uint64_t hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id, 290 msiqtail_t *msiq_tail); 291 292 /* 293 * MSI Functions: 294 */ 295 extern uint64_t hvio_msi_init(devhandle_t dev_hdl, uint64_t addr32, 296 uint64_t addr64); 297 extern uint64_t hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num, 298 msiqid_t *msiq_id); 299 extern uint64_t hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num, 300 msiqid_t msiq_id); 301 extern uint64_t hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num, 302 pci_msi_valid_state_t *msi_valid_state); 303 extern uint64_t hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num, 304 pci_msi_valid_state_t msi_valid_state); 305 extern uint64_t hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num, 306 pci_msi_state_t *msi_state); 307 extern uint64_t hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num, 308 pci_msi_state_t msi_state); 309 310 /* 311 * MSG Functions: 312 */ 313 extern uint64_t hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 314 msiqid_t *msiq_id); 315 extern uint64_t hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 316 msiqid_t msiq_id); 317 extern uint64_t hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 318 pcie_msg_valid_state_t *msg_valid_state); 319 extern uint64_t hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 320 pcie_msg_valid_state_t msg_valid_state); 321 322 /* 323 * Suspend/Resume Functions: 324 */ 325 extern uint64_t hvio_suspend(devhandle_t dev_hdl, pxu_t *pxu_p); 326 extern void hvio_resume(devhandle_t dev_hdl, 327 devino_t devino, pxu_t *pxu_p); 328 extern uint64_t hvio_cb_suspend(devhandle_t dev_hdl, pxu_t *pxu_p); 329 extern void hvio_cb_resume(devhandle_t pci_dev_hdl, devhandle_t xbus_dev_hdl, 330 devino_t devino, pxu_t *pxu_p); 331 extern int px_send_pme_turnoff(caddr_t csr_base); 332 333 #ifdef __cplusplus 334 } 335 #endif 336 337 #endif /* _SYS_PX_LIB4U_H */ 338