1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PX_LIB4U_H 27 #define _SYS_PX_LIB4U_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /* 36 * Errors returned. 37 */ 38 #define H_EOK 0 /* Successful return */ 39 #define H_ENOINTR 1 /* Invalid interrupt id */ 40 #define H_EINVAL 2 /* Invalid argument */ 41 #define H_ENOACCESS 3 /* No access to resource */ 42 #define H_EIO 4 /* I/O error */ 43 #define H_ENOTSUPPORTED 5 /* Function not supported */ 44 #define H_ENOMAP 6 /* Mapping is not valid, */ 45 /* no translation exists */ 46 47 /* 48 * Register base definitions. 49 * 50 * The specific numeric values for CSR, XBUS, Configuration, 51 * Interrupt blocks and other register bases. 52 */ 53 typedef enum { 54 PX_REG_CSR = 0, 55 PX_REG_XBC, 56 PX_REG_CFG, 57 PX_REG_IC, 58 PX_REG_MAX 59 } px_reg_bank_t; 60 61 /* 62 * Registers/state/variables that need to be saved and restored during 63 * suspend/resume. 64 * 65 * SUN4U px specific data structure. 66 */ 67 68 /* Control block soft state structure */ 69 typedef struct px_cb_list { 70 px_t *pxp; 71 struct px_cb_list *next; 72 } px_cb_list_t; 73 74 typedef struct px_cb { 75 px_cb_list_t *pxl; /* linked list px */ 76 kmutex_t cb_mutex; /* lock for CB */ 77 sysino_t sysino; /* proxy sysino */ 78 cpuid_t cpuid; /* proxy cpuid */ 79 int attachcnt; /* number of attached px */ 80 uint_t (*px_cb_func)(caddr_t); /* CB intr dispatcher */ 81 } px_cb_t; 82 83 typedef struct pxu { 84 uint32_t chip_id; 85 uint8_t portid; 86 uint16_t tsb_cookie; 87 uint32_t tsb_size; 88 uint64_t *tsb_vaddr; 89 void *msiq_mapped_p; 90 px_cb_t *px_cb_p; 91 92 /* Soft state for suspend/resume */ 93 uint64_t *pec_config_state; 94 uint64_t *mmu_config_state; 95 uint64_t *ib_intr_map; 96 uint64_t *ib_config_state; 97 uint64_t *xcb_config_state; 98 uint64_t *msiq_config_state; 99 100 /* sun4u specific vars */ 101 caddr_t px_address[4]; 102 ddi_acc_handle_t px_ac[4]; 103 } pxu_t; 104 105 #define PX2CB(px_p) (((pxu_t *)px_p->px_plat_p)->px_cb_p) 106 107 /* 108 * Event Queue data structure. 109 */ 110 typedef struct eq_rec { 111 uint64_t eq_rec_rsvd0 : 1, /* DW 0 - 63 */ 112 eq_rec_fmt_type : 7, /* DW 0 - 62:56 */ 113 eq_rec_len : 10, /* DW 0 - 55:46 */ 114 eq_rec_addr0 : 14, /* DW 0 - 45:32 */ 115 eq_rec_rid : 16, /* DW 0 - 31:16 */ 116 eq_rec_data0 : 16; /* DW 0 - 15:00 */ 117 uint64_t eq_rec_addr1 : 48, /* DW 1 - 63:16 */ 118 eq_rec_data1 : 16; /* DW 1 - 15:0 */ 119 uint64_t eq_rec_rsvd[6]; /* DW 2-7 */ 120 } eq_rec_t; 121 122 /* 123 * EQ record type 124 * 125 * Upper 4 bits of eq_rec_fmt_type is used 126 * to identify the EQ record type. 127 */ 128 #define EQ_REC_MSG 0x6 /* MSG - 0x3X */ 129 #define EQ_REC_MSI32 0xB /* MSI32 - 0x58 */ 130 #define EQ_REC_MSI64 0xF /* MSI64 - 0x78 */ 131 132 /* EQ State */ 133 #define EQ_IDLE_STATE 0x1 /* IDLE */ 134 #define EQ_ACTIVE_STATE 0x2 /* ACTIVE */ 135 #define EQ_ERROR_STATE 0x4 /* ERROR */ 136 137 #define MMU_INVALID_TTE 0ull 138 #define MMU_TTE_VALID(tte) (((tte) & MMU_TTE_V) == MMU_TTE_V) 139 #define MMU_TTETOPA(x) ((x & 0x7ffffffffff) >> MMU_PAGE_SHIFT) 140 141 /* 142 * control register decoding 143 */ 144 /* tsb size: 0=1k 1=2k 2=4k 3=8k 4=16k 5=32k 6=64k 7=128k */ 145 #define MMU_CTL_TO_TSBSIZE(ctl) ((ctl) >> 16) 146 #define MMU_TSBSIZE_TO_TSBENTRIES(s) ((1 << (s)) << (13 - 3)) 147 148 /* 149 * For mmu bypass addresses, bit 43 specifies cacheability. 150 */ 151 #define MMU_BYPASS_NONCACHE (1ull << 43) 152 153 /* 154 * The following macros define the address ranges supported for DVMA 155 * and mmu bypass transfers. 156 */ 157 #define MMU_BYPASS_BASE 0xFFFC000000000000ull 158 #define MMU_BYPASS_END 0xFFFC01FFFFFFFFFFull 159 160 /* 161 * The following macros are for loading and unloading io tte 162 * entries. 163 */ 164 #define MMU_TTE_SIZE 8 165 #define MMU_TTE_V (1ull << 63) 166 #define MMU_TTE_W (1ull << 1) 167 168 #define INO_BITS 6 /* INO#s are 6 bits long */ 169 #define IGN_BITS 5 /* IGN#s are 5 bits long */ 170 #define INO_MASK 0x3F /* INO#s mask */ 171 #define IGN_MASK 0x1F /* IGN#s mask */ 172 173 #define ID_TO_IGN(portid) ((uint16_t)((portid) & IGN_MASK)) 174 #define ID_TO_NODEID(portid) ((uint16_t)((portid) >> IGN_BITS)) 175 #define DEVINO_TO_SYSINO(portid, devino) \ 176 ((ID_TO_NODEID(portid) << (IGN_BITS + INO_BITS)) | \ 177 ((ID_TO_IGN(portid) << INO_BITS) | (devino & INO_MASK))) 178 #define SYSINO_TO_DEVINO(sysino) (sysino & INO_MASK) 179 180 /* Interrupt states */ 181 #define INTERRUPT_IDLE_STATE 0 182 #define INTERRUPT_RECEIVED_STATE 1 183 #define INTERRUPT_PENDING_STATE 3 184 185 /* 186 * Defines for link width and max packet size for ACKBAK Latency Threshold Timer 187 * and TxLink Replay Timer Latency Table array sizes 188 * Num Link Width Packet Size 189 * 0 1 128 190 * 1 4 256 191 * 2 8 512 192 * 3 16 1024 193 * 4 - 2048 194 * 5 - 4096 195 */ 196 #define LINK_WIDTH_ARR_SIZE 4 197 #define LINK_MAX_PKT_ARR_SIZE 6 198 199 /* 200 * Defines for registers which have multi-bit fields. 201 */ 202 #define TLU_LINK_CONTROL_ASPM_DISABLED 0x0 203 #define TLU_LINK_CONTROL_ASPM_L0S_EN 0x1 204 #define TLU_LINK_CONTROL_ASPM_L1_EN 0x2 205 #define TLU_LINK_CONTROL_ASPM_L0S_L1_EN 0x3 206 207 #define TLU_CONTROL_CONFIG_DEFAULT 0x1 208 #define TLU_CONTROL_L0S_TIM_DEFAULT 0xdaull 209 #define TLU_CONTROL_MPS_MASK 0x1C 210 #define TLU_CONTROL_MPS_SHIFT 2 211 212 #define LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_0 0x0 213 #define LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_1 0x1 214 #define LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_2 0x2 215 #define LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_3 0x3 216 217 #define LPU_TXLINK_RETRY_FIFO_POINTER_RTRY_FIFO_TLPTR_DEFAULT 0xFFFFull 218 #define LPU_TXLINK_RETRY_FIFO_POINTER_RTRY_FIFO_HDPTR_DEFAULT 0x0ull 219 220 #define LPU_TXLINK_SEQUENCE_COUNTER_ACK_SEQ_CNTR_DEFAULT 0xFFF 221 #define LPU_TXLINK_SEQUENCE_COUNTER_NXT_TX_SEQ_CNTR_DEFAULT 0x0 222 #define LPU_TXLINK_SEQUENCE_COUNT_FIFO_MAX_ADDR_SEQ_CNT_MAX_ADDR_DEF 0x157 223 224 #define LPU_TXLINK_SEQUENCE_COUNT_FIFO_POINTERS_SEQ_CNT_TLPTR_DEFAULT 0xFFF 225 #define LPU_TXLINK_SEQUENCE_COUNT_FIFO_POINTERS_SEQ_CNT_HDPTR_DEFAULT 0x0 226 227 #define LPU_LTSSM_CONFIG1_LTSSM_8_TO_DEFAULT 0x2 228 #define LPU_LTSSM_CONFIG1_LTSSM_20_TO_DEFAULT 0x5 229 #define LPU_LTSSM_CONFIG2_LTSSM_12_TO_DEFAULT 0x2DC6C0 230 #define LPU_LTSSM_CONFIG3_LTSSM_2_TO_DEFAULT 0x7A120 231 #define LPU_LTSSM_CONFIG4_DATA_RATE_DEFAULT 0x2 232 #define LPU_LTSSM_CONFIG4_N_FTS_DEFAULT 0x8c 233 234 /* LPU LTSSM states */ 235 #define LPU_LTSSM_L0 0x0 236 #define LPU_LTSSM_L1_IDLE 0x15 237 238 /* TLU Control register bits */ 239 #define TLU_REMAIN_DETECT_QUIET 8 240 241 /* PX BDF Shift in a Phyiscal Address - used FMA Fabric only */ 242 #define PX_PA_BDF_SHIFT 12 243 #define PX_BDF_TO_CFGADDR(bdf, offset) (((bdf) << PX_PA_BDF_SHIFT) + (offset)) 244 245 /* 246 * The sequence of the chip_type appearance is significant. 247 * There are code depending on it: PX_CHIP_TYPE(pxu_p) < PX_CHIP_FIRE. 248 */ 249 typedef enum { 250 PX_CHIP_UNIDENTIFIED = 0, 251 PX_CHIP_FIRE = 1 252 } px_chip_id_t; 253 254 /* 255 * [msb] [lsb] 256 * 0x00 <chip_type> <version#> <module-revision#> 257 */ 258 #define PX_CHIP_ID(t, v, m) (((t) << 16) | ((v) << 8) | (m)) 259 #define PX_ID_CHIP_TYPE(id) ((id) >> 16) 260 #define PX_CHIP_TYPE(pxu_p) PX_ID_CHIP_TYPE(PX_CHIP_ID((pxu_p)->chip_id)) 261 #define PX_CHIP_REV(pxu_p) PX_CHIP_ID(((pxu_p)->chip_id) & 0xFF) 262 #define PX_CHIP_VER(pxu_p) PX_CHIP_ID((((pxu_p)->chip_id) >> 8) & 0xFF) 263 264 /* 265 * Fire hardware specific version definitions. 266 */ 267 #define FIRE_VER_10 PX_CHIP_ID(PX_CHIP_FIRE, 0x01, 0x00) 268 #define FIRE_VER_20 PX_CHIP_ID(PX_CHIP_FIRE, 0x03, 0x00) 269 270 extern void hvio_cb_init(caddr_t xbc_csr_base, pxu_t *pxu_p); 271 extern void hvio_ib_init(caddr_t csr_base, pxu_t *pxu_p); 272 extern void hvio_mmu_init(caddr_t csr_base, pxu_t *pxu_p); 273 extern void hvio_pec_init(caddr_t csr_base, pxu_t *pxu_p); 274 275 extern uint64_t hvio_intr_devino_to_sysino(devhandle_t dev_hdl, pxu_t *pxu_p, 276 devino_t devino, sysino_t *sysino); 277 extern uint64_t hvio_intr_getvalid(devhandle_t dev_hdl, sysino_t sysino, 278 intr_valid_state_t *intr_valid_state); 279 extern uint64_t hvio_intr_setvalid(devhandle_t dev_hdl, sysino_t sysino, 280 intr_valid_state_t intr_valid_state); 281 extern uint64_t hvio_intr_getstate(devhandle_t dev_hdl, sysino_t sysino, 282 intr_state_t *intr_state); 283 extern uint64_t hvio_intr_setstate(devhandle_t dev_hdl, sysino_t sysino, 284 intr_state_t intr_state); 285 extern uint64_t hvio_intr_gettarget(devhandle_t dev_hdl, sysino_t sysino, 286 cpuid_t *cpuid); 287 extern uint64_t hvio_intr_settarget(devhandle_t dev_hdl, sysino_t sysino, 288 cpuid_t cpuid); 289 290 extern uint64_t hvio_iommu_map(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid, 291 pages_t pages, io_attributes_t attr, void *addr, size_t pfn_index, 292 int flags); 293 extern uint64_t hvio_iommu_demap(devhandle_t dev_hdl, pxu_t *pxu_p, 294 tsbid_t tsbid, pages_t pages); 295 extern uint64_t hvio_iommu_getmap(devhandle_t dev_hdl, pxu_t *pxu_p, 296 tsbid_t tsbid, io_attributes_t *attr_p, r_addr_t *r_addr_p); 297 extern uint64_t hvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra, 298 io_attributes_t attr, io_addr_t *io_addr_p); 299 300 /* 301 * MSIQ Functions: 302 */ 303 extern uint64_t hvio_msiq_init(devhandle_t dev_hdl, pxu_t *pxu_p); 304 extern uint64_t hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 305 pci_msiq_valid_state_t *msiq_valid_state); 306 extern uint64_t hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 307 pci_msiq_valid_state_t msiq_valid_state); 308 extern uint64_t hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id, 309 pci_msiq_state_t *msiq_state); 310 extern uint64_t hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id, 311 pci_msiq_state_t msiq_state); 312 extern uint64_t hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id, 313 msiqhead_t *msiq_head); 314 extern uint64_t hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id, 315 msiqhead_t msiq_head); 316 extern uint64_t hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id, 317 msiqtail_t *msiq_tail); 318 319 /* 320 * MSI Functions: 321 */ 322 extern uint64_t hvio_msi_init(devhandle_t dev_hdl, uint64_t addr32, 323 uint64_t addr64); 324 extern uint64_t hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num, 325 msiqid_t *msiq_id); 326 extern uint64_t hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num, 327 msiqid_t msiq_id); 328 extern uint64_t hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num, 329 pci_msi_valid_state_t *msi_valid_state); 330 extern uint64_t hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num, 331 pci_msi_valid_state_t msi_valid_state); 332 extern uint64_t hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num, 333 pci_msi_state_t *msi_state); 334 extern uint64_t hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num, 335 pci_msi_state_t msi_state); 336 337 /* 338 * MSG Functions: 339 */ 340 extern uint64_t hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 341 msiqid_t *msiq_id); 342 extern uint64_t hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 343 msiqid_t msiq_id); 344 extern uint64_t hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 345 pcie_msg_valid_state_t *msg_valid_state); 346 extern uint64_t hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 347 pcie_msg_valid_state_t msg_valid_state); 348 349 /* 350 * Suspend/Resume Functions: 351 */ 352 extern uint64_t hvio_suspend(devhandle_t dev_hdl, pxu_t *pxu_p); 353 extern void hvio_resume(devhandle_t dev_hdl, 354 devino_t devino, pxu_t *pxu_p); 355 extern uint64_t hvio_cb_suspend(devhandle_t dev_hdl, pxu_t *pxu_p); 356 extern void hvio_cb_resume(devhandle_t pci_dev_hdl, devhandle_t xbus_dev_hdl, 357 devino_t devino, pxu_t *pxu_p); 358 extern int px_send_pme_turnoff(caddr_t csr_base); 359 extern int px_link_wait4l1idle(caddr_t csr_base); 360 extern int px_link_retrain(caddr_t csr_base); 361 extern void px_enable_detect_quiet(caddr_t csr_base); 362 363 extern void px_lib_clr_errs(px_t *px_p); 364 365 #ifdef __cplusplus 366 } 367 #endif 368 369 #endif /* _SYS_PX_LIB4U_H */ 370