1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PX_LIB4U_H 27 #define _SYS_PX_LIB4U_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /* 36 * Errors returned. 37 */ 38 #define H_EOK 0 /* Successful return */ 39 #define H_ENOINTR 1 /* Invalid interrupt id */ 40 #define H_EINVAL 2 /* Invalid argument */ 41 #define H_ENOACCESS 3 /* No access to resource */ 42 #define H_EIO 4 /* I/O error */ 43 #define H_ENOTSUPPORTED 5 /* Function not supported */ 44 #define H_ENOMAP 6 /* Mapping is not valid, */ 45 /* no translation exists */ 46 47 /* 48 * Register base definitions. 49 * 50 * The specific numeric values for CSR, XBUS, Configuration, 51 * Interrupt blocks and other register bases. 52 */ 53 typedef enum { 54 PX_REG_CSR = 0, 55 PX_REG_XBC, 56 PX_REG_CFG, 57 PX_REG_IC, 58 PX_REG_MAX 59 } px_reg_bank_t; 60 61 /* 62 * Registers/state/variables that need to be saved and restored during 63 * suspend/resume. 64 * 65 * SUN4U px specific data structure. 66 */ 67 68 /* Control block soft state structure */ 69 typedef struct px_cb_list { 70 px_t *pxp; 71 struct px_cb_list *next; 72 } px_cb_list_t; 73 74 /* IO chip type */ 75 typedef enum { 76 PX_CHIP_UNIDENTIFIED = 0, 77 PX_CHIP_FIRE = 1, 78 PX_CHIP_OBERON = 2 79 } px_chip_type_t; 80 81 #define PX_CHIP_TYPE(pxu_p) ((pxu_p)->chip_type) 82 83 typedef struct px_cb { 84 px_cb_list_t *pxl; /* linked list px */ 85 kmutex_t cb_mutex; /* lock for CB */ 86 sysino_t sysino; /* proxy sysino */ 87 cpuid_t cpuid; /* proxy cpuid */ 88 int attachcnt; /* number of attached px */ 89 uint_t (*px_cb_func)(caddr_t); /* CB intr dispatcher */ 90 } px_cb_t; 91 92 typedef struct pxu { 93 px_chip_type_t chip_type; 94 uint8_t portid; 95 uint16_t tsb_cookie; 96 uint32_t tsb_size; 97 uint64_t *tsb_vaddr; 98 uint64_t tsb_paddr; /* Only used for Oberon */ 99 100 void *msiq_mapped_p; 101 px_cb_t *px_cb_p; 102 103 /* Soft state for suspend/resume */ 104 uint64_t *pec_config_state; 105 uint64_t *mmu_config_state; 106 uint64_t *ib_intr_map; 107 uint64_t *ib_config_state; 108 uint64_t *xcb_config_state; 109 uint64_t *msiq_config_state; 110 111 /* sun4u specific vars */ 112 caddr_t px_address[4]; 113 ddi_acc_handle_t px_ac[4]; 114 115 /* PCItool */ 116 caddr_t pcitool_addr; 117 } pxu_t; 118 119 #define PX2CB(px_p) (((pxu_t *)px_p->px_plat_p)->px_cb_p) 120 121 /* 122 * Event Queue data structure. 123 */ 124 typedef struct eq_rec { 125 uint64_t eq_rec_rsvd0 : 1, /* DW 0 - 63 */ 126 eq_rec_fmt_type : 7, /* DW 0 - 62:56 */ 127 eq_rec_len : 10, /* DW 0 - 55:46 */ 128 eq_rec_addr0 : 14, /* DW 0 - 45:32 */ 129 eq_rec_rid : 16, /* DW 0 - 31:16 */ 130 eq_rec_data0 : 16; /* DW 0 - 15:00 */ 131 uint64_t eq_rec_addr1 : 48, /* DW 1 - 63:16 */ 132 eq_rec_data1 : 16; /* DW 1 - 15:0 */ 133 uint64_t eq_rec_rsvd[6]; /* DW 2-7 */ 134 } eq_rec_t; 135 136 /* 137 * EQ record type 138 * 139 * Upper 4 bits of eq_rec_fmt_type is used 140 * to identify the EQ record type. 141 */ 142 #define EQ_REC_MSG 0x6 /* MSG - 0x3X */ 143 #define EQ_REC_MSI32 0xB /* MSI32 - 0x58 */ 144 #define EQ_REC_MSI64 0xF /* MSI64 - 0x78 */ 145 146 /* EQ State */ 147 #define EQ_IDLE_STATE 0x1 /* IDLE */ 148 #define EQ_ACTIVE_STATE 0x2 /* ACTIVE */ 149 #define EQ_ERROR_STATE 0x4 /* ERROR */ 150 151 #define MMU_INVALID_TTE 0ull 152 #define MMU_TTE_VALID(tte) (((tte) & MMU_TTE_V) == MMU_TTE_V) 153 #define MMU_OBERON_PADDR_MASK 0x7fffffffffff 154 #define MMU_FIRE_PADDR_MASK 0x7ffffffffff 155 156 /* 157 * control register decoding 158 */ 159 /* tsb size: 0=1k 1=2k 2=4k 3=8k 4=16k 5=32k 6=64k 7=128k */ 160 #define MMU_CTL_TO_TSBSIZE(ctl) ((ctl) >> 16) 161 #define MMU_TSBSIZE_TO_TSBENTRIES(s) ((1 << (s)) << (13 - 3)) 162 163 /* 164 * For Fire mmu bypass addresses, bit 43 specifies cacheability. 165 */ 166 #define MMU_FIRE_BYPASS_NONCACHE (1ull << 43) 167 168 /* 169 * For Oberon mmu bypass addresses, bit 47 specifies cacheability. 170 */ 171 #define MMU_OBERON_BYPASS_NONCACHE (1ull << 47) 172 173 /* 174 * The following macros define the address ranges supported for DVMA 175 * and mmu bypass transfers. For Oberon, bit 63 is used for ordering. 176 */ 177 #define MMU_FIRE_BYPASS_BASE 0xFFFC000000000000ull 178 #define MMU_FIRE_BYPASS_END 0xFFFC01FFFFFFFFFFull 179 180 #define MMU_OBERON_BYPASS_BASE 0x7FFC000000000000ull 181 #define MMU_OBERON_BYPASS_END 0x7FFC01FFFFFFFFFFull 182 183 #define MMU_TSB_PA_MASK 0x7FFFFFFFE000 184 185 /* 186 * The following macros are for loading and unloading io tte 187 * entries. 188 */ 189 #define MMU_TTE_SIZE 8 190 #define MMU_TTE_V (1ull << 63) 191 #define MMU_TTE_W (1ull << 1) 192 #define MMU_TTE_RO (1ull << 62) /* Oberon Relaxed Ordering */ 193 194 #define INO_BITS 6 /* INO#s are 6 bits long */ 195 #define INO_MASK 0x3F /* INO#s mask */ 196 197 #define SYSINO_TO_DEVINO(sysino) (sysino & INO_MASK) 198 199 #define FIRE_IGN_MASK 0x1F /* IGN#s mask, 5 bits long for Fire */ 200 #define OBERON_IGN_MASK 0xFF /* IGN#s mask, 8 bits long for Oberon */ 201 202 #define ID_TO_IGN(chip, portid) ((portid) & ((chip) == PX_CHIP_OBERON ? \ 203 OBERON_IGN_MASK : FIRE_IGN_MASK)) 204 205 #define DEVINO_TO_SYSINO(portid, devino) \ 206 (((portid) << INO_BITS) | ((devino) & INO_MASK)) 207 208 /* Interrupt states */ 209 #define INTERRUPT_IDLE_STATE 0 210 #define INTERRUPT_RECEIVED_STATE 1 211 #define INTERRUPT_PENDING_STATE 3 212 213 /* 214 * Defines for link width and max packet size for ACKBAK Latency Threshold Timer 215 * and TxLink Replay Timer Latency Table array sizes 216 * Num Link Width Packet Size 217 * 0 1 128 218 * 1 4 256 219 * 2 8 512 220 * 3 16 1024 221 * 4 - 2048 222 * 5 - 4096 223 */ 224 #define LINK_WIDTH_ARR_SIZE 4 225 #define LINK_MAX_PKT_ARR_SIZE 6 226 227 /* 228 * Defines for registers which have multi-bit fields. 229 */ 230 #define TLU_LINK_CONTROL_ASPM_DISABLED 0x0 231 #define TLU_LINK_CONTROL_ASPM_L0S_EN 0x1 232 #define TLU_LINK_CONTROL_ASPM_L1_EN 0x2 233 #define TLU_LINK_CONTROL_ASPM_L0S_L1_EN 0x3 234 235 #define TLU_CONTROL_CONFIG_DEFAULT 0x1 236 #define TLU_CONTROL_L0S_TIM_DEFAULT 0xdaull 237 #define TLU_CONTROL_MPS_MASK 0x1C 238 #define TLU_CONTROL_MPS_SHIFT 2 239 240 #define LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_0 0x0 241 #define LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_1 0x1 242 #define LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_2 0x2 243 #define LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_3 0x3 244 245 #define LPU_TXLINK_RETRY_FIFO_POINTER_RTRY_FIFO_TLPTR_DEFAULT 0xFFFFull 246 #define LPU_TXLINK_RETRY_FIFO_POINTER_RTRY_FIFO_HDPTR_DEFAULT 0x0ull 247 248 #define LPU_TXLINK_SEQUENCE_COUNTER_ACK_SEQ_CNTR_DEFAULT 0xFFF 249 #define LPU_TXLINK_SEQUENCE_COUNTER_NXT_TX_SEQ_CNTR_DEFAULT 0x0 250 #define LPU_TXLINK_SEQUENCE_COUNT_FIFO_MAX_ADDR_SEQ_CNT_MAX_ADDR_DEF 0x157 251 252 #define LPU_TXLINK_SEQUENCE_COUNT_FIFO_POINTERS_SEQ_CNT_TLPTR_DEFAULT 0xFFF 253 #define LPU_TXLINK_SEQUENCE_COUNT_FIFO_POINTERS_SEQ_CNT_HDPTR_DEFAULT 0x0 254 255 #define LPU_LTSSM_CONFIG1_LTSSM_8_TO_DEFAULT 0x2 256 #define LPU_LTSSM_CONFIG1_LTSSM_20_TO_DEFAULT 0x5 257 #define LPU_LTSSM_CONFIG2_LTSSM_12_TO_DEFAULT 0x2DC6C0 258 #define LPU_LTSSM_CONFIG3_LTSSM_2_TO_DEFAULT 0x7A120 259 #define LPU_LTSSM_CONFIG4_DATA_RATE_DEFAULT 0x2 260 #define LPU_LTSSM_CONFIG4_N_FTS_DEFAULT 0x8c 261 262 /* LPU LTSSM states */ 263 #define LPU_LTSSM_L0 0x0 264 #define LPU_LTSSM_L1_IDLE 0x15 265 266 /* TLU Control register bits */ 267 #define TLU_REMAIN_DETECT_QUIET 8 268 269 /* PX BDF Shift in a Phyiscal Address - used FMA Fabric only */ 270 #define PX_PA_BDF_SHIFT 12 271 #define PX_BDF_TO_CFGADDR(bdf, offset) (((bdf) << PX_PA_BDF_SHIFT) + (offset)) 272 273 /* 274 * Fire hardware specific version definitions. 275 * All Fire versions > 2.0 will be numerically greater than FIRE_MOD_REV_20 276 */ 277 #define FIRE_MOD_REV_20 0x03 278 279 /* 280 * Oberon specific definitions. 281 */ 282 #define OBERON_RANGE_PROP_MASK 0x7fff 283 284 /* 285 * HW specific paddr mask. 286 */ 287 extern uint64_t px_paddr_mask; 288 289 extern void hvio_cb_init(caddr_t xbc_csr_base, pxu_t *pxu_p); 290 extern void hvio_ib_init(caddr_t csr_base, pxu_t *pxu_p); 291 extern void hvio_mmu_init(caddr_t csr_base, pxu_t *pxu_p); 292 extern void hvio_pec_init(caddr_t csr_base, pxu_t *pxu_p); 293 294 extern uint64_t hvio_intr_devino_to_sysino(devhandle_t dev_hdl, pxu_t *pxu_p, 295 devino_t devino, sysino_t *sysino); 296 extern uint64_t hvio_intr_getvalid(devhandle_t dev_hdl, sysino_t sysino, 297 intr_valid_state_t *intr_valid_state); 298 extern uint64_t hvio_intr_setvalid(devhandle_t dev_hdl, sysino_t sysino, 299 intr_valid_state_t intr_valid_state); 300 extern uint64_t hvio_intr_getstate(devhandle_t dev_hdl, sysino_t sysino, 301 intr_state_t *intr_state); 302 extern uint64_t hvio_intr_setstate(devhandle_t dev_hdl, sysino_t sysino, 303 intr_state_t intr_state); 304 extern uint64_t hvio_intr_gettarget(devhandle_t dev_hdl, pxu_t *pxu_p, 305 sysino_t sysino, cpuid_t *cpuid); 306 extern uint64_t hvio_intr_settarget(devhandle_t dev_hdl, pxu_t *pxu_p, 307 sysino_t sysino, cpuid_t cpuid); 308 309 extern uint64_t hvio_iommu_map(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid, 310 pages_t pages, io_attributes_t attr, void *addr, size_t pfn_index, 311 int flags); 312 extern uint64_t hvio_iommu_demap(devhandle_t dev_hdl, pxu_t *pxu_p, 313 tsbid_t tsbid, pages_t pages); 314 extern uint64_t hvio_iommu_getmap(devhandle_t dev_hdl, pxu_t *pxu_p, 315 tsbid_t tsbid, io_attributes_t *attr_p, r_addr_t *r_addr_p); 316 extern uint64_t hvio_iommu_getbypass(devhandle_t dev_hdl, pxu_t *pxu_p, 317 r_addr_t ra, io_attributes_t attr, io_addr_t *io_addr_p); 318 extern uint64_t hvio_get_bypass_base(pxu_t *pxu_p); 319 extern uint64_t hvio_get_bypass_end(pxu_t *pxu_p); 320 extern uint64_t px_get_range_prop(px_t *px_p, px_ranges_t *rp, int bank); 321 322 323 /* 324 * MSIQ Functions: 325 */ 326 extern uint64_t hvio_msiq_init(devhandle_t dev_hdl, pxu_t *pxu_p); 327 extern uint64_t hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 328 pci_msiq_valid_state_t *msiq_valid_state); 329 extern uint64_t hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 330 pci_msiq_valid_state_t msiq_valid_state); 331 extern uint64_t hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id, 332 pci_msiq_state_t *msiq_state); 333 extern uint64_t hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id, 334 pci_msiq_state_t msiq_state); 335 extern uint64_t hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id, 336 msiqhead_t *msiq_head); 337 extern uint64_t hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id, 338 msiqhead_t msiq_head); 339 extern uint64_t hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id, 340 msiqtail_t *msiq_tail); 341 342 /* 343 * MSI Functions: 344 */ 345 extern uint64_t hvio_msi_init(devhandle_t dev_hdl, uint64_t addr32, 346 uint64_t addr64); 347 extern uint64_t hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num, 348 msiqid_t *msiq_id); 349 extern uint64_t hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num, 350 msiqid_t msiq_id); 351 extern uint64_t hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num, 352 pci_msi_valid_state_t *msi_valid_state); 353 extern uint64_t hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num, 354 pci_msi_valid_state_t msi_valid_state); 355 extern uint64_t hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num, 356 pci_msi_state_t *msi_state); 357 extern uint64_t hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num, 358 pci_msi_state_t msi_state); 359 360 /* 361 * MSG Functions: 362 */ 363 extern uint64_t hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 364 msiqid_t *msiq_id); 365 extern uint64_t hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 366 msiqid_t msiq_id); 367 extern uint64_t hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 368 pcie_msg_valid_state_t *msg_valid_state); 369 extern uint64_t hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 370 pcie_msg_valid_state_t msg_valid_state); 371 372 /* 373 * Suspend/Resume Functions: 374 */ 375 extern uint64_t hvio_suspend(devhandle_t dev_hdl, pxu_t *pxu_p); 376 extern void hvio_resume(devhandle_t dev_hdl, 377 devino_t devino, pxu_t *pxu_p); 378 extern uint64_t hvio_cb_suspend(devhandle_t dev_hdl, pxu_t *pxu_p); 379 extern void hvio_cb_resume(devhandle_t pci_dev_hdl, devhandle_t xbus_dev_hdl, 380 devino_t devino, pxu_t *pxu_p); 381 extern int px_send_pme_turnoff(caddr_t csr_base); 382 extern int px_link_wait4l1idle(caddr_t csr_base); 383 extern int px_link_retrain(caddr_t csr_base); 384 extern void px_enable_detect_quiet(caddr_t csr_base); 385 386 extern void px_lib_clr_errs(px_t *px_p); 387 388 /* 389 * Hotplug functions: 390 */ 391 extern int hvio_hotplug_init(dev_info_t *dip, void *arg); 392 extern int hvio_hotplug_uninit(dev_info_t *dip); 393 394 #ifdef __cplusplus 395 } 396 #endif 397 398 #endif /* _SYS_PX_LIB4U_H */ 399