1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/types.h> 29 #include <sys/cmn_err.h> 30 #include <sys/vmsystm.h> 31 #include <sys/vmem.h> 32 #include <sys/machsystm.h> /* lddphys() */ 33 #include <sys/iommutsb.h> 34 #include <sys/pci.h> 35 #include <sys/hotplug/pci/pciehpc.h> 36 #include <pcie_pwr.h> 37 #include <px_obj.h> 38 #include "px_regs.h" 39 #include "oberon_regs.h" 40 #include "px_csr.h" 41 #include "px_lib4u.h" 42 #include "px_err.h" 43 44 /* 45 * Registers that need to be saved and restored during suspend/resume. 46 */ 47 48 /* 49 * Registers in the PEC Module. 50 * LPU_RESET should be set to 0ull during resume 51 * 52 * This array is in reg,chip form. PX_CHIP_UNIDENTIFIED is for all chips 53 * or PX_CHIP_FIRE for Fire only, or PX_CHIP_OBERON for Oberon only. 54 */ 55 static struct px_pec_regs { 56 uint64_t reg; 57 uint64_t chip; 58 } pec_config_state_regs[] = { 59 {PEC_CORE_AND_BLOCK_INTERRUPT_ENABLE, PX_CHIP_UNIDENTIFIED}, 60 {ILU_ERROR_LOG_ENABLE, PX_CHIP_UNIDENTIFIED}, 61 {ILU_INTERRUPT_ENABLE, PX_CHIP_UNIDENTIFIED}, 62 {TLU_CONTROL, PX_CHIP_UNIDENTIFIED}, 63 {TLU_OTHER_EVENT_LOG_ENABLE, PX_CHIP_UNIDENTIFIED}, 64 {TLU_OTHER_EVENT_INTERRUPT_ENABLE, PX_CHIP_UNIDENTIFIED}, 65 {TLU_DEVICE_CONTROL, PX_CHIP_UNIDENTIFIED}, 66 {TLU_LINK_CONTROL, PX_CHIP_UNIDENTIFIED}, 67 {TLU_UNCORRECTABLE_ERROR_LOG_ENABLE, PX_CHIP_UNIDENTIFIED}, 68 {TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE, PX_CHIP_UNIDENTIFIED}, 69 {TLU_CORRECTABLE_ERROR_LOG_ENABLE, PX_CHIP_UNIDENTIFIED}, 70 {TLU_CORRECTABLE_ERROR_INTERRUPT_ENABLE, PX_CHIP_UNIDENTIFIED}, 71 {DLU_LINK_LAYER_CONFIG, PX_CHIP_OBERON}, 72 {DLU_FLOW_CONTROL_UPDATE_CONTROL, PX_CHIP_OBERON}, 73 {DLU_TXLINK_REPLAY_TIMER_THRESHOLD, PX_CHIP_OBERON}, 74 {LPU_LINK_LAYER_INTERRUPT_MASK, PX_CHIP_FIRE}, 75 {LPU_PHY_INTERRUPT_MASK, PX_CHIP_FIRE}, 76 {LPU_RECEIVE_PHY_INTERRUPT_MASK, PX_CHIP_FIRE}, 77 {LPU_TRANSMIT_PHY_INTERRUPT_MASK, PX_CHIP_FIRE}, 78 {LPU_GIGABLAZE_GLUE_INTERRUPT_MASK, PX_CHIP_FIRE}, 79 {LPU_LTSSM_INTERRUPT_MASK, PX_CHIP_FIRE}, 80 {LPU_RESET, PX_CHIP_FIRE}, 81 {LPU_DEBUG_CONFIG, PX_CHIP_FIRE}, 82 {LPU_INTERRUPT_MASK, PX_CHIP_FIRE}, 83 {LPU_LINK_LAYER_CONFIG, PX_CHIP_FIRE}, 84 {LPU_FLOW_CONTROL_UPDATE_CONTROL, PX_CHIP_FIRE}, 85 {LPU_TXLINK_FREQUENT_NAK_LATENCY_TIMER_THRESHOLD, PX_CHIP_FIRE}, 86 {LPU_TXLINK_REPLAY_TIMER_THRESHOLD, PX_CHIP_FIRE}, 87 {LPU_REPLAY_BUFFER_MAX_ADDRESS, PX_CHIP_FIRE}, 88 {LPU_TXLINK_RETRY_FIFO_POINTER, PX_CHIP_FIRE}, 89 {LPU_LTSSM_CONFIG2, PX_CHIP_FIRE}, 90 {LPU_LTSSM_CONFIG3, PX_CHIP_FIRE}, 91 {LPU_LTSSM_CONFIG4, PX_CHIP_FIRE}, 92 {LPU_LTSSM_CONFIG5, PX_CHIP_FIRE}, 93 {DMC_CORE_AND_BLOCK_INTERRUPT_ENABLE, PX_CHIP_UNIDENTIFIED}, 94 {DMC_DEBUG_SELECT_FOR_PORT_A, PX_CHIP_UNIDENTIFIED}, 95 {DMC_DEBUG_SELECT_FOR_PORT_B, PX_CHIP_UNIDENTIFIED} 96 }; 97 98 #define PEC_KEYS \ 99 ((sizeof (pec_config_state_regs))/sizeof (struct px_pec_regs)) 100 101 #define PEC_SIZE (PEC_KEYS * sizeof (uint64_t)) 102 103 /* 104 * Registers for the MMU module. 105 * MMU_TTE_CACHE_INVALIDATE needs to be cleared. (-1ull) 106 */ 107 static uint64_t mmu_config_state_regs[] = { 108 MMU_TSB_CONTROL, 109 MMU_CONTROL_AND_STATUS, 110 MMU_ERROR_LOG_ENABLE, 111 MMU_INTERRUPT_ENABLE 112 }; 113 #define MMU_SIZE (sizeof (mmu_config_state_regs)) 114 #define MMU_KEYS (MMU_SIZE / sizeof (uint64_t)) 115 116 /* 117 * Registers for the IB Module 118 */ 119 static uint64_t ib_config_state_regs[] = { 120 IMU_ERROR_LOG_ENABLE, 121 IMU_INTERRUPT_ENABLE 122 }; 123 #define IB_SIZE (sizeof (ib_config_state_regs)) 124 #define IB_KEYS (IB_SIZE / sizeof (uint64_t)) 125 #define IB_MAP_SIZE (INTERRUPT_MAPPING_ENTRIES * sizeof (uint64_t)) 126 127 /* 128 * Registers for the JBC module. 129 * JBC_ERROR_STATUS_CLEAR needs to be cleared. (-1ull) 130 */ 131 static uint64_t jbc_config_state_regs[] = { 132 JBUS_PARITY_CONTROL, 133 JBC_FATAL_RESET_ENABLE, 134 JBC_CORE_AND_BLOCK_INTERRUPT_ENABLE, 135 JBC_ERROR_LOG_ENABLE, 136 JBC_INTERRUPT_ENABLE 137 }; 138 #define JBC_SIZE (sizeof (jbc_config_state_regs)) 139 #define JBC_KEYS (JBC_SIZE / sizeof (uint64_t)) 140 141 /* 142 * Registers for the UBC module. 143 * UBC_ERROR_STATUS_CLEAR needs to be cleared. (-1ull) 144 */ 145 static uint64_t ubc_config_state_regs[] = { 146 UBC_ERROR_LOG_ENABLE, 147 UBC_INTERRUPT_ENABLE 148 }; 149 #define UBC_SIZE (sizeof (ubc_config_state_regs)) 150 #define UBC_KEYS (UBC_SIZE / sizeof (uint64_t)) 151 152 static uint64_t msiq_config_other_regs[] = { 153 ERR_COR_MAPPING, 154 ERR_NONFATAL_MAPPING, 155 ERR_FATAL_MAPPING, 156 PM_PME_MAPPING, 157 PME_TO_ACK_MAPPING, 158 MSI_32_BIT_ADDRESS, 159 MSI_64_BIT_ADDRESS 160 }; 161 #define MSIQ_OTHER_SIZE (sizeof (msiq_config_other_regs)) 162 #define MSIQ_OTHER_KEYS (MSIQ_OTHER_SIZE / sizeof (uint64_t)) 163 164 #define MSIQ_STATE_SIZE (EVENT_QUEUE_STATE_ENTRIES * sizeof (uint64_t)) 165 #define MSIQ_MAPPING_SIZE (MSI_MAPPING_ENTRIES * sizeof (uint64_t)) 166 167 /* OPL tuning variables for link unstable issue */ 168 int wait_perst = 500000; /* step 9, default: 500ms */ 169 int wait_enable_port = 45000; /* step 11, default: 45ms */ 170 int link_retry_count = 2; /* step 11, default: 2 */ 171 172 static uint64_t msiq_suspend(devhandle_t dev_hdl, pxu_t *pxu_p); 173 static void msiq_resume(devhandle_t dev_hdl, pxu_t *pxu_p); 174 static void jbc_init(caddr_t xbc_csr_base, pxu_t *pxu_p); 175 static void ubc_init(caddr_t xbc_csr_base, pxu_t *pxu_p); 176 177 /* 178 * Initialize the bus, but do not enable interrupts. 179 */ 180 /* ARGSUSED */ 181 void 182 hvio_cb_init(caddr_t xbc_csr_base, pxu_t *pxu_p) 183 { 184 switch (PX_CHIP_TYPE(pxu_p)) { 185 case PX_CHIP_OBERON: 186 ubc_init(xbc_csr_base, pxu_p); 187 break; 188 case PX_CHIP_FIRE: 189 jbc_init(xbc_csr_base, pxu_p); 190 break; 191 default: 192 DBG(DBG_CB, NULL, "hvio_cb_init - unknown chip type: 0x%x\n", 193 PX_CHIP_TYPE(pxu_p)); 194 break; 195 } 196 } 197 198 /* 199 * Initialize the JBC module, but do not enable interrupts. 200 */ 201 /* ARGSUSED */ 202 static void 203 jbc_init(caddr_t xbc_csr_base, pxu_t *pxu_p) 204 { 205 uint64_t val; 206 207 /* Check if we need to enable inverted parity */ 208 val = (1ULL << JBUS_PARITY_CONTROL_P_EN); 209 CSR_XS(xbc_csr_base, JBUS_PARITY_CONTROL, val); 210 DBG(DBG_CB, NULL, "jbc_init, JBUS_PARITY_CONTROL: 0x%llx\n", 211 CSR_XR(xbc_csr_base, JBUS_PARITY_CONTROL)); 212 213 val = (1 << JBC_FATAL_RESET_ENABLE_SPARE_P_INT_EN) | 214 (1 << JBC_FATAL_RESET_ENABLE_MB_PEA_P_INT_EN) | 215 (1 << JBC_FATAL_RESET_ENABLE_CPE_P_INT_EN) | 216 (1 << JBC_FATAL_RESET_ENABLE_APE_P_INT_EN) | 217 (1 << JBC_FATAL_RESET_ENABLE_PIO_CPE_INT_EN) | 218 (1 << JBC_FATAL_RESET_ENABLE_JTCEEW_P_INT_EN) | 219 (1 << JBC_FATAL_RESET_ENABLE_JTCEEI_P_INT_EN) | 220 (1 << JBC_FATAL_RESET_ENABLE_JTCEER_P_INT_EN); 221 CSR_XS(xbc_csr_base, JBC_FATAL_RESET_ENABLE, val); 222 DBG(DBG_CB, NULL, "jbc_init, JBC_FATAL_RESET_ENABLE: 0x%llx\n", 223 CSR_XR(xbc_csr_base, JBC_FATAL_RESET_ENABLE)); 224 225 /* 226 * Enable merge, jbc and dmc interrupts. 227 */ 228 CSR_XS(xbc_csr_base, JBC_CORE_AND_BLOCK_INTERRUPT_ENABLE, -1ull); 229 DBG(DBG_CB, NULL, 230 "jbc_init, JBC_CORE_AND_BLOCK_INTERRUPT_ENABLE: 0x%llx\n", 231 CSR_XR(xbc_csr_base, JBC_CORE_AND_BLOCK_INTERRUPT_ENABLE)); 232 233 /* 234 * CSR_V JBC's interrupt regs (log, enable, status, clear) 235 */ 236 DBG(DBG_CB, NULL, "jbc_init, JBC_ERROR_LOG_ENABLE: 0x%llx\n", 237 CSR_XR(xbc_csr_base, JBC_ERROR_LOG_ENABLE)); 238 239 DBG(DBG_CB, NULL, "jbc_init, JBC_INTERRUPT_ENABLE: 0x%llx\n", 240 CSR_XR(xbc_csr_base, JBC_INTERRUPT_ENABLE)); 241 242 DBG(DBG_CB, NULL, "jbc_init, JBC_INTERRUPT_STATUS: 0x%llx\n", 243 CSR_XR(xbc_csr_base, JBC_INTERRUPT_STATUS)); 244 245 DBG(DBG_CB, NULL, "jbc_init, JBC_ERROR_STATUS_CLEAR: 0x%llx\n", 246 CSR_XR(xbc_csr_base, JBC_ERROR_STATUS_CLEAR)); 247 } 248 249 /* 250 * Initialize the UBC module, but do not enable interrupts. 251 */ 252 /* ARGSUSED */ 253 static void 254 ubc_init(caddr_t xbc_csr_base, pxu_t *pxu_p) 255 { 256 /* 257 * Enable Uranus bus error log bits. 258 */ 259 CSR_XS(xbc_csr_base, UBC_ERROR_LOG_ENABLE, -1ull); 260 DBG(DBG_CB, NULL, "ubc_init, UBC_ERROR_LOG_ENABLE: 0x%llx\n", 261 CSR_XR(xbc_csr_base, UBC_ERROR_LOG_ENABLE)); 262 263 /* 264 * Clear Uranus bus errors. 265 */ 266 CSR_XS(xbc_csr_base, UBC_ERROR_STATUS_CLEAR, -1ull); 267 DBG(DBG_CB, NULL, "ubc_init, UBC_ERROR_STATUS_CLEAR: 0x%llx\n", 268 CSR_XR(xbc_csr_base, UBC_ERROR_STATUS_CLEAR)); 269 270 /* 271 * CSR_V UBC's interrupt regs (log, enable, status, clear) 272 */ 273 DBG(DBG_CB, NULL, "ubc_init, UBC_ERROR_LOG_ENABLE: 0x%llx\n", 274 CSR_XR(xbc_csr_base, UBC_ERROR_LOG_ENABLE)); 275 276 DBG(DBG_CB, NULL, "ubc_init, UBC_INTERRUPT_ENABLE: 0x%llx\n", 277 CSR_XR(xbc_csr_base, UBC_INTERRUPT_ENABLE)); 278 279 DBG(DBG_CB, NULL, "ubc_init, UBC_INTERRUPT_STATUS: 0x%llx\n", 280 CSR_XR(xbc_csr_base, UBC_INTERRUPT_STATUS)); 281 282 DBG(DBG_CB, NULL, "ubc_init, UBC_ERROR_STATUS_CLEAR: 0x%llx\n", 283 CSR_XR(xbc_csr_base, UBC_ERROR_STATUS_CLEAR)); 284 } 285 286 /* 287 * Initialize the module, but do not enable interrupts. 288 */ 289 /* ARGSUSED */ 290 void 291 hvio_ib_init(caddr_t csr_base, pxu_t *pxu_p) 292 { 293 /* 294 * CSR_V IB's interrupt regs (log, enable, status, clear) 295 */ 296 DBG(DBG_IB, NULL, "hvio_ib_init - IMU_ERROR_LOG_ENABLE: 0x%llx\n", 297 CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE)); 298 299 DBG(DBG_IB, NULL, "hvio_ib_init - IMU_INTERRUPT_ENABLE: 0x%llx\n", 300 CSR_XR(csr_base, IMU_INTERRUPT_ENABLE)); 301 302 DBG(DBG_IB, NULL, "hvio_ib_init - IMU_INTERRUPT_STATUS: 0x%llx\n", 303 CSR_XR(csr_base, IMU_INTERRUPT_STATUS)); 304 305 DBG(DBG_IB, NULL, "hvio_ib_init - IMU_ERROR_STATUS_CLEAR: 0x%llx\n", 306 CSR_XR(csr_base, IMU_ERROR_STATUS_CLEAR)); 307 } 308 309 /* 310 * Initialize the module, but do not enable interrupts. 311 */ 312 /* ARGSUSED */ 313 static void 314 ilu_init(caddr_t csr_base, pxu_t *pxu_p) 315 { 316 /* 317 * CSR_V ILU's interrupt regs (log, enable, status, clear) 318 */ 319 DBG(DBG_ILU, NULL, "ilu_init - ILU_ERROR_LOG_ENABLE: 0x%llx\n", 320 CSR_XR(csr_base, ILU_ERROR_LOG_ENABLE)); 321 322 DBG(DBG_ILU, NULL, "ilu_init - ILU_INTERRUPT_ENABLE: 0x%llx\n", 323 CSR_XR(csr_base, ILU_INTERRUPT_ENABLE)); 324 325 DBG(DBG_ILU, NULL, "ilu_init - ILU_INTERRUPT_STATUS: 0x%llx\n", 326 CSR_XR(csr_base, ILU_INTERRUPT_STATUS)); 327 328 DBG(DBG_ILU, NULL, "ilu_init - ILU_ERROR_STATUS_CLEAR: 0x%llx\n", 329 CSR_XR(csr_base, ILU_ERROR_STATUS_CLEAR)); 330 } 331 332 /* 333 * Initialize the module, but do not enable interrupts. 334 */ 335 /* ARGSUSED */ 336 static void 337 tlu_init(caddr_t csr_base, pxu_t *pxu_p) 338 { 339 uint64_t val; 340 341 /* 342 * CSR_V TLU_CONTROL Expect OBP ??? 343 */ 344 345 /* 346 * L0s entry default timer value - 7.0 us 347 * Completion timeout select default value - 67.1 ms and 348 * OBP will set this value. 349 * 350 * Configuration - Bit 0 should always be 0 for upstream port. 351 * Bit 1 is clock - how is this related to the clock bit in TLU 352 * Link Control register? Both are hardware dependent and likely 353 * set by OBP. 354 * 355 * NOTE: Do not set the NPWR_EN bit. The desired value of this bit 356 * will be set by OBP. 357 */ 358 val = CSR_XR(csr_base, TLU_CONTROL); 359 val |= (TLU_CONTROL_L0S_TIM_DEFAULT << TLU_CONTROL_L0S_TIM) | 360 TLU_CONTROL_CONFIG_DEFAULT; 361 362 /* 363 * For Oberon, NPWR_EN is set to 0 to prevent PIO reads from blocking 364 * behind non-posted PIO writes. This blocking could cause a master or 365 * slave timeout on the host bus if multiple serialized PIOs were to 366 * suffer Completion Timeouts because the CTO delays for each PIO ahead 367 * of the read would accumulate. Since the Olympus processor can have 368 * only 1 PIO outstanding, there is no possibility of PIO accesses from 369 * a given CPU to a given device being re-ordered by the PCIe fabric; 370 * therefore turning off serialization should be safe from a PCIe 371 * ordering perspective. 372 */ 373 if (PX_CHIP_TYPE(pxu_p) == PX_CHIP_OBERON) 374 val &= ~(1ull << TLU_CONTROL_NPWR_EN); 375 376 /* 377 * Set Detect.Quiet. This will disable automatic link 378 * re-training, if the link goes down e.g. power management 379 * turns off power to the downstream device. This will enable 380 * Fire to go to Drain state, after link down. The drain state 381 * forces a reset to the FC state machine, which is required for 382 * proper link re-training. 383 */ 384 val |= (1ull << TLU_REMAIN_DETECT_QUIET); 385 CSR_XS(csr_base, TLU_CONTROL, val); 386 DBG(DBG_TLU, NULL, "tlu_init - TLU_CONTROL: 0x%llx\n", 387 CSR_XR(csr_base, TLU_CONTROL)); 388 389 /* 390 * CSR_V TLU_STATUS Expect HW 0x4 391 */ 392 393 /* 394 * Only bit [7:0] are currently defined. Bits [2:0] 395 * are the state, which should likely be in state active, 396 * 100b. Bit three is 'recovery', which is not understood. 397 * All other bits are reserved. 398 */ 399 DBG(DBG_TLU, NULL, "tlu_init - TLU_STATUS: 0x%llx\n", 400 CSR_XR(csr_base, TLU_STATUS)); 401 402 /* 403 * CSR_V TLU_PME_TURN_OFF_GENERATE Expect HW 0x0 404 */ 405 DBG(DBG_TLU, NULL, "tlu_init - TLU_PME_TURN_OFF_GENERATE: 0x%llx\n", 406 CSR_XR(csr_base, TLU_PME_TURN_OFF_GENERATE)); 407 408 /* 409 * CSR_V TLU_INGRESS_CREDITS_INITIAL Expect HW 0x10000200C0 410 */ 411 412 /* 413 * Ingress credits initial register. Bits [39:32] should be 414 * 0x10, bits [19:12] should be 0x20, and bits [11:0] should 415 * be 0xC0. These are the reset values, and should be set by 416 * HW. 417 */ 418 DBG(DBG_TLU, NULL, "tlu_init - TLU_INGRESS_CREDITS_INITIAL: 0x%llx\n", 419 CSR_XR(csr_base, TLU_INGRESS_CREDITS_INITIAL)); 420 421 /* 422 * CSR_V TLU_DIAGNOSTIC Expect HW 0x0 423 */ 424 425 /* 426 * Diagnostic register - always zero unless we are debugging. 427 */ 428 DBG(DBG_TLU, NULL, "tlu_init - TLU_DIAGNOSTIC: 0x%llx\n", 429 CSR_XR(csr_base, TLU_DIAGNOSTIC)); 430 431 /* 432 * CSR_V TLU_EGRESS_CREDITS_CONSUMED Expect HW 0x0 433 */ 434 DBG(DBG_TLU, NULL, "tlu_init - TLU_EGRESS_CREDITS_CONSUMED: 0x%llx\n", 435 CSR_XR(csr_base, TLU_EGRESS_CREDITS_CONSUMED)); 436 437 /* 438 * CSR_V TLU_EGRESS_CREDIT_LIMIT Expect HW 0x0 439 */ 440 DBG(DBG_TLU, NULL, "tlu_init - TLU_EGRESS_CREDIT_LIMIT: 0x%llx\n", 441 CSR_XR(csr_base, TLU_EGRESS_CREDIT_LIMIT)); 442 443 /* 444 * CSR_V TLU_EGRESS_RETRY_BUFFER Expect HW 0x0 445 */ 446 DBG(DBG_TLU, NULL, "tlu_init - TLU_EGRESS_RETRY_BUFFER: 0x%llx\n", 447 CSR_XR(csr_base, TLU_EGRESS_RETRY_BUFFER)); 448 449 /* 450 * CSR_V TLU_INGRESS_CREDITS_ALLOCATED Expected HW 0x0 451 */ 452 DBG(DBG_TLU, NULL, 453 "tlu_init - TLU_INGRESS_CREDITS_ALLOCATED: 0x%llx\n", 454 CSR_XR(csr_base, TLU_INGRESS_CREDITS_ALLOCATED)); 455 456 /* 457 * CSR_V TLU_INGRESS_CREDITS_RECEIVED Expected HW 0x0 458 */ 459 DBG(DBG_TLU, NULL, 460 "tlu_init - TLU_INGRESS_CREDITS_RECEIVED: 0x%llx\n", 461 CSR_XR(csr_base, TLU_INGRESS_CREDITS_RECEIVED)); 462 463 /* 464 * CSR_V TLU's interrupt regs (log, enable, status, clear) 465 */ 466 DBG(DBG_TLU, NULL, 467 "tlu_init - TLU_OTHER_EVENT_LOG_ENABLE: 0x%llx\n", 468 CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE)); 469 470 DBG(DBG_TLU, NULL, 471 "tlu_init - TLU_OTHER_EVENT_INTERRUPT_ENABLE: 0x%llx\n", 472 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_ENABLE)); 473 474 DBG(DBG_TLU, NULL, 475 "tlu_init - TLU_OTHER_EVENT_INTERRUPT_STATUS: 0x%llx\n", 476 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_STATUS)); 477 478 DBG(DBG_TLU, NULL, 479 "tlu_init - TLU_OTHER_EVENT_STATUS_CLEAR: 0x%llx\n", 480 CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_CLEAR)); 481 482 /* 483 * CSR_V TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG Expect HW 0x0 484 */ 485 DBG(DBG_TLU, NULL, 486 "tlu_init - TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG: 0x%llx\n", 487 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG)); 488 489 /* 490 * CSR_V TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG Expect HW 0x0 491 */ 492 DBG(DBG_TLU, NULL, 493 "tlu_init - TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG: 0x%llx\n", 494 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG)); 495 496 /* 497 * CSR_V TLU_TRANSMIT_OTHER_EVENT_HEADER1_LOG Expect HW 0x0 498 */ 499 DBG(DBG_TLU, NULL, 500 "tlu_init - TLU_TRANSMIT_OTHER_EVENT_HEADER1_LOG: 0x%llx\n", 501 CSR_XR(csr_base, TLU_TRANSMIT_OTHER_EVENT_HEADER1_LOG)); 502 503 /* 504 * CSR_V TLU_TRANSMIT_OTHER_EVENT_HEADER2_LOG Expect HW 0x0 505 */ 506 DBG(DBG_TLU, NULL, 507 "tlu_init - TLU_TRANSMIT_OTHER_EVENT_HEADER2_LOG: 0x%llx\n", 508 CSR_XR(csr_base, TLU_TRANSMIT_OTHER_EVENT_HEADER2_LOG)); 509 510 /* 511 * CSR_V TLU_PERFORMANCE_COUNTER_SELECT Expect HW 0x0 512 */ 513 DBG(DBG_TLU, NULL, 514 "tlu_init - TLU_PERFORMANCE_COUNTER_SELECT: 0x%llx\n", 515 CSR_XR(csr_base, TLU_PERFORMANCE_COUNTER_SELECT)); 516 517 /* 518 * CSR_V TLU_PERFORMANCE_COUNTER_ZERO Expect HW 0x0 519 */ 520 DBG(DBG_TLU, NULL, 521 "tlu_init - TLU_PERFORMANCE_COUNTER_ZERO: 0x%llx\n", 522 CSR_XR(csr_base, TLU_PERFORMANCE_COUNTER_ZERO)); 523 524 /* 525 * CSR_V TLU_PERFORMANCE_COUNTER_ONE Expect HW 0x0 526 */ 527 DBG(DBG_TLU, NULL, "tlu_init - TLU_PERFORMANCE_COUNTER_ONE: 0x%llx\n", 528 CSR_XR(csr_base, TLU_PERFORMANCE_COUNTER_ONE)); 529 530 /* 531 * CSR_V TLU_PERFORMANCE_COUNTER_TWO Expect HW 0x0 532 */ 533 DBG(DBG_TLU, NULL, "tlu_init - TLU_PERFORMANCE_COUNTER_TWO: 0x%llx\n", 534 CSR_XR(csr_base, TLU_PERFORMANCE_COUNTER_TWO)); 535 536 /* 537 * CSR_V TLU_DEBUG_SELECT_A Expect HW 0x0 538 */ 539 540 DBG(DBG_TLU, NULL, "tlu_init - TLU_DEBUG_SELECT_A: 0x%llx\n", 541 CSR_XR(csr_base, TLU_DEBUG_SELECT_A)); 542 543 /* 544 * CSR_V TLU_DEBUG_SELECT_B Expect HW 0x0 545 */ 546 DBG(DBG_TLU, NULL, "tlu_init - TLU_DEBUG_SELECT_B: 0x%llx\n", 547 CSR_XR(csr_base, TLU_DEBUG_SELECT_B)); 548 549 /* 550 * CSR_V TLU_DEVICE_CAPABILITIES Expect HW 0xFC2 551 */ 552 DBG(DBG_TLU, NULL, "tlu_init - TLU_DEVICE_CAPABILITIES: 0x%llx\n", 553 CSR_XR(csr_base, TLU_DEVICE_CAPABILITIES)); 554 555 /* 556 * CSR_V TLU_DEVICE_CONTROL Expect HW 0x0 557 */ 558 559 /* 560 * Bits [14:12] are the Max Read Request Size, which is always 64 561 * bytes which is 000b. Bits [7:5] are Max Payload Size, which 562 * start at 128 bytes which is 000b. This may be revisited if 563 * init_child finds greater values. 564 */ 565 val = 0x0ull; 566 CSR_XS(csr_base, TLU_DEVICE_CONTROL, val); 567 DBG(DBG_TLU, NULL, "tlu_init - TLU_DEVICE_CONTROL: 0x%llx\n", 568 CSR_XR(csr_base, TLU_DEVICE_CONTROL)); 569 570 /* 571 * CSR_V TLU_DEVICE_STATUS Expect HW 0x0 572 */ 573 DBG(DBG_TLU, NULL, "tlu_init - TLU_DEVICE_STATUS: 0x%llx\n", 574 CSR_XR(csr_base, TLU_DEVICE_STATUS)); 575 576 /* 577 * CSR_V TLU_LINK_CAPABILITIES Expect HW 0x15C81 578 */ 579 DBG(DBG_TLU, NULL, "tlu_init - TLU_LINK_CAPABILITIES: 0x%llx\n", 580 CSR_XR(csr_base, TLU_LINK_CAPABILITIES)); 581 582 /* 583 * CSR_V TLU_LINK_CONTROL Expect OBP 0x40 584 */ 585 586 /* 587 * The CLOCK bit should be set by OBP if the hardware dictates, 588 * and if it is set then ASPM should be used since then L0s exit 589 * latency should be lower than L1 exit latency. 590 * 591 * Note that we will not enable power management during bringup 592 * since it has not been test and is creating some problems in 593 * simulation. 594 */ 595 val = (1ull << TLU_LINK_CONTROL_CLOCK); 596 597 CSR_XS(csr_base, TLU_LINK_CONTROL, val); 598 DBG(DBG_TLU, NULL, "tlu_init - TLU_LINK_CONTROL: 0x%llx\n", 599 CSR_XR(csr_base, TLU_LINK_CONTROL)); 600 601 /* 602 * CSR_V TLU_LINK_STATUS Expect OBP 0x1011 603 */ 604 605 /* 606 * Not sure if HW or OBP will be setting this read only 607 * register. Bit 12 is Clock, and it should always be 1 608 * signifying that the component uses the same physical 609 * clock as the platform. Bits [9:4] are for the width, 610 * with the expected value above signifying a x1 width. 611 * Bits [3:0] are the speed, with 1b signifying 2.5 Gb/s, 612 * the only speed as yet supported by the PCI-E spec. 613 */ 614 DBG(DBG_TLU, NULL, "tlu_init - TLU_LINK_STATUS: 0x%llx\n", 615 CSR_XR(csr_base, TLU_LINK_STATUS)); 616 617 /* 618 * CSR_V TLU_SLOT_CAPABILITIES Expect OBP ??? 619 */ 620 621 /* 622 * Power Limits for the slots. Will be platform 623 * dependent, and OBP will need to set after consulting 624 * with the HW guys. 625 * 626 * Bits [16:15] are power limit scale, which most likely 627 * will be 0b signifying 1x. Bits [14:7] are the Set 628 * Power Limit Value, which is a number which is multiplied 629 * by the power limit scale to get the actual power limit. 630 */ 631 DBG(DBG_TLU, NULL, "tlu_init - TLU_SLOT_CAPABILITIES: 0x%llx\n", 632 CSR_XR(csr_base, TLU_SLOT_CAPABILITIES)); 633 634 /* 635 * CSR_V TLU_UNCORRECTABLE_ERROR_LOG_ENABLE Expect Kernel 0x17F011 636 */ 637 DBG(DBG_TLU, NULL, 638 "tlu_init - TLU_UNCORRECTABLE_ERROR_LOG_ENABLE: 0x%llx\n", 639 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE)); 640 641 /* 642 * CSR_V TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE Expect 643 * Kernel 0x17F0110017F011 644 */ 645 DBG(DBG_TLU, NULL, 646 "tlu_init - TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE: 0x%llx\n", 647 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE)); 648 649 /* 650 * CSR_V TLU_UNCORRECTABLE_ERROR_INTERRUPT_STATUS Expect HW 0x0 651 */ 652 DBG(DBG_TLU, NULL, 653 "tlu_init - TLU_UNCORRECTABLE_ERROR_INTERRUPT_STATUS: 0x%llx\n", 654 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_STATUS)); 655 656 /* 657 * CSR_V TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR Expect HW 0x0 658 */ 659 DBG(DBG_TLU, NULL, 660 "tlu_init - TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR: 0x%llx\n", 661 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR)); 662 663 /* 664 * CSR_V TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER1_LOG HW 0x0 665 */ 666 DBG(DBG_TLU, NULL, 667 "tlu_init - TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER1_LOG: 0x%llx\n", 668 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER1_LOG)); 669 670 /* 671 * CSR_V TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER2_LOG HW 0x0 672 */ 673 DBG(DBG_TLU, NULL, 674 "tlu_init - TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER2_LOG: 0x%llx\n", 675 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER2_LOG)); 676 677 /* 678 * CSR_V TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER1_LOG HW 0x0 679 */ 680 DBG(DBG_TLU, NULL, 681 "tlu_init - TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER1_LOG: 0x%llx\n", 682 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER1_LOG)); 683 684 /* 685 * CSR_V TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER2_LOG HW 0x0 686 */ 687 DBG(DBG_TLU, NULL, 688 "tlu_init - TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER2_LOG: 0x%llx\n", 689 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER2_LOG)); 690 691 692 /* 693 * CSR_V TLU's CE interrupt regs (log, enable, status, clear) 694 * Plus header logs 695 */ 696 697 /* 698 * CSR_V TLU_CORRECTABLE_ERROR_LOG_ENABLE Expect Kernel 0x11C1 699 */ 700 DBG(DBG_TLU, NULL, 701 "tlu_init - TLU_CORRECTABLE_ERROR_LOG_ENABLE: 0x%llx\n", 702 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_LOG_ENABLE)); 703 704 /* 705 * CSR_V TLU_CORRECTABLE_ERROR_INTERRUPT_ENABLE Kernel 0x11C1000011C1 706 */ 707 DBG(DBG_TLU, NULL, 708 "tlu_init - TLU_CORRECTABLE_ERROR_INTERRUPT_ENABLE: 0x%llx\n", 709 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_INTERRUPT_ENABLE)); 710 711 /* 712 * CSR_V TLU_CORRECTABLE_ERROR_INTERRUPT_STATUS Expect HW 0x0 713 */ 714 DBG(DBG_TLU, NULL, 715 "tlu_init - TLU_CORRECTABLE_ERROR_INTERRUPT_STATUS: 0x%llx\n", 716 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_INTERRUPT_STATUS)); 717 718 /* 719 * CSR_V TLU_CORRECTABLE_ERROR_STATUS_CLEAR Expect HW 0x0 720 */ 721 DBG(DBG_TLU, NULL, 722 "tlu_init - TLU_CORRECTABLE_ERROR_STATUS_CLEAR: 0x%llx\n", 723 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_STATUS_CLEAR)); 724 } 725 726 /* ARGSUSED */ 727 static void 728 lpu_init(caddr_t csr_base, pxu_t *pxu_p) 729 { 730 /* Variables used to set the ACKNAK Latency Timer and Replay Timer */ 731 int link_width, max_payload; 732 733 uint64_t val; 734 735 /* 736 * ACKNAK Latency Threshold Table. 737 * See Fire PRM 2.0 section 1.2.12.2, table 1-17. 738 */ 739 int acknak_timer_table[LINK_MAX_PKT_ARR_SIZE][LINK_WIDTH_ARR_SIZE] = { 740 {0xED, 0x49, 0x43, 0x30}, 741 {0x1A0, 0x76, 0x6B, 0x48}, 742 {0x22F, 0x9A, 0x56, 0x56}, 743 {0x42F, 0x11A, 0x96, 0x96}, 744 {0x82F, 0x21A, 0x116, 0x116}, 745 {0x102F, 0x41A, 0x216, 0x216} 746 }; 747 748 /* 749 * TxLink Replay Timer Latency Table 750 * See Fire PRM 2.0 sections 1.2.12.3, table 1-18. 751 */ 752 int replay_timer_table[LINK_MAX_PKT_ARR_SIZE][LINK_WIDTH_ARR_SIZE] = { 753 {0x379, 0x112, 0xFC, 0xB4}, 754 {0x618, 0x1BA, 0x192, 0x10E}, 755 {0x831, 0x242, 0x143, 0x143}, 756 {0xFB1, 0x422, 0x233, 0x233}, 757 {0x1EB0, 0x7E1, 0x412, 0x412}, 758 {0x3CB0, 0xF61, 0x7D2, 0x7D2} 759 }; 760 761 /* 762 * Get the Link Width. See table above LINK_WIDTH_ARR_SIZE #define 763 * Only Link Widths of x1, x4, and x8 are supported. 764 * If any width is reported other than x8, set default to x8. 765 */ 766 link_width = CSR_FR(csr_base, TLU_LINK_STATUS, WIDTH); 767 DBG(DBG_LPU, NULL, "lpu_init - Link Width: x%d\n", link_width); 768 769 /* 770 * Convert link_width to match timer array configuration. 771 */ 772 switch (link_width) { 773 case 1: 774 link_width = 0; 775 break; 776 case 4: 777 link_width = 1; 778 break; 779 case 8: 780 link_width = 2; 781 break; 782 case 16: 783 link_width = 3; 784 break; 785 default: 786 link_width = 0; 787 } 788 789 /* 790 * Get the Max Payload Size. 791 * See table above LINK_MAX_PKT_ARR_SIZE #define 792 */ 793 max_payload = ((CSR_FR(csr_base, TLU_CONTROL, CONFIG) & 794 TLU_CONTROL_MPS_MASK) >> TLU_CONTROL_MPS_SHIFT); 795 796 DBG(DBG_LPU, NULL, "lpu_init - May Payload: %d\n", 797 (0x80 << max_payload)); 798 799 /* Make sure the packet size is not greater than 4096 */ 800 max_payload = (max_payload >= LINK_MAX_PKT_ARR_SIZE) ? 801 (LINK_MAX_PKT_ARR_SIZE - 1) : max_payload; 802 803 /* 804 * CSR_V LPU_ID Expect HW 0x0 805 */ 806 807 /* 808 * This register has link id, phy id and gigablaze id. 809 * Should be set by HW. 810 */ 811 DBG(DBG_LPU, NULL, "lpu_init - LPU_ID: 0x%llx\n", 812 CSR_XR(csr_base, LPU_ID)); 813 814 /* 815 * CSR_V LPU_RESET Expect Kernel 0x0 816 */ 817 818 /* 819 * No reason to have any reset bits high until an error is 820 * detected on the link. 821 */ 822 val = 0ull; 823 CSR_XS(csr_base, LPU_RESET, val); 824 DBG(DBG_LPU, NULL, "lpu_init - LPU_RESET: 0x%llx\n", 825 CSR_XR(csr_base, LPU_RESET)); 826 827 /* 828 * CSR_V LPU_DEBUG_STATUS Expect HW 0x0 829 */ 830 831 /* 832 * Bits [15:8] are Debug B, and bit [7:0] are Debug A. 833 * They are read-only. What do the 8 bits mean, and 834 * how do they get set if they are read only? 835 */ 836 DBG(DBG_LPU, NULL, "lpu_init - LPU_DEBUG_STATUS: 0x%llx\n", 837 CSR_XR(csr_base, LPU_DEBUG_STATUS)); 838 839 /* 840 * CSR_V LPU_DEBUG_CONFIG Expect Kernel 0x0 841 */ 842 DBG(DBG_LPU, NULL, "lpu_init - LPU_DEBUG_CONFIG: 0x%llx\n", 843 CSR_XR(csr_base, LPU_DEBUG_CONFIG)); 844 845 /* 846 * CSR_V LPU_LTSSM_CONTROL Expect HW 0x0 847 */ 848 DBG(DBG_LPU, NULL, "lpu_init - LPU_LTSSM_CONTROL: 0x%llx\n", 849 CSR_XR(csr_base, LPU_LTSSM_CONTROL)); 850 851 /* 852 * CSR_V LPU_LINK_STATUS Expect HW 0x101 853 */ 854 855 /* 856 * This register has bits [9:4] for link width, and the 857 * default 0x10, means a width of x16. The problem is 858 * this width is not supported according to the TLU 859 * link status register. 860 */ 861 DBG(DBG_LPU, NULL, "lpu_init - LPU_LINK_STATUS: 0x%llx\n", 862 CSR_XR(csr_base, LPU_LINK_STATUS)); 863 864 /* 865 * CSR_V LPU_INTERRUPT_STATUS Expect HW 0x0 866 */ 867 DBG(DBG_LPU, NULL, "lpu_init - LPU_INTERRUPT_STATUS: 0x%llx\n", 868 CSR_XR(csr_base, LPU_INTERRUPT_STATUS)); 869 870 /* 871 * CSR_V LPU_INTERRUPT_MASK Expect HW 0x0 872 */ 873 DBG(DBG_LPU, NULL, "lpu_init - LPU_INTERRUPT_MASK: 0x%llx\n", 874 CSR_XR(csr_base, LPU_INTERRUPT_MASK)); 875 876 /* 877 * CSR_V LPU_LINK_PERFORMANCE_COUNTER_SELECT Expect HW 0x0 878 */ 879 DBG(DBG_LPU, NULL, 880 "lpu_init - LPU_LINK_PERFORMANCE_COUNTER_SELECT: 0x%llx\n", 881 CSR_XR(csr_base, LPU_LINK_PERFORMANCE_COUNTER_SELECT)); 882 883 /* 884 * CSR_V LPU_LINK_PERFORMANCE_COUNTER_CONTROL Expect HW 0x0 885 */ 886 DBG(DBG_LPU, NULL, 887 "lpu_init - LPU_LINK_PERFORMANCE_COUNTER_CONTROL: 0x%llx\n", 888 CSR_XR(csr_base, LPU_LINK_PERFORMANCE_COUNTER_CONTROL)); 889 890 /* 891 * CSR_V LPU_LINK_PERFORMANCE_COUNTER1 Expect HW 0x0 892 */ 893 DBG(DBG_LPU, NULL, 894 "lpu_init - LPU_LINK_PERFORMANCE_COUNTER1: 0x%llx\n", 895 CSR_XR(csr_base, LPU_LINK_PERFORMANCE_COUNTER1)); 896 897 /* 898 * CSR_V LPU_LINK_PERFORMANCE_COUNTER1_TEST Expect HW 0x0 899 */ 900 DBG(DBG_LPU, NULL, 901 "lpu_init - LPU_LINK_PERFORMANCE_COUNTER1_TEST: 0x%llx\n", 902 CSR_XR(csr_base, LPU_LINK_PERFORMANCE_COUNTER1_TEST)); 903 904 /* 905 * CSR_V LPU_LINK_PERFORMANCE_COUNTER2 Expect HW 0x0 906 */ 907 DBG(DBG_LPU, NULL, 908 "lpu_init - LPU_LINK_PERFORMANCE_COUNTER2: 0x%llx\n", 909 CSR_XR(csr_base, LPU_LINK_PERFORMANCE_COUNTER2)); 910 911 /* 912 * CSR_V LPU_LINK_PERFORMANCE_COUNTER2_TEST Expect HW 0x0 913 */ 914 DBG(DBG_LPU, NULL, 915 "lpu_init - LPU_LINK_PERFORMANCE_COUNTER2_TEST: 0x%llx\n", 916 CSR_XR(csr_base, LPU_LINK_PERFORMANCE_COUNTER2_TEST)); 917 918 /* 919 * CSR_V LPU_LINK_LAYER_CONFIG Expect HW 0x100 920 */ 921 922 /* 923 * This is another place where Max Payload can be set, 924 * this time for the link layer. It will be set to 925 * 128B, which is the default, but this will need to 926 * be revisited. 927 */ 928 val = (1ull << LPU_LINK_LAYER_CONFIG_VC0_EN); 929 CSR_XS(csr_base, LPU_LINK_LAYER_CONFIG, val); 930 DBG(DBG_LPU, NULL, "lpu_init - LPU_LINK_LAYER_CONFIG: 0x%llx\n", 931 CSR_XR(csr_base, LPU_LINK_LAYER_CONFIG)); 932 933 /* 934 * CSR_V LPU_LINK_LAYER_STATUS Expect OBP 0x5 935 */ 936 937 /* 938 * Another R/W status register. Bit 3, DL up Status, will 939 * be set high. The link state machine status bits [2:0] 940 * are set to 0x1, but the status bits are not defined in the 941 * PRM. What does 0x1 mean, what others values are possible 942 * and what are thier meanings? 943 * 944 * This register has been giving us problems in simulation. 945 * It has been mentioned that software should not program 946 * any registers with WE bits except during debug. So 947 * this register will no longer be programmed. 948 */ 949 950 DBG(DBG_LPU, NULL, "lpu_init - LPU_LINK_LAYER_STATUS: 0x%llx\n", 951 CSR_XR(csr_base, LPU_LINK_LAYER_STATUS)); 952 953 /* 954 * CSR_V LPU_LINK_LAYER_INTERRUPT_AND_STATUS_TEST Expect HW 0x0 955 */ 956 DBG(DBG_LPU, NULL, 957 "lpu_init - LPU_LINK_LAYER_INTERRUPT_AND_STATUS_TEST: 0x%llx\n", 958 CSR_XR(csr_base, LPU_LINK_LAYER_INTERRUPT_AND_STATUS_TEST)); 959 960 /* 961 * CSR_V LPU Link Layer interrupt regs (mask, status) 962 */ 963 DBG(DBG_LPU, NULL, 964 "lpu_init - LPU_LINK_LAYER_INTERRUPT_MASK: 0x%llx\n", 965 CSR_XR(csr_base, LPU_LINK_LAYER_INTERRUPT_MASK)); 966 967 DBG(DBG_LPU, NULL, 968 "lpu_init - LPU_LINK_LAYER_INTERRUPT_AND_STATUS: 0x%llx\n", 969 CSR_XR(csr_base, LPU_LINK_LAYER_INTERRUPT_AND_STATUS)); 970 971 /* 972 * CSR_V LPU_FLOW_CONTROL_UPDATE_CONTROL Expect OBP 0x7 973 */ 974 975 /* 976 * The PRM says that only the first two bits will be set 977 * high by default, which will enable flow control for 978 * posted and non-posted updates, but NOT completetion 979 * updates. 980 */ 981 val = (1ull << LPU_FLOW_CONTROL_UPDATE_CONTROL_FC0_U_NP_EN) | 982 (1ull << LPU_FLOW_CONTROL_UPDATE_CONTROL_FC0_U_P_EN); 983 CSR_XS(csr_base, LPU_FLOW_CONTROL_UPDATE_CONTROL, val); 984 DBG(DBG_LPU, NULL, 985 "lpu_init - LPU_FLOW_CONTROL_UPDATE_CONTROL: 0x%llx\n", 986 CSR_XR(csr_base, LPU_FLOW_CONTROL_UPDATE_CONTROL)); 987 988 /* 989 * CSR_V LPU_LINK_LAYER_FLOW_CONTROL_UPDATE_TIMEOUT_VALUE 990 * Expect OBP 0x1D4C 991 */ 992 993 /* 994 * This should be set by OBP. We'll check to make sure. 995 */ 996 DBG(DBG_LPU, NULL, "lpu_init - " 997 "LPU_LINK_LAYER_FLOW_CONTROL_UPDATE_TIMEOUT_VALUE: 0x%llx\n", 998 CSR_XR(csr_base, 999 LPU_LINK_LAYER_FLOW_CONTROL_UPDATE_TIMEOUT_VALUE)); 1000 1001 /* 1002 * CSR_V LPU_LINK_LAYER_VC0_FLOW_CONTROL_UPDATE_TIMER0 Expect OBP ??? 1003 */ 1004 1005 /* 1006 * This register has Flow Control Update Timer values for 1007 * non-posted and posted requests, bits [30:16] and bits 1008 * [14:0], respectively. These are read-only to SW so 1009 * either HW or OBP needs to set them. 1010 */ 1011 DBG(DBG_LPU, NULL, "lpu_init - " 1012 "LPU_LINK_LAYER_VC0_FLOW_CONTROL_UPDATE_TIMER0: 0x%llx\n", 1013 CSR_XR(csr_base, 1014 LPU_LINK_LAYER_VC0_FLOW_CONTROL_UPDATE_TIMER0)); 1015 1016 /* 1017 * CSR_V LPU_LINK_LAYER_VC0_FLOW_CONTROL_UPDATE_TIMER1 Expect OBP ??? 1018 */ 1019 1020 /* 1021 * Same as timer0 register above, except for bits [14:0] 1022 * have the timer values for completetions. Read-only to 1023 * SW; OBP or HW need to set it. 1024 */ 1025 DBG(DBG_LPU, NULL, "lpu_init - " 1026 "LPU_LINK_LAYER_VC0_FLOW_CONTROL_UPDATE_TIMER1: 0x%llx\n", 1027 CSR_XR(csr_base, 1028 LPU_LINK_LAYER_VC0_FLOW_CONTROL_UPDATE_TIMER1)); 1029 1030 /* 1031 * CSR_V LPU_TXLINK_FREQUENT_NAK_LATENCY_TIMER_THRESHOLD 1032 */ 1033 val = acknak_timer_table[max_payload][link_width]; 1034 CSR_XS(csr_base, LPU_TXLINK_FREQUENT_NAK_LATENCY_TIMER_THRESHOLD, val); 1035 1036 DBG(DBG_LPU, NULL, "lpu_init - " 1037 "LPU_TXLINK_FREQUENT_NAK_LATENCY_TIMER_THRESHOLD: 0x%llx\n", 1038 CSR_XR(csr_base, LPU_TXLINK_FREQUENT_NAK_LATENCY_TIMER_THRESHOLD)); 1039 1040 /* 1041 * CSR_V LPU_TXLINK_ACKNAK_LATENCY_TIMER Expect HW 0x0 1042 */ 1043 DBG(DBG_LPU, NULL, 1044 "lpu_init - LPU_TXLINK_ACKNAK_LATENCY_TIMER: 0x%llx\n", 1045 CSR_XR(csr_base, LPU_TXLINK_ACKNAK_LATENCY_TIMER)); 1046 1047 /* 1048 * CSR_V LPU_TXLINK_REPLAY_TIMER_THRESHOLD 1049 */ 1050 val = replay_timer_table[max_payload][link_width]; 1051 CSR_XS(csr_base, LPU_TXLINK_REPLAY_TIMER_THRESHOLD, val); 1052 1053 DBG(DBG_LPU, NULL, 1054 "lpu_init - LPU_TXLINK_REPLAY_TIMER_THRESHOLD: 0x%llx\n", 1055 CSR_XR(csr_base, LPU_TXLINK_REPLAY_TIMER_THRESHOLD)); 1056 1057 /* 1058 * CSR_V LPU_TXLINK_REPLAY_TIMER Expect HW 0x0 1059 */ 1060 DBG(DBG_LPU, NULL, "lpu_init - LPU_TXLINK_REPLAY_TIMER: 0x%llx\n", 1061 CSR_XR(csr_base, LPU_TXLINK_REPLAY_TIMER)); 1062 1063 /* 1064 * CSR_V LPU_TXLINK_REPLAY_NUMBER_STATUS Expect OBP 0x3 1065 */ 1066 DBG(DBG_LPU, NULL, 1067 "lpu_init - LPU_TXLINK_REPLAY_NUMBER_STATUS: 0x%llx\n", 1068 CSR_XR(csr_base, LPU_TXLINK_REPLAY_NUMBER_STATUS)); 1069 1070 /* 1071 * CSR_V LPU_REPLAY_BUFFER_MAX_ADDRESS Expect OBP 0xB3F 1072 */ 1073 DBG(DBG_LPU, NULL, 1074 "lpu_init - LPU_REPLAY_BUFFER_MAX_ADDRESS: 0x%llx\n", 1075 CSR_XR(csr_base, LPU_REPLAY_BUFFER_MAX_ADDRESS)); 1076 1077 /* 1078 * CSR_V LPU_TXLINK_RETRY_FIFO_POINTER Expect OBP 0xFFFF0000 1079 */ 1080 val = ((LPU_TXLINK_RETRY_FIFO_POINTER_RTRY_FIFO_TLPTR_DEFAULT << 1081 LPU_TXLINK_RETRY_FIFO_POINTER_RTRY_FIFO_TLPTR) | 1082 (LPU_TXLINK_RETRY_FIFO_POINTER_RTRY_FIFO_HDPTR_DEFAULT << 1083 LPU_TXLINK_RETRY_FIFO_POINTER_RTRY_FIFO_HDPTR)); 1084 1085 CSR_XS(csr_base, LPU_TXLINK_RETRY_FIFO_POINTER, val); 1086 DBG(DBG_LPU, NULL, 1087 "lpu_init - LPU_TXLINK_RETRY_FIFO_POINTER: 0x%llx\n", 1088 CSR_XR(csr_base, LPU_TXLINK_RETRY_FIFO_POINTER)); 1089 1090 /* 1091 * CSR_V LPU_TXLINK_RETRY_FIFO_R_W_POINTER Expect OBP 0x0 1092 */ 1093 DBG(DBG_LPU, NULL, 1094 "lpu_init - LPU_TXLINK_RETRY_FIFO_R_W_POINTER: 0x%llx\n", 1095 CSR_XR(csr_base, LPU_TXLINK_RETRY_FIFO_R_W_POINTER)); 1096 1097 /* 1098 * CSR_V LPU_TXLINK_RETRY_FIFO_CREDIT Expect HW 0x1580 1099 */ 1100 DBG(DBG_LPU, NULL, 1101 "lpu_init - LPU_TXLINK_RETRY_FIFO_CREDIT: 0x%llx\n", 1102 CSR_XR(csr_base, LPU_TXLINK_RETRY_FIFO_CREDIT)); 1103 1104 /* 1105 * CSR_V LPU_TXLINK_SEQUENCE_COUNTER Expect OBP 0xFFF0000 1106 */ 1107 DBG(DBG_LPU, NULL, "lpu_init - LPU_TXLINK_SEQUENCE_COUNTER: 0x%llx\n", 1108 CSR_XR(csr_base, LPU_TXLINK_SEQUENCE_COUNTER)); 1109 1110 /* 1111 * CSR_V LPU_TXLINK_ACK_SENT_SEQUENCE_NUMBER Expect HW 0xFFF 1112 */ 1113 DBG(DBG_LPU, NULL, 1114 "lpu_init - LPU_TXLINK_ACK_SENT_SEQUENCE_NUMBER: 0x%llx\n", 1115 CSR_XR(csr_base, LPU_TXLINK_ACK_SENT_SEQUENCE_NUMBER)); 1116 1117 /* 1118 * CSR_V LPU_TXLINK_SEQUENCE_COUNT_FIFO_MAX_ADDR Expect OBP 0x157 1119 */ 1120 1121 /* 1122 * Test only register. Will not be programmed. 1123 */ 1124 DBG(DBG_LPU, NULL, 1125 "lpu_init - LPU_TXLINK_SEQUENCE_COUNT_FIFO_MAX_ADDR: 0x%llx\n", 1126 CSR_XR(csr_base, LPU_TXLINK_SEQUENCE_COUNT_FIFO_MAX_ADDR)); 1127 1128 /* 1129 * CSR_V LPU_TXLINK_SEQUENCE_COUNT_FIFO_POINTERS Expect HW 0xFFF0000 1130 */ 1131 1132 /* 1133 * Test only register. Will not be programmed. 1134 */ 1135 DBG(DBG_LPU, NULL, 1136 "lpu_init - LPU_TXLINK_SEQUENCE_COUNT_FIFO_POINTERS: 0x%llx\n", 1137 CSR_XR(csr_base, LPU_TXLINK_SEQUENCE_COUNT_FIFO_POINTERS)); 1138 1139 /* 1140 * CSR_V LPU_TXLINK_SEQUENCE_COUNT_R_W_POINTERS Expect HW 0x0 1141 */ 1142 DBG(DBG_LPU, NULL, 1143 "lpu_init - LPU_TXLINK_SEQUENCE_COUNT_R_W_POINTERS: 0x%llx\n", 1144 CSR_XR(csr_base, LPU_TXLINK_SEQUENCE_COUNT_R_W_POINTERS)); 1145 1146 /* 1147 * CSR_V LPU_TXLINK_TEST_CONTROL Expect HW 0x0 1148 */ 1149 DBG(DBG_LPU, NULL, "lpu_init - LPU_TXLINK_TEST_CONTROL: 0x%llx\n", 1150 CSR_XR(csr_base, LPU_TXLINK_TEST_CONTROL)); 1151 1152 /* 1153 * CSR_V LPU_TXLINK_MEMORY_ADDRESS_CONTROL Expect HW 0x0 1154 */ 1155 1156 /* 1157 * Test only register. Will not be programmed. 1158 */ 1159 DBG(DBG_LPU, NULL, 1160 "lpu_init - LPU_TXLINK_MEMORY_ADDRESS_CONTROL: 0x%llx\n", 1161 CSR_XR(csr_base, LPU_TXLINK_MEMORY_ADDRESS_CONTROL)); 1162 1163 /* 1164 * CSR_V LPU_TXLINK_MEMORY_DATA_LOAD0 Expect HW 0x0 1165 */ 1166 DBG(DBG_LPU, NULL, 1167 "lpu_init - LPU_TXLINK_MEMORY_DATA_LOAD0: 0x%llx\n", 1168 CSR_XR(csr_base, LPU_TXLINK_MEMORY_DATA_LOAD0)); 1169 1170 /* 1171 * CSR_V LPU_TXLINK_MEMORY_DATA_LOAD1 Expect HW 0x0 1172 */ 1173 DBG(DBG_LPU, NULL, 1174 "lpu_init - LPU_TXLINK_MEMORY_DATA_LOAD1: 0x%llx\n", 1175 CSR_XR(csr_base, LPU_TXLINK_MEMORY_DATA_LOAD1)); 1176 1177 /* 1178 * CSR_V LPU_TXLINK_MEMORY_DATA_LOAD2 Expect HW 0x0 1179 */ 1180 DBG(DBG_LPU, NULL, 1181 "lpu_init - LPU_TXLINK_MEMORY_DATA_LOAD2: 0x%llx\n", 1182 CSR_XR(csr_base, LPU_TXLINK_MEMORY_DATA_LOAD2)); 1183 1184 /* 1185 * CSR_V LPU_TXLINK_MEMORY_DATA_LOAD3 Expect HW 0x0 1186 */ 1187 DBG(DBG_LPU, NULL, 1188 "lpu_init - LPU_TXLINK_MEMORY_DATA_LOAD3: 0x%llx\n", 1189 CSR_XR(csr_base, LPU_TXLINK_MEMORY_DATA_LOAD3)); 1190 1191 /* 1192 * CSR_V LPU_TXLINK_MEMORY_DATA_LOAD4 Expect HW 0x0 1193 */ 1194 DBG(DBG_LPU, NULL, 1195 "lpu_init - LPU_TXLINK_MEMORY_DATA_LOAD4: 0x%llx\n", 1196 CSR_XR(csr_base, LPU_TXLINK_MEMORY_DATA_LOAD4)); 1197 1198 /* 1199 * CSR_V LPU_TXLINK_RETRY_DATA_COUNT Expect HW 0x0 1200 */ 1201 1202 /* 1203 * Test only register. Will not be programmed. 1204 */ 1205 DBG(DBG_LPU, NULL, "lpu_init - LPU_TXLINK_RETRY_DATA_COUNT: 0x%llx\n", 1206 CSR_XR(csr_base, LPU_TXLINK_RETRY_DATA_COUNT)); 1207 1208 /* 1209 * CSR_V LPU_TXLINK_SEQUENCE_BUFFER_COUNT Expect HW 0x0 1210 */ 1211 1212 /* 1213 * Test only register. Will not be programmed. 1214 */ 1215 DBG(DBG_LPU, NULL, 1216 "lpu_init - LPU_TXLINK_SEQUENCE_BUFFER_COUNT: 0x%llx\n", 1217 CSR_XR(csr_base, LPU_TXLINK_SEQUENCE_BUFFER_COUNT)); 1218 1219 /* 1220 * CSR_V LPU_TXLINK_SEQUENCE_BUFFER_BOTTOM_DATA Expect HW 0x0 1221 */ 1222 1223 /* 1224 * Test only register. 1225 */ 1226 DBG(DBG_LPU, NULL, 1227 "lpu_init - LPU_TXLINK_SEQUENCE_BUFFER_BOTTOM_DATA: 0x%llx\n", 1228 CSR_XR(csr_base, LPU_TXLINK_SEQUENCE_BUFFER_BOTTOM_DATA)); 1229 1230 /* 1231 * CSR_V LPU_RXLINK_NEXT_RECEIVE_SEQUENCE_1_COUNTER Expect HW 0x0 1232 */ 1233 DBG(DBG_LPU, NULL, "lpu_init - " 1234 "LPU_RXLINK_NEXT_RECEIVE_SEQUENCE_1_COUNTER: 0x%llx\n", 1235 CSR_XR(csr_base, LPU_RXLINK_NEXT_RECEIVE_SEQUENCE_1_COUNTER)); 1236 1237 /* 1238 * CSR_V LPU_RXLINK_UNSUPPORTED_DLLP_RECEIVED Expect HW 0x0 1239 */ 1240 1241 /* 1242 * test only register. 1243 */ 1244 DBG(DBG_LPU, NULL, 1245 "lpu_init - LPU_RXLINK_UNSUPPORTED_DLLP_RECEIVED: 0x%llx\n", 1246 CSR_XR(csr_base, LPU_RXLINK_UNSUPPORTED_DLLP_RECEIVED)); 1247 1248 /* 1249 * CSR_V LPU_RXLINK_TEST_CONTROL Expect HW 0x0 1250 */ 1251 1252 /* 1253 * test only register. 1254 */ 1255 DBG(DBG_LPU, NULL, "lpu_init - LPU_RXLINK_TEST_CONTROL: 0x%llx\n", 1256 CSR_XR(csr_base, LPU_RXLINK_TEST_CONTROL)); 1257 1258 /* 1259 * CSR_V LPU_PHYSICAL_LAYER_CONFIGURATION Expect HW 0x10 1260 */ 1261 DBG(DBG_LPU, NULL, 1262 "lpu_init - LPU_PHYSICAL_LAYER_CONFIGURATION: 0x%llx\n", 1263 CSR_XR(csr_base, LPU_PHYSICAL_LAYER_CONFIGURATION)); 1264 1265 /* 1266 * CSR_V LPU_PHY_LAYER_STATUS Expect HW 0x0 1267 */ 1268 DBG(DBG_LPU, NULL, "lpu_init - LPU_PHY_LAYER_STATUS: 0x%llx\n", 1269 CSR_XR(csr_base, LPU_PHY_LAYER_STATUS)); 1270 1271 /* 1272 * CSR_V LPU_PHY_INTERRUPT_AND_STATUS_TEST Expect HW 0x0 1273 */ 1274 DBG(DBG_LPU, NULL, 1275 "lpu_init - LPU_PHY_INTERRUPT_AND_STATUS_TEST: 0x%llx\n", 1276 CSR_XR(csr_base, LPU_PHY_INTERRUPT_AND_STATUS_TEST)); 1277 1278 /* 1279 * CSR_V LPU PHY LAYER interrupt regs (mask, status) 1280 */ 1281 DBG(DBG_LPU, NULL, "lpu_init - LPU_PHY_INTERRUPT_MASK: 0x%llx\n", 1282 CSR_XR(csr_base, LPU_PHY_INTERRUPT_MASK)); 1283 1284 DBG(DBG_LPU, NULL, 1285 "lpu_init - LPU_PHY_LAYER_INTERRUPT_AND_STATUS: 0x%llx\n", 1286 CSR_XR(csr_base, LPU_PHY_LAYER_INTERRUPT_AND_STATUS)); 1287 1288 /* 1289 * CSR_V LPU_RECEIVE_PHY_CONFIG Expect HW 0x0 1290 */ 1291 1292 /* 1293 * This also needs some explanation. What is the best value 1294 * for the water mark? Test mode enables which test mode? 1295 * Programming model needed for the Receiver Reset Lane N 1296 * bits. 1297 */ 1298 DBG(DBG_LPU, NULL, "lpu_init - LPU_RECEIVE_PHY_CONFIG: 0x%llx\n", 1299 CSR_XR(csr_base, LPU_RECEIVE_PHY_CONFIG)); 1300 1301 /* 1302 * CSR_V LPU_RECEIVE_PHY_STATUS1 Expect HW 0x0 1303 */ 1304 DBG(DBG_LPU, NULL, "lpu_init - LPU_RECEIVE_PHY_STATUS1: 0x%llx\n", 1305 CSR_XR(csr_base, LPU_RECEIVE_PHY_STATUS1)); 1306 1307 /* 1308 * CSR_V LPU_RECEIVE_PHY_STATUS2 Expect HW 0x0 1309 */ 1310 DBG(DBG_LPU, NULL, "lpu_init - LPU_RECEIVE_PHY_STATUS2: 0x%llx\n", 1311 CSR_XR(csr_base, LPU_RECEIVE_PHY_STATUS2)); 1312 1313 /* 1314 * CSR_V LPU_RECEIVE_PHY_STATUS3 Expect HW 0x0 1315 */ 1316 DBG(DBG_LPU, NULL, "lpu_init - LPU_RECEIVE_PHY_STATUS3: 0x%llx\n", 1317 CSR_XR(csr_base, LPU_RECEIVE_PHY_STATUS3)); 1318 1319 /* 1320 * CSR_V LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS_TEST Expect HW 0x0 1321 */ 1322 DBG(DBG_LPU, NULL, 1323 "lpu_init - LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS_TEST: 0x%llx\n", 1324 CSR_XR(csr_base, LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS_TEST)); 1325 1326 /* 1327 * CSR_V LPU RX LAYER interrupt regs (mask, status) 1328 */ 1329 DBG(DBG_LPU, NULL, 1330 "lpu_init - LPU_RECEIVE_PHY_INTERRUPT_MASK: 0x%llx\n", 1331 CSR_XR(csr_base, LPU_RECEIVE_PHY_INTERRUPT_MASK)); 1332 1333 DBG(DBG_LPU, NULL, 1334 "lpu_init - LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS: 0x%llx\n", 1335 CSR_XR(csr_base, LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS)); 1336 1337 /* 1338 * CSR_V LPU_TRANSMIT_PHY_CONFIG Expect HW 0x0 1339 */ 1340 DBG(DBG_LPU, NULL, "lpu_init - LPU_TRANSMIT_PHY_CONFIG: 0x%llx\n", 1341 CSR_XR(csr_base, LPU_TRANSMIT_PHY_CONFIG)); 1342 1343 /* 1344 * CSR_V LPU_TRANSMIT_PHY_STATUS Expect HW 0x0 1345 */ 1346 DBG(DBG_LPU, NULL, "lpu_init - LPU_TRANSMIT_PHY_STATUS: 0x%llx\n", 1347 CSR_XR(csr_base, LPU_TRANSMIT_PHY_STATUS)); 1348 1349 /* 1350 * CSR_V LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS_TEST Expect HW 0x0 1351 */ 1352 DBG(DBG_LPU, NULL, 1353 "lpu_init - LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS_TEST: 0x%llx\n", 1354 CSR_XR(csr_base, 1355 LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS_TEST)); 1356 1357 /* 1358 * CSR_V LPU TX LAYER interrupt regs (mask, status) 1359 */ 1360 DBG(DBG_LPU, NULL, 1361 "lpu_init - LPU_TRANSMIT_PHY_INTERRUPT_MASK: 0x%llx\n", 1362 CSR_XR(csr_base, LPU_TRANSMIT_PHY_INTERRUPT_MASK)); 1363 1364 DBG(DBG_LPU, NULL, 1365 "lpu_init - LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS: 0x%llx\n", 1366 CSR_XR(csr_base, LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS)); 1367 1368 /* 1369 * CSR_V LPU_TRANSMIT_PHY_STATUS_2 Expect HW 0x0 1370 */ 1371 DBG(DBG_LPU, NULL, "lpu_init - LPU_TRANSMIT_PHY_STATUS_2: 0x%llx\n", 1372 CSR_XR(csr_base, LPU_TRANSMIT_PHY_STATUS_2)); 1373 1374 /* 1375 * CSR_V LPU_LTSSM_CONFIG1 Expect OBP 0x205 1376 */ 1377 1378 /* 1379 * The new PRM has values for LTSSM 8 ns timeout value and 1380 * LTSSM 20 ns timeout value. But what do these values mean? 1381 * Most of the other bits are questions as well. 1382 * 1383 * As such we will use the reset value. 1384 */ 1385 DBG(DBG_LPU, NULL, "lpu_init - LPU_LTSSM_CONFIG1: 0x%llx\n", 1386 CSR_XR(csr_base, LPU_LTSSM_CONFIG1)); 1387 1388 /* 1389 * CSR_V LPU_LTSSM_CONFIG2 Expect OBP 0x2DC6C0 1390 */ 1391 1392 /* 1393 * Again, what does '12 ms timeout value mean'? 1394 */ 1395 val = (LPU_LTSSM_CONFIG2_LTSSM_12_TO_DEFAULT << 1396 LPU_LTSSM_CONFIG2_LTSSM_12_TO); 1397 CSR_XS(csr_base, LPU_LTSSM_CONFIG2, val); 1398 DBG(DBG_LPU, NULL, "lpu_init - LPU_LTSSM_CONFIG2: 0x%llx\n", 1399 CSR_XR(csr_base, LPU_LTSSM_CONFIG2)); 1400 1401 /* 1402 * CSR_V LPU_LTSSM_CONFIG3 Expect OBP 0x7A120 1403 */ 1404 val = (LPU_LTSSM_CONFIG3_LTSSM_2_TO_DEFAULT << 1405 LPU_LTSSM_CONFIG3_LTSSM_2_TO); 1406 CSR_XS(csr_base, LPU_LTSSM_CONFIG3, val); 1407 DBG(DBG_LPU, NULL, "lpu_init - LPU_LTSSM_CONFIG3: 0x%llx\n", 1408 CSR_XR(csr_base, LPU_LTSSM_CONFIG3)); 1409 1410 /* 1411 * CSR_V LPU_LTSSM_CONFIG4 Expect OBP 0x21300 1412 */ 1413 val = ((LPU_LTSSM_CONFIG4_DATA_RATE_DEFAULT << 1414 LPU_LTSSM_CONFIG4_DATA_RATE) | 1415 (LPU_LTSSM_CONFIG4_N_FTS_DEFAULT << 1416 LPU_LTSSM_CONFIG4_N_FTS)); 1417 CSR_XS(csr_base, LPU_LTSSM_CONFIG4, val); 1418 DBG(DBG_LPU, NULL, "lpu_init - LPU_LTSSM_CONFIG4: 0x%llx\n", 1419 CSR_XR(csr_base, LPU_LTSSM_CONFIG4)); 1420 1421 /* 1422 * CSR_V LPU_LTSSM_CONFIG5 Expect OBP 0x0 1423 */ 1424 val = 0ull; 1425 CSR_XS(csr_base, LPU_LTSSM_CONFIG5, val); 1426 DBG(DBG_LPU, NULL, "lpu_init - LPU_LTSSM_CONFIG5: 0x%llx\n", 1427 CSR_XR(csr_base, LPU_LTSSM_CONFIG5)); 1428 1429 /* 1430 * CSR_V LPU_LTSSM_STATUS1 Expect OBP 0x0 1431 */ 1432 1433 /* 1434 * LTSSM Status registers are test only. 1435 */ 1436 DBG(DBG_LPU, NULL, "lpu_init - LPU_LTSSM_STATUS1: 0x%llx\n", 1437 CSR_XR(csr_base, LPU_LTSSM_STATUS1)); 1438 1439 /* 1440 * CSR_V LPU_LTSSM_STATUS2 Expect OBP 0x0 1441 */ 1442 DBG(DBG_LPU, NULL, "lpu_init - LPU_LTSSM_STATUS2: 0x%llx\n", 1443 CSR_XR(csr_base, LPU_LTSSM_STATUS2)); 1444 1445 /* 1446 * CSR_V LPU_LTSSM_INTERRUPT_AND_STATUS_TEST Expect HW 0x0 1447 */ 1448 DBG(DBG_LPU, NULL, 1449 "lpu_init - LPU_LTSSM_INTERRUPT_AND_STATUS_TEST: 0x%llx\n", 1450 CSR_XR(csr_base, LPU_LTSSM_INTERRUPT_AND_STATUS_TEST)); 1451 1452 /* 1453 * CSR_V LPU LTSSM LAYER interrupt regs (mask, status) 1454 */ 1455 DBG(DBG_LPU, NULL, "lpu_init - LPU_LTSSM_INTERRUPT_MASK: 0x%llx\n", 1456 CSR_XR(csr_base, LPU_LTSSM_INTERRUPT_MASK)); 1457 1458 DBG(DBG_LPU, NULL, 1459 "lpu_init - LPU_LTSSM_INTERRUPT_AND_STATUS: 0x%llx\n", 1460 CSR_XR(csr_base, LPU_LTSSM_INTERRUPT_AND_STATUS)); 1461 1462 /* 1463 * CSR_V LPU_LTSSM_STATUS_WRITE_ENABLE Expect OBP 0x0 1464 */ 1465 DBG(DBG_LPU, NULL, 1466 "lpu_init - LPU_LTSSM_STATUS_WRITE_ENABLE: 0x%llx\n", 1467 CSR_XR(csr_base, LPU_LTSSM_STATUS_WRITE_ENABLE)); 1468 1469 /* 1470 * CSR_V LPU_GIGABLAZE_GLUE_CONFIG1 Expect OBP 0x88407 1471 */ 1472 DBG(DBG_LPU, NULL, "lpu_init - LPU_GIGABLAZE_GLUE_CONFIG1: 0x%llx\n", 1473 CSR_XR(csr_base, LPU_GIGABLAZE_GLUE_CONFIG1)); 1474 1475 /* 1476 * CSR_V LPU_GIGABLAZE_GLUE_CONFIG2 Expect OBP 0x35 1477 */ 1478 DBG(DBG_LPU, NULL, "lpu_init - LPU_GIGABLAZE_GLUE_CONFIG2: 0x%llx\n", 1479 CSR_XR(csr_base, LPU_GIGABLAZE_GLUE_CONFIG2)); 1480 1481 /* 1482 * CSR_V LPU_GIGABLAZE_GLUE_CONFIG3 Expect OBP 0x4400FA 1483 */ 1484 DBG(DBG_LPU, NULL, "lpu_init - LPU_GIGABLAZE_GLUE_CONFIG3: 0x%llx\n", 1485 CSR_XR(csr_base, LPU_GIGABLAZE_GLUE_CONFIG3)); 1486 1487 /* 1488 * CSR_V LPU_GIGABLAZE_GLUE_CONFIG4 Expect OBP 0x1E848 1489 */ 1490 DBG(DBG_LPU, NULL, "lpu_init - LPU_GIGABLAZE_GLUE_CONFIG4: 0x%llx\n", 1491 CSR_XR(csr_base, LPU_GIGABLAZE_GLUE_CONFIG4)); 1492 1493 /* 1494 * CSR_V LPU_GIGABLAZE_GLUE_STATUS Expect OBP 0x0 1495 */ 1496 DBG(DBG_LPU, NULL, "lpu_init - LPU_GIGABLAZE_GLUE_STATUS: 0x%llx\n", 1497 CSR_XR(csr_base, LPU_GIGABLAZE_GLUE_STATUS)); 1498 1499 /* 1500 * CSR_V LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS_TEST Expect OBP 0x0 1501 */ 1502 DBG(DBG_LPU, NULL, "lpu_init - " 1503 "LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS_TEST: 0x%llx\n", 1504 CSR_XR(csr_base, 1505 LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS_TEST)); 1506 1507 /* 1508 * CSR_V LPU GIGABLASE LAYER interrupt regs (mask, status) 1509 */ 1510 DBG(DBG_LPU, NULL, 1511 "lpu_init - LPU_GIGABLAZE_GLUE_INTERRUPT_MASK: 0x%llx\n", 1512 CSR_XR(csr_base, LPU_GIGABLAZE_GLUE_INTERRUPT_MASK)); 1513 1514 DBG(DBG_LPU, NULL, 1515 "lpu_init - LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS: 0x%llx\n", 1516 CSR_XR(csr_base, LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS)); 1517 1518 /* 1519 * CSR_V LPU_GIGABLAZE_GLUE_POWER_DOWN1 Expect HW 0x0 1520 */ 1521 DBG(DBG_LPU, NULL, 1522 "lpu_init - LPU_GIGABLAZE_GLUE_POWER_DOWN1: 0x%llx\n", 1523 CSR_XR(csr_base, LPU_GIGABLAZE_GLUE_POWER_DOWN1)); 1524 1525 /* 1526 * CSR_V LPU_GIGABLAZE_GLUE_POWER_DOWN2 Expect HW 0x0 1527 */ 1528 DBG(DBG_LPU, NULL, 1529 "lpu_init - LPU_GIGABLAZE_GLUE_POWER_DOWN2: 0x%llx\n", 1530 CSR_XR(csr_base, LPU_GIGABLAZE_GLUE_POWER_DOWN2)); 1531 1532 /* 1533 * CSR_V LPU_GIGABLAZE_GLUE_CONFIG5 Expect OBP 0x0 1534 */ 1535 DBG(DBG_LPU, NULL, "lpu_init - LPU_GIGABLAZE_GLUE_CONFIG5: 0x%llx\n", 1536 CSR_XR(csr_base, LPU_GIGABLAZE_GLUE_CONFIG5)); 1537 } 1538 1539 /* ARGSUSED */ 1540 static void 1541 dlu_init(caddr_t csr_base, pxu_t *pxu_p) 1542 { 1543 uint64_t val; 1544 1545 CSR_XS(csr_base, DLU_INTERRUPT_MASK, 0ull); 1546 DBG(DBG_TLU, NULL, "dlu_init - DLU_INTERRUPT_MASK: 0x%llx\n", 1547 CSR_XR(csr_base, DLU_INTERRUPT_MASK)); 1548 1549 val = (1ull << DLU_LINK_LAYER_CONFIG_VC0_EN); 1550 CSR_XS(csr_base, DLU_LINK_LAYER_CONFIG, val); 1551 DBG(DBG_TLU, NULL, "dlu_init - DLU_LINK_LAYER_CONFIG: 0x%llx\n", 1552 CSR_XR(csr_base, DLU_LINK_LAYER_CONFIG)); 1553 1554 val = (1ull << DLU_FLOW_CONTROL_UPDATE_CONTROL_FC0_U_NP_EN) | 1555 (1ull << DLU_FLOW_CONTROL_UPDATE_CONTROL_FC0_U_P_EN); 1556 1557 CSR_XS(csr_base, DLU_FLOW_CONTROL_UPDATE_CONTROL, val); 1558 DBG(DBG_TLU, NULL, "dlu_init - DLU_FLOW_CONTROL_UPDATE_CONTROL: " 1559 "0x%llx\n", CSR_XR(csr_base, DLU_FLOW_CONTROL_UPDATE_CONTROL)); 1560 1561 val = (DLU_TXLINK_REPLAY_TIMER_THRESHOLD_DEFAULT << 1562 DLU_TXLINK_REPLAY_TIMER_THRESHOLD_RPLAY_TMR_THR); 1563 1564 CSR_XS(csr_base, DLU_TXLINK_REPLAY_TIMER_THRESHOLD, val); 1565 1566 DBG(DBG_TLU, NULL, "dlu_init - DLU_TXLINK_REPLAY_TIMER_THRESHOLD: " 1567 "0x%llx\n", CSR_XR(csr_base, DLU_TXLINK_REPLAY_TIMER_THRESHOLD)); 1568 } 1569 1570 /* ARGSUSED */ 1571 static void 1572 dmc_init(caddr_t csr_base, pxu_t *pxu_p) 1573 { 1574 uint64_t val; 1575 1576 /* 1577 * CSR_V DMC_CORE_AND_BLOCK_INTERRUPT_ENABLE Expect OBP 0x8000000000000003 1578 */ 1579 1580 val = -1ull; 1581 CSR_XS(csr_base, DMC_CORE_AND_BLOCK_INTERRUPT_ENABLE, val); 1582 DBG(DBG_DMC, NULL, 1583 "dmc_init - DMC_CORE_AND_BLOCK_INTERRUPT_ENABLE: 0x%llx\n", 1584 CSR_XR(csr_base, DMC_CORE_AND_BLOCK_INTERRUPT_ENABLE)); 1585 1586 /* 1587 * CSR_V DMC_CORE_AND_BLOCK_ERROR_STATUS Expect HW 0x0 1588 */ 1589 DBG(DBG_DMC, NULL, 1590 "dmc_init - DMC_CORE_AND_BLOCK_ERROR_STATUS: 0x%llx\n", 1591 CSR_XR(csr_base, DMC_CORE_AND_BLOCK_ERROR_STATUS)); 1592 1593 /* 1594 * CSR_V DMC_DEBUG_SELECT_FOR_PORT_A Expect HW 0x0 1595 */ 1596 val = 0x0ull; 1597 CSR_XS(csr_base, DMC_DEBUG_SELECT_FOR_PORT_A, val); 1598 DBG(DBG_DMC, NULL, "dmc_init - DMC_DEBUG_SELECT_FOR_PORT_A: 0x%llx\n", 1599 CSR_XR(csr_base, DMC_DEBUG_SELECT_FOR_PORT_A)); 1600 1601 /* 1602 * CSR_V DMC_DEBUG_SELECT_FOR_PORT_B Expect HW 0x0 1603 */ 1604 val = 0x0ull; 1605 CSR_XS(csr_base, DMC_DEBUG_SELECT_FOR_PORT_B, val); 1606 DBG(DBG_DMC, NULL, "dmc_init - DMC_DEBUG_SELECT_FOR_PORT_B: 0x%llx\n", 1607 CSR_XR(csr_base, DMC_DEBUG_SELECT_FOR_PORT_B)); 1608 } 1609 1610 void 1611 hvio_pec_init(caddr_t csr_base, pxu_t *pxu_p) 1612 { 1613 uint64_t val; 1614 1615 ilu_init(csr_base, pxu_p); 1616 tlu_init(csr_base, pxu_p); 1617 1618 switch (PX_CHIP_TYPE(pxu_p)) { 1619 case PX_CHIP_OBERON: 1620 dlu_init(csr_base, pxu_p); 1621 break; 1622 case PX_CHIP_FIRE: 1623 lpu_init(csr_base, pxu_p); 1624 break; 1625 default: 1626 DBG(DBG_PEC, NULL, "hvio_pec_init - unknown chip type: 0x%x\n", 1627 PX_CHIP_TYPE(pxu_p)); 1628 break; 1629 } 1630 1631 dmc_init(csr_base, pxu_p); 1632 1633 /* 1634 * CSR_V PEC_CORE_AND_BLOCK_INTERRUPT_ENABLE Expect Kernel 0x800000000000000F 1635 */ 1636 1637 val = -1ull; 1638 CSR_XS(csr_base, PEC_CORE_AND_BLOCK_INTERRUPT_ENABLE, val); 1639 DBG(DBG_PEC, NULL, 1640 "hvio_pec_init - PEC_CORE_AND_BLOCK_INTERRUPT_ENABLE: 0x%llx\n", 1641 CSR_XR(csr_base, PEC_CORE_AND_BLOCK_INTERRUPT_ENABLE)); 1642 1643 /* 1644 * CSR_V PEC_CORE_AND_BLOCK_INTERRUPT_STATUS Expect HW 0x0 1645 */ 1646 DBG(DBG_PEC, NULL, 1647 "hvio_pec_init - PEC_CORE_AND_BLOCK_INTERRUPT_STATUS: 0x%llx\n", 1648 CSR_XR(csr_base, PEC_CORE_AND_BLOCK_INTERRUPT_STATUS)); 1649 } 1650 1651 /* 1652 * Convert a TTE to physical address 1653 */ 1654 static r_addr_t 1655 mmu_tte_to_pa(uint64_t tte, pxu_t *pxu_p) 1656 { 1657 uint64_t pa_mask; 1658 1659 switch (PX_CHIP_TYPE(pxu_p)) { 1660 case PX_CHIP_OBERON: 1661 pa_mask = MMU_OBERON_PADDR_MASK; 1662 break; 1663 case PX_CHIP_FIRE: 1664 pa_mask = MMU_FIRE_PADDR_MASK; 1665 break; 1666 default: 1667 DBG(DBG_MMU, NULL, "mmu_tte_to_pa - unknown chip type: 0x%x\n", 1668 PX_CHIP_TYPE(pxu_p)); 1669 pa_mask = 0; 1670 break; 1671 } 1672 return ((tte & pa_mask) >> MMU_PAGE_SHIFT); 1673 } 1674 1675 /* 1676 * Return MMU bypass noncache bit for chip 1677 */ 1678 static r_addr_t 1679 mmu_bypass_noncache(pxu_t *pxu_p) 1680 { 1681 r_addr_t bypass_noncache_bit; 1682 1683 switch (PX_CHIP_TYPE(pxu_p)) { 1684 case PX_CHIP_OBERON: 1685 bypass_noncache_bit = MMU_OBERON_BYPASS_NONCACHE; 1686 break; 1687 case PX_CHIP_FIRE: 1688 bypass_noncache_bit = MMU_FIRE_BYPASS_NONCACHE; 1689 break; 1690 default: 1691 DBG(DBG_MMU, NULL, 1692 "mmu_bypass_nocache - unknown chip type: 0x%x\n", 1693 PX_CHIP_TYPE(pxu_p)); 1694 bypass_noncache_bit = 0; 1695 break; 1696 } 1697 return (bypass_noncache_bit); 1698 } 1699 1700 /* 1701 * Calculate number of TSB entries for the chip. 1702 */ 1703 /* ARGSUSED */ 1704 static uint_t 1705 mmu_tsb_entries(caddr_t csr_base, pxu_t *pxu_p) 1706 { 1707 uint64_t tsb_ctrl; 1708 uint_t obp_tsb_entries, obp_tsb_size; 1709 1710 tsb_ctrl = CSR_XR(csr_base, MMU_TSB_CONTROL); 1711 1712 obp_tsb_size = tsb_ctrl & 0xF; 1713 1714 obp_tsb_entries = MMU_TSBSIZE_TO_TSBENTRIES(obp_tsb_size); 1715 1716 return (obp_tsb_entries); 1717 } 1718 1719 /* 1720 * Initialize the module, but do not enable interrupts. 1721 */ 1722 void 1723 hvio_mmu_init(caddr_t csr_base, pxu_t *pxu_p) 1724 { 1725 uint64_t val, i, obp_tsb_pa, *base_tte_addr; 1726 uint_t obp_tsb_entries; 1727 1728 bzero(pxu_p->tsb_vaddr, pxu_p->tsb_size); 1729 1730 /* 1731 * Preserve OBP's TSB 1732 */ 1733 obp_tsb_pa = CSR_XR(csr_base, MMU_TSB_CONTROL) & MMU_TSB_PA_MASK; 1734 1735 obp_tsb_entries = mmu_tsb_entries(csr_base, pxu_p); 1736 1737 base_tte_addr = pxu_p->tsb_vaddr + 1738 ((pxu_p->tsb_size >> 3) - obp_tsb_entries); 1739 1740 for (i = 0; i < obp_tsb_entries; i++) { 1741 uint64_t tte = lddphys(obp_tsb_pa + i * 8); 1742 1743 if (!MMU_TTE_VALID(tte)) 1744 continue; 1745 1746 base_tte_addr[i] = tte; 1747 } 1748 1749 /* 1750 * Invalidate the TLB through the diagnostic register. 1751 */ 1752 1753 CSR_XS(csr_base, MMU_TTE_CACHE_INVALIDATE, -1ull); 1754 1755 /* 1756 * Configure the Fire MMU TSB Control Register. Determine 1757 * the encoding for either 8KB pages (0) or 64KB pages (1). 1758 * 1759 * Write the most significant 30 bits of the TSB physical address 1760 * and the encoded TSB table size. 1761 */ 1762 for (i = 8; i && (pxu_p->tsb_size < (0x2000 << i)); i--); 1763 1764 val = (((((va_to_pa(pxu_p->tsb_vaddr)) >> 13) << 13) | 1765 ((MMU_PAGE_SHIFT == 13) ? 0 : 1) << 8) | i); 1766 1767 CSR_XS(csr_base, MMU_TSB_CONTROL, val); 1768 1769 /* 1770 * Enable the MMU, set the "TSB Cache Snoop Enable", 1771 * the "Cache Mode", the "Bypass Enable" and 1772 * the "Translation Enable" bits. 1773 */ 1774 val = CSR_XR(csr_base, MMU_CONTROL_AND_STATUS); 1775 val |= ((1ull << MMU_CONTROL_AND_STATUS_SE) 1776 | (MMU_CONTROL_AND_STATUS_CM_MASK << MMU_CONTROL_AND_STATUS_CM) 1777 | (1ull << MMU_CONTROL_AND_STATUS_BE) 1778 | (1ull << MMU_CONTROL_AND_STATUS_TE)); 1779 1780 CSR_XS(csr_base, MMU_CONTROL_AND_STATUS, val); 1781 1782 /* 1783 * Read the register here to ensure that the previous writes to 1784 * the Fire MMU registers have been flushed. (Technically, this 1785 * is not entirely necessary here as we will likely do later reads 1786 * during Fire initialization, but it is a small price to pay for 1787 * more modular code.) 1788 */ 1789 (void) CSR_XR(csr_base, MMU_CONTROL_AND_STATUS); 1790 1791 /* 1792 * CSR_V TLU's UE interrupt regs (log, enable, status, clear) 1793 * Plus header logs 1794 */ 1795 DBG(DBG_MMU, NULL, "mmu_init - MMU_ERROR_LOG_ENABLE: 0x%llx\n", 1796 CSR_XR(csr_base, MMU_ERROR_LOG_ENABLE)); 1797 1798 DBG(DBG_MMU, NULL, "mmu_init - MMU_INTERRUPT_ENABLE: 0x%llx\n", 1799 CSR_XR(csr_base, MMU_INTERRUPT_ENABLE)); 1800 1801 DBG(DBG_MMU, NULL, "mmu_init - MMU_INTERRUPT_STATUS: 0x%llx\n", 1802 CSR_XR(csr_base, MMU_INTERRUPT_STATUS)); 1803 1804 DBG(DBG_MMU, NULL, "mmu_init - MMU_ERROR_STATUS_CLEAR: 0x%llx\n", 1805 CSR_XR(csr_base, MMU_ERROR_STATUS_CLEAR)); 1806 } 1807 1808 /* 1809 * Generic IOMMU Servies 1810 */ 1811 1812 /* ARGSUSED */ 1813 uint64_t 1814 hvio_iommu_map(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid, pages_t pages, 1815 io_attributes_t io_attr, void *addr, size_t pfn_index, int flags) 1816 { 1817 tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); 1818 uint64_t attr = MMU_TTE_V; 1819 int i; 1820 1821 if (io_attr & PCI_MAP_ATTR_WRITE) 1822 attr |= MMU_TTE_W; 1823 1824 if ((PX_CHIP_TYPE(pxu_p) == PX_CHIP_OBERON) && 1825 (io_attr & PCI_MAP_ATTR_RO)) 1826 attr |= MMU_TTE_RO; 1827 1828 if (attr & MMU_TTE_RO) { 1829 DBG(DBG_MMU, NULL, "hvio_iommu_map: pfn_index=0x%x " 1830 "pages=0x%x attr = 0x%lx\n", pfn_index, pages, attr); 1831 } 1832 1833 if (flags & MMU_MAP_PFN) { 1834 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)addr; 1835 for (i = 0; i < pages; i++, pfn_index++, tsb_index++) { 1836 px_iopfn_t pfn = PX_GET_MP_PFN(mp, pfn_index); 1837 pxu_p->tsb_vaddr[tsb_index] = MMU_PTOB(pfn) | attr; 1838 1839 /* 1840 * Oberon will need to flush the corresponding TTEs in 1841 * Cache. We only need to flush every cache line. 1842 * Extra PIO's are expensive. 1843 */ 1844 if (PX_CHIP_TYPE(pxu_p) == PX_CHIP_OBERON) { 1845 if ((i == (pages-1))||!((tsb_index+1) & 0x7)) { 1846 CSR_XS(dev_hdl, 1847 MMU_TTE_CACHE_FLUSH_ADDRESS, 1848 (pxu_p->tsb_paddr+ 1849 (tsb_index*MMU_TTE_SIZE))); 1850 } 1851 } 1852 } 1853 } else { 1854 caddr_t a = (caddr_t)addr; 1855 for (i = 0; i < pages; i++, a += MMU_PAGE_SIZE, tsb_index++) { 1856 px_iopfn_t pfn = hat_getpfnum(kas.a_hat, a); 1857 pxu_p->tsb_vaddr[tsb_index] = MMU_PTOB(pfn) | attr; 1858 1859 /* 1860 * Oberon will need to flush the corresponding TTEs in 1861 * Cache. We only need to flush every cache line. 1862 * Extra PIO's are expensive. 1863 */ 1864 if (PX_CHIP_TYPE(pxu_p) == PX_CHIP_OBERON) { 1865 if ((i == (pages-1))||!((tsb_index+1) & 0x7)) { 1866 CSR_XS(dev_hdl, 1867 MMU_TTE_CACHE_FLUSH_ADDRESS, 1868 (pxu_p->tsb_paddr+ 1869 (tsb_index*MMU_TTE_SIZE))); 1870 } 1871 } 1872 } 1873 } 1874 1875 return (H_EOK); 1876 } 1877 1878 /* ARGSUSED */ 1879 uint64_t 1880 hvio_iommu_demap(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid, 1881 pages_t pages) 1882 { 1883 tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); 1884 int i; 1885 1886 for (i = 0; i < pages; i++, tsb_index++) { 1887 pxu_p->tsb_vaddr[tsb_index] = MMU_INVALID_TTE; 1888 1889 /* 1890 * Oberon will need to flush the corresponding TTEs in 1891 * Cache. We only need to flush every cache line. 1892 * Extra PIO's are expensive. 1893 */ 1894 if (PX_CHIP_TYPE(pxu_p) == PX_CHIP_OBERON) { 1895 if ((i == (pages-1))||!((tsb_index+1) & 0x7)) { 1896 CSR_XS(dev_hdl, 1897 MMU_TTE_CACHE_FLUSH_ADDRESS, 1898 (pxu_p->tsb_paddr+ 1899 (tsb_index*MMU_TTE_SIZE))); 1900 } 1901 } 1902 } 1903 1904 return (H_EOK); 1905 } 1906 1907 /* ARGSUSED */ 1908 uint64_t 1909 hvio_iommu_getmap(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid, 1910 io_attributes_t *attr_p, r_addr_t *r_addr_p) 1911 { 1912 tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); 1913 uint64_t *tte_addr; 1914 uint64_t ret = H_EOK; 1915 1916 tte_addr = (uint64_t *)(pxu_p->tsb_vaddr) + tsb_index; 1917 1918 if (*tte_addr & MMU_TTE_V) { 1919 *r_addr_p = mmu_tte_to_pa(*tte_addr, pxu_p); 1920 *attr_p = (*tte_addr & MMU_TTE_W) ? 1921 PCI_MAP_ATTR_WRITE:PCI_MAP_ATTR_READ; 1922 } else { 1923 *r_addr_p = 0; 1924 *attr_p = 0; 1925 ret = H_ENOMAP; 1926 } 1927 1928 return (ret); 1929 } 1930 1931 /* ARGSUSED */ 1932 uint64_t 1933 hvio_get_bypass_base(pxu_t *pxu_p) 1934 { 1935 uint64_t base; 1936 1937 switch (PX_CHIP_TYPE(pxu_p)) { 1938 case PX_CHIP_OBERON: 1939 base = MMU_OBERON_BYPASS_BASE; 1940 break; 1941 case PX_CHIP_FIRE: 1942 base = MMU_FIRE_BYPASS_BASE; 1943 break; 1944 default: 1945 DBG(DBG_MMU, NULL, 1946 "hvio_get_bypass_base - unknown chip type: 0x%x\n", 1947 PX_CHIP_TYPE(pxu_p)); 1948 base = 0; 1949 break; 1950 } 1951 return (base); 1952 } 1953 1954 /* ARGSUSED */ 1955 uint64_t 1956 hvio_get_bypass_end(pxu_t *pxu_p) 1957 { 1958 uint64_t end; 1959 1960 switch (PX_CHIP_TYPE(pxu_p)) { 1961 case PX_CHIP_OBERON: 1962 end = MMU_OBERON_BYPASS_END; 1963 break; 1964 case PX_CHIP_FIRE: 1965 end = MMU_FIRE_BYPASS_END; 1966 break; 1967 default: 1968 DBG(DBG_MMU, NULL, 1969 "hvio_get_bypass_end - unknown chip type: 0x%x\n", 1970 PX_CHIP_TYPE(pxu_p)); 1971 end = 0; 1972 break; 1973 } 1974 return (end); 1975 } 1976 1977 /* ARGSUSED */ 1978 uint64_t 1979 hvio_iommu_getbypass(devhandle_t dev_hdl, pxu_t *pxu_p, r_addr_t ra, 1980 io_attributes_t attr, io_addr_t *io_addr_p) 1981 { 1982 uint64_t pfn = MMU_BTOP(ra); 1983 1984 *io_addr_p = hvio_get_bypass_base(pxu_p) | ra | 1985 (pf_is_memory(pfn) ? 0 : mmu_bypass_noncache(pxu_p)); 1986 1987 return (H_EOK); 1988 } 1989 1990 /* 1991 * Generic IO Interrupt Servies 1992 */ 1993 1994 /* 1995 * Converts a device specific interrupt number given by the 1996 * arguments devhandle and devino into a system specific ino. 1997 */ 1998 /* ARGSUSED */ 1999 uint64_t 2000 hvio_intr_devino_to_sysino(devhandle_t dev_hdl, pxu_t *pxu_p, devino_t devino, 2001 sysino_t *sysino) 2002 { 2003 if (devino > INTERRUPT_MAPPING_ENTRIES) { 2004 DBG(DBG_IB, NULL, "ino %x is invalid\n", devino); 2005 return (H_ENOINTR); 2006 } 2007 2008 *sysino = DEVINO_TO_SYSINO(pxu_p->portid, devino); 2009 2010 return (H_EOK); 2011 } 2012 2013 /* 2014 * Returns state in intr_valid_state if the interrupt defined by sysino 2015 * is valid (enabled) or not-valid (disabled). 2016 */ 2017 uint64_t 2018 hvio_intr_getvalid(devhandle_t dev_hdl, sysino_t sysino, 2019 intr_valid_state_t *intr_valid_state) 2020 { 2021 if (CSRA_BR((caddr_t)dev_hdl, INTERRUPT_MAPPING, 2022 SYSINO_TO_DEVINO(sysino), ENTRIES_V)) { 2023 *intr_valid_state = INTR_VALID; 2024 } else { 2025 *intr_valid_state = INTR_NOTVALID; 2026 } 2027 2028 return (H_EOK); 2029 } 2030 2031 /* 2032 * Sets the 'valid' state of the interrupt defined by 2033 * the argument sysino to the state defined by the 2034 * argument intr_valid_state. 2035 */ 2036 uint64_t 2037 hvio_intr_setvalid(devhandle_t dev_hdl, sysino_t sysino, 2038 intr_valid_state_t intr_valid_state) 2039 { 2040 switch (intr_valid_state) { 2041 case INTR_VALID: 2042 CSRA_BS((caddr_t)dev_hdl, INTERRUPT_MAPPING, 2043 SYSINO_TO_DEVINO(sysino), ENTRIES_V); 2044 break; 2045 case INTR_NOTVALID: 2046 CSRA_BC((caddr_t)dev_hdl, INTERRUPT_MAPPING, 2047 SYSINO_TO_DEVINO(sysino), ENTRIES_V); 2048 break; 2049 default: 2050 return (EINVAL); 2051 } 2052 2053 return (H_EOK); 2054 } 2055 2056 /* 2057 * Returns the current state of the interrupt given by the sysino 2058 * argument. 2059 */ 2060 uint64_t 2061 hvio_intr_getstate(devhandle_t dev_hdl, sysino_t sysino, 2062 intr_state_t *intr_state) 2063 { 2064 intr_state_t state; 2065 2066 state = CSRA_FR((caddr_t)dev_hdl, INTERRUPT_CLEAR, 2067 SYSINO_TO_DEVINO(sysino), ENTRIES_INT_STATE); 2068 2069 switch (state) { 2070 case INTERRUPT_IDLE_STATE: 2071 *intr_state = INTR_IDLE_STATE; 2072 break; 2073 case INTERRUPT_RECEIVED_STATE: 2074 *intr_state = INTR_RECEIVED_STATE; 2075 break; 2076 case INTERRUPT_PENDING_STATE: 2077 *intr_state = INTR_DELIVERED_STATE; 2078 break; 2079 default: 2080 return (EINVAL); 2081 } 2082 2083 return (H_EOK); 2084 2085 } 2086 2087 /* 2088 * Sets the current state of the interrupt given by the sysino 2089 * argument to the value given in the argument intr_state. 2090 * 2091 * Note: Setting the state to INTR_IDLE clears any pending 2092 * interrupt for sysino. 2093 */ 2094 uint64_t 2095 hvio_intr_setstate(devhandle_t dev_hdl, sysino_t sysino, 2096 intr_state_t intr_state) 2097 { 2098 intr_state_t state; 2099 2100 switch (intr_state) { 2101 case INTR_IDLE_STATE: 2102 state = INTERRUPT_IDLE_STATE; 2103 break; 2104 case INTR_DELIVERED_STATE: 2105 state = INTERRUPT_PENDING_STATE; 2106 break; 2107 default: 2108 return (EINVAL); 2109 } 2110 2111 CSRA_FS((caddr_t)dev_hdl, INTERRUPT_CLEAR, 2112 SYSINO_TO_DEVINO(sysino), ENTRIES_INT_STATE, state); 2113 2114 return (H_EOK); 2115 } 2116 2117 /* 2118 * Returns the cpuid that is the current target of the 2119 * interrupt given by the sysino argument. 2120 * 2121 * The cpuid value returned is undefined if the target 2122 * has not been set via intr_settarget. 2123 */ 2124 uint64_t 2125 hvio_intr_gettarget(devhandle_t dev_hdl, pxu_t *pxu_p, sysino_t sysino, 2126 cpuid_t *cpuid) 2127 { 2128 switch (PX_CHIP_TYPE(pxu_p)) { 2129 case PX_CHIP_OBERON: 2130 *cpuid = CSRA_FR((caddr_t)dev_hdl, INTERRUPT_MAPPING, 2131 SYSINO_TO_DEVINO(sysino), ENTRIES_T_DESTID); 2132 break; 2133 case PX_CHIP_FIRE: 2134 *cpuid = CSRA_FR((caddr_t)dev_hdl, INTERRUPT_MAPPING, 2135 SYSINO_TO_DEVINO(sysino), ENTRIES_T_JPID); 2136 break; 2137 default: 2138 DBG(DBG_CB, NULL, "hvio_intr_gettarget - " 2139 "unknown chip type: 0x%x\n", PX_CHIP_TYPE(pxu_p)); 2140 return (EINVAL); 2141 } 2142 2143 return (H_EOK); 2144 } 2145 2146 /* 2147 * Set the target cpu for the interrupt defined by the argument 2148 * sysino to the target cpu value defined by the argument cpuid. 2149 */ 2150 uint64_t 2151 hvio_intr_settarget(devhandle_t dev_hdl, pxu_t *pxu_p, sysino_t sysino, 2152 cpuid_t cpuid) 2153 { 2154 2155 uint64_t val, intr_controller; 2156 uint32_t ino = SYSINO_TO_DEVINO(sysino); 2157 2158 /* 2159 * For now, we assign interrupt controller in a round 2160 * robin fashion. Later, we may need to come up with 2161 * a more efficient assignment algorithm. 2162 */ 2163 intr_controller = 0x1ull << (cpuid % 4); 2164 2165 switch (PX_CHIP_TYPE(pxu_p)) { 2166 case PX_CHIP_OBERON: 2167 val = (((cpuid & 2168 INTERRUPT_MAPPING_ENTRIES_T_DESTID_MASK) << 2169 INTERRUPT_MAPPING_ENTRIES_T_DESTID) | 2170 ((intr_controller & 2171 INTERRUPT_MAPPING_ENTRIES_INT_CNTRL_NUM_MASK) 2172 << INTERRUPT_MAPPING_ENTRIES_INT_CNTRL_NUM)); 2173 break; 2174 case PX_CHIP_FIRE: 2175 val = (((cpuid & INTERRUPT_MAPPING_ENTRIES_T_JPID_MASK) << 2176 INTERRUPT_MAPPING_ENTRIES_T_JPID) | 2177 ((intr_controller & 2178 INTERRUPT_MAPPING_ENTRIES_INT_CNTRL_NUM_MASK) 2179 << INTERRUPT_MAPPING_ENTRIES_INT_CNTRL_NUM)); 2180 break; 2181 default: 2182 DBG(DBG_CB, NULL, "hvio_intr_settarget - " 2183 "unknown chip type: 0x%x\n", PX_CHIP_TYPE(pxu_p)); 2184 return (EINVAL); 2185 } 2186 2187 /* For EQ interrupts, set DATA MONDO bit */ 2188 if ((ino >= PX_DEFAULT_MSIQ_1ST_DEVINO) && 2189 (ino < (PX_DEFAULT_MSIQ_1ST_DEVINO + PX_DEFAULT_MSIQ_CNT))) 2190 val |= (0x1ull << INTERRUPT_MAPPING_ENTRIES_MDO_MODE); 2191 2192 CSRA_XS((caddr_t)dev_hdl, INTERRUPT_MAPPING, ino, val); 2193 2194 return (H_EOK); 2195 } 2196 2197 /* 2198 * MSIQ Functions: 2199 */ 2200 uint64_t 2201 hvio_msiq_init(devhandle_t dev_hdl, pxu_t *pxu_p) 2202 { 2203 CSRA_XS((caddr_t)dev_hdl, EVENT_QUEUE_BASE_ADDRESS, 0, 2204 (uint64_t)pxu_p->msiq_mapped_p); 2205 DBG(DBG_IB, NULL, 2206 "hvio_msiq_init: EVENT_QUEUE_BASE_ADDRESS 0x%llx\n", 2207 CSR_XR((caddr_t)dev_hdl, EVENT_QUEUE_BASE_ADDRESS)); 2208 2209 CSRA_XS((caddr_t)dev_hdl, INTERRUPT_MONDO_DATA_0, 0, 2210 (uint64_t)ID_TO_IGN(PX_CHIP_TYPE(pxu_p), 2211 pxu_p->portid) << INO_BITS); 2212 DBG(DBG_IB, NULL, "hvio_msiq_init: " 2213 "INTERRUPT_MONDO_DATA_0: 0x%llx\n", 2214 CSR_XR((caddr_t)dev_hdl, INTERRUPT_MONDO_DATA_0)); 2215 2216 return (H_EOK); 2217 } 2218 2219 uint64_t 2220 hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 2221 pci_msiq_valid_state_t *msiq_valid_state) 2222 { 2223 uint32_t eq_state; 2224 uint64_t ret = H_EOK; 2225 2226 eq_state = CSRA_FR((caddr_t)dev_hdl, EVENT_QUEUE_STATE, 2227 msiq_id, ENTRIES_STATE); 2228 2229 switch (eq_state) { 2230 case EQ_IDLE_STATE: 2231 *msiq_valid_state = PCI_MSIQ_INVALID; 2232 break; 2233 case EQ_ACTIVE_STATE: 2234 case EQ_ERROR_STATE: 2235 *msiq_valid_state = PCI_MSIQ_VALID; 2236 break; 2237 default: 2238 ret = H_EIO; 2239 break; 2240 } 2241 2242 return (ret); 2243 } 2244 2245 uint64_t 2246 hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 2247 pci_msiq_valid_state_t msiq_valid_state) 2248 { 2249 uint64_t ret = H_EOK; 2250 2251 switch (msiq_valid_state) { 2252 case PCI_MSIQ_INVALID: 2253 CSRA_BS((caddr_t)dev_hdl, EVENT_QUEUE_CONTROL_CLEAR, 2254 msiq_id, ENTRIES_DIS); 2255 break; 2256 case PCI_MSIQ_VALID: 2257 CSRA_BS((caddr_t)dev_hdl, EVENT_QUEUE_CONTROL_SET, 2258 msiq_id, ENTRIES_EN); 2259 break; 2260 default: 2261 ret = H_EINVAL; 2262 break; 2263 } 2264 2265 return (ret); 2266 } 2267 2268 uint64_t 2269 hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id, 2270 pci_msiq_state_t *msiq_state) 2271 { 2272 uint32_t eq_state; 2273 uint64_t ret = H_EOK; 2274 2275 eq_state = CSRA_FR((caddr_t)dev_hdl, EVENT_QUEUE_STATE, 2276 msiq_id, ENTRIES_STATE); 2277 2278 switch (eq_state) { 2279 case EQ_IDLE_STATE: 2280 case EQ_ACTIVE_STATE: 2281 *msiq_state = PCI_MSIQ_STATE_IDLE; 2282 break; 2283 case EQ_ERROR_STATE: 2284 *msiq_state = PCI_MSIQ_STATE_ERROR; 2285 break; 2286 default: 2287 ret = H_EIO; 2288 } 2289 2290 return (ret); 2291 } 2292 2293 uint64_t 2294 hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id, 2295 pci_msiq_state_t msiq_state) 2296 { 2297 uint32_t eq_state; 2298 uint64_t ret = H_EOK; 2299 2300 eq_state = CSRA_FR((caddr_t)dev_hdl, EVENT_QUEUE_STATE, 2301 msiq_id, ENTRIES_STATE); 2302 2303 switch (eq_state) { 2304 case EQ_IDLE_STATE: 2305 if (msiq_state == PCI_MSIQ_STATE_ERROR) 2306 ret = H_EIO; 2307 break; 2308 case EQ_ACTIVE_STATE: 2309 if (msiq_state == PCI_MSIQ_STATE_ERROR) 2310 CSRA_BS((caddr_t)dev_hdl, EVENT_QUEUE_CONTROL_SET, 2311 msiq_id, ENTRIES_ENOVERR); 2312 else 2313 ret = H_EIO; 2314 break; 2315 case EQ_ERROR_STATE: 2316 if (msiq_state == PCI_MSIQ_STATE_IDLE) 2317 CSRA_BS((caddr_t)dev_hdl, EVENT_QUEUE_CONTROL_CLEAR, 2318 msiq_id, ENTRIES_E2I); 2319 else 2320 ret = H_EIO; 2321 break; 2322 default: 2323 ret = H_EIO; 2324 } 2325 2326 return (ret); 2327 } 2328 2329 uint64_t 2330 hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id, 2331 msiqhead_t *msiq_head) 2332 { 2333 *msiq_head = CSRA_FR((caddr_t)dev_hdl, EVENT_QUEUE_HEAD, 2334 msiq_id, ENTRIES_HEAD); 2335 2336 return (H_EOK); 2337 } 2338 2339 uint64_t 2340 hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id, 2341 msiqhead_t msiq_head) 2342 { 2343 CSRA_FS((caddr_t)dev_hdl, EVENT_QUEUE_HEAD, msiq_id, 2344 ENTRIES_HEAD, msiq_head); 2345 2346 return (H_EOK); 2347 } 2348 2349 uint64_t 2350 hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id, 2351 msiqtail_t *msiq_tail) 2352 { 2353 *msiq_tail = CSRA_FR((caddr_t)dev_hdl, EVENT_QUEUE_TAIL, 2354 msiq_id, ENTRIES_TAIL); 2355 2356 return (H_EOK); 2357 } 2358 2359 /* 2360 * MSI Functions: 2361 */ 2362 uint64_t 2363 hvio_msi_init(devhandle_t dev_hdl, uint64_t addr32, uint64_t addr64) 2364 { 2365 /* PCI MEM 32 resources to perform 32 bit MSI transactions */ 2366 CSRA_FS((caddr_t)dev_hdl, MSI_32_BIT_ADDRESS, 0, 2367 ADDR, (uint64_t)addr32 >> MSI_32_BIT_ADDRESS_ADDR); 2368 DBG(DBG_IB, NULL, "hvio_msiq_init: MSI_32_BIT_ADDRESS: 0x%llx\n", 2369 CSR_XR((caddr_t)dev_hdl, MSI_32_BIT_ADDRESS)); 2370 2371 /* Reserve PCI MEM 64 resources to perform 64 bit MSI transactions */ 2372 CSRA_FS((caddr_t)dev_hdl, MSI_64_BIT_ADDRESS, 0, 2373 ADDR, (uint64_t)addr64 >> MSI_64_BIT_ADDRESS_ADDR); 2374 DBG(DBG_IB, NULL, "hvio_msiq_init: MSI_64_BIT_ADDRESS: 0x%llx\n", 2375 CSR_XR((caddr_t)dev_hdl, MSI_64_BIT_ADDRESS)); 2376 2377 return (H_EOK); 2378 } 2379 2380 uint64_t 2381 hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num, 2382 msiqid_t *msiq_id) 2383 { 2384 *msiq_id = CSRA_FR((caddr_t)dev_hdl, MSI_MAPPING, 2385 msi_num, ENTRIES_EQNUM); 2386 2387 return (H_EOK); 2388 } 2389 2390 uint64_t 2391 hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num, 2392 msiqid_t msiq_id) 2393 { 2394 CSRA_FS((caddr_t)dev_hdl, MSI_MAPPING, msi_num, 2395 ENTRIES_EQNUM, msiq_id); 2396 2397 return (H_EOK); 2398 } 2399 2400 uint64_t 2401 hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num, 2402 pci_msi_valid_state_t *msi_valid_state) 2403 { 2404 *msi_valid_state = CSRA_BR((caddr_t)dev_hdl, MSI_MAPPING, 2405 msi_num, ENTRIES_V); 2406 2407 return (H_EOK); 2408 } 2409 2410 uint64_t 2411 hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num, 2412 pci_msi_valid_state_t msi_valid_state) 2413 { 2414 uint64_t ret = H_EOK; 2415 2416 switch (msi_valid_state) { 2417 case PCI_MSI_VALID: 2418 CSRA_BS((caddr_t)dev_hdl, MSI_MAPPING, msi_num, 2419 ENTRIES_V); 2420 break; 2421 case PCI_MSI_INVALID: 2422 CSRA_BC((caddr_t)dev_hdl, MSI_MAPPING, msi_num, 2423 ENTRIES_V); 2424 break; 2425 default: 2426 ret = H_EINVAL; 2427 } 2428 2429 return (ret); 2430 } 2431 2432 uint64_t 2433 hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num, 2434 pci_msi_state_t *msi_state) 2435 { 2436 *msi_state = CSRA_BR((caddr_t)dev_hdl, MSI_MAPPING, 2437 msi_num, ENTRIES_EQWR_N); 2438 2439 return (H_EOK); 2440 } 2441 2442 uint64_t 2443 hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num, 2444 pci_msi_state_t msi_state) 2445 { 2446 uint64_t ret = H_EOK; 2447 2448 switch (msi_state) { 2449 case PCI_MSI_STATE_IDLE: 2450 CSRA_BS((caddr_t)dev_hdl, MSI_CLEAR, msi_num, 2451 ENTRIES_EQWR_N); 2452 break; 2453 case PCI_MSI_STATE_DELIVERED: 2454 default: 2455 ret = H_EINVAL; 2456 break; 2457 } 2458 2459 return (ret); 2460 } 2461 2462 /* 2463 * MSG Functions: 2464 */ 2465 uint64_t 2466 hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 2467 msiqid_t *msiq_id) 2468 { 2469 uint64_t ret = H_EOK; 2470 2471 switch (msg_type) { 2472 case PCIE_PME_MSG: 2473 *msiq_id = CSR_FR((caddr_t)dev_hdl, PM_PME_MAPPING, EQNUM); 2474 break; 2475 case PCIE_PME_ACK_MSG: 2476 *msiq_id = CSR_FR((caddr_t)dev_hdl, PME_TO_ACK_MAPPING, 2477 EQNUM); 2478 break; 2479 case PCIE_CORR_MSG: 2480 *msiq_id = CSR_FR((caddr_t)dev_hdl, ERR_COR_MAPPING, EQNUM); 2481 break; 2482 case PCIE_NONFATAL_MSG: 2483 *msiq_id = CSR_FR((caddr_t)dev_hdl, ERR_NONFATAL_MAPPING, 2484 EQNUM); 2485 break; 2486 case PCIE_FATAL_MSG: 2487 *msiq_id = CSR_FR((caddr_t)dev_hdl, ERR_FATAL_MAPPING, EQNUM); 2488 break; 2489 default: 2490 ret = H_EINVAL; 2491 break; 2492 } 2493 2494 return (ret); 2495 } 2496 2497 uint64_t 2498 hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 2499 msiqid_t msiq_id) 2500 { 2501 uint64_t ret = H_EOK; 2502 2503 switch (msg_type) { 2504 case PCIE_PME_MSG: 2505 CSR_FS((caddr_t)dev_hdl, PM_PME_MAPPING, EQNUM, msiq_id); 2506 break; 2507 case PCIE_PME_ACK_MSG: 2508 CSR_FS((caddr_t)dev_hdl, PME_TO_ACK_MAPPING, EQNUM, msiq_id); 2509 break; 2510 case PCIE_CORR_MSG: 2511 CSR_FS((caddr_t)dev_hdl, ERR_COR_MAPPING, EQNUM, msiq_id); 2512 break; 2513 case PCIE_NONFATAL_MSG: 2514 CSR_FS((caddr_t)dev_hdl, ERR_NONFATAL_MAPPING, EQNUM, msiq_id); 2515 break; 2516 case PCIE_FATAL_MSG: 2517 CSR_FS((caddr_t)dev_hdl, ERR_FATAL_MAPPING, EQNUM, msiq_id); 2518 break; 2519 default: 2520 ret = H_EINVAL; 2521 break; 2522 } 2523 2524 return (ret); 2525 } 2526 2527 uint64_t 2528 hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 2529 pcie_msg_valid_state_t *msg_valid_state) 2530 { 2531 uint64_t ret = H_EOK; 2532 2533 switch (msg_type) { 2534 case PCIE_PME_MSG: 2535 *msg_valid_state = CSR_BR((caddr_t)dev_hdl, PM_PME_MAPPING, V); 2536 break; 2537 case PCIE_PME_ACK_MSG: 2538 *msg_valid_state = CSR_BR((caddr_t)dev_hdl, 2539 PME_TO_ACK_MAPPING, V); 2540 break; 2541 case PCIE_CORR_MSG: 2542 *msg_valid_state = CSR_BR((caddr_t)dev_hdl, ERR_COR_MAPPING, V); 2543 break; 2544 case PCIE_NONFATAL_MSG: 2545 *msg_valid_state = CSR_BR((caddr_t)dev_hdl, 2546 ERR_NONFATAL_MAPPING, V); 2547 break; 2548 case PCIE_FATAL_MSG: 2549 *msg_valid_state = CSR_BR((caddr_t)dev_hdl, ERR_FATAL_MAPPING, 2550 V); 2551 break; 2552 default: 2553 ret = H_EINVAL; 2554 break; 2555 } 2556 2557 return (ret); 2558 } 2559 2560 uint64_t 2561 hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 2562 pcie_msg_valid_state_t msg_valid_state) 2563 { 2564 uint64_t ret = H_EOK; 2565 2566 switch (msg_valid_state) { 2567 case PCIE_MSG_VALID: 2568 switch (msg_type) { 2569 case PCIE_PME_MSG: 2570 CSR_BS((caddr_t)dev_hdl, PM_PME_MAPPING, V); 2571 break; 2572 case PCIE_PME_ACK_MSG: 2573 CSR_BS((caddr_t)dev_hdl, PME_TO_ACK_MAPPING, V); 2574 break; 2575 case PCIE_CORR_MSG: 2576 CSR_BS((caddr_t)dev_hdl, ERR_COR_MAPPING, V); 2577 break; 2578 case PCIE_NONFATAL_MSG: 2579 CSR_BS((caddr_t)dev_hdl, ERR_NONFATAL_MAPPING, V); 2580 break; 2581 case PCIE_FATAL_MSG: 2582 CSR_BS((caddr_t)dev_hdl, ERR_FATAL_MAPPING, V); 2583 break; 2584 default: 2585 ret = H_EINVAL; 2586 break; 2587 } 2588 2589 break; 2590 case PCIE_MSG_INVALID: 2591 switch (msg_type) { 2592 case PCIE_PME_MSG: 2593 CSR_BC((caddr_t)dev_hdl, PM_PME_MAPPING, V); 2594 break; 2595 case PCIE_PME_ACK_MSG: 2596 CSR_BC((caddr_t)dev_hdl, PME_TO_ACK_MAPPING, V); 2597 break; 2598 case PCIE_CORR_MSG: 2599 CSR_BC((caddr_t)dev_hdl, ERR_COR_MAPPING, V); 2600 break; 2601 case PCIE_NONFATAL_MSG: 2602 CSR_BC((caddr_t)dev_hdl, ERR_NONFATAL_MAPPING, V); 2603 break; 2604 case PCIE_FATAL_MSG: 2605 CSR_BC((caddr_t)dev_hdl, ERR_FATAL_MAPPING, V); 2606 break; 2607 default: 2608 ret = H_EINVAL; 2609 break; 2610 } 2611 break; 2612 default: 2613 ret = H_EINVAL; 2614 } 2615 2616 return (ret); 2617 } 2618 2619 /* 2620 * Suspend/Resume Functions: 2621 * (pec, mmu, ib) 2622 * cb 2623 * Registers saved have all been touched in the XXX_init functions. 2624 */ 2625 uint64_t 2626 hvio_suspend(devhandle_t dev_hdl, pxu_t *pxu_p) 2627 { 2628 uint64_t *config_state; 2629 int total_size; 2630 int i; 2631 2632 if (msiq_suspend(dev_hdl, pxu_p) != H_EOK) 2633 return (H_EIO); 2634 2635 total_size = PEC_SIZE + MMU_SIZE + IB_SIZE + IB_MAP_SIZE; 2636 config_state = kmem_zalloc(total_size, KM_NOSLEEP); 2637 2638 if (config_state == NULL) { 2639 return (H_EIO); 2640 } 2641 2642 /* 2643 * Soft state for suspend/resume from pxu_t 2644 * uint64_t *pec_config_state; 2645 * uint64_t *mmu_config_state; 2646 * uint64_t *ib_intr_map; 2647 * uint64_t *ib_config_state; 2648 * uint64_t *xcb_config_state; 2649 */ 2650 2651 /* Save the PEC configuration states */ 2652 pxu_p->pec_config_state = config_state; 2653 for (i = 0; i < PEC_KEYS; i++) { 2654 if ((pec_config_state_regs[i].chip == PX_CHIP_TYPE(pxu_p)) || 2655 (pec_config_state_regs[i].chip == PX_CHIP_UNIDENTIFIED)) { 2656 pxu_p->pec_config_state[i] = 2657 CSR_XR((caddr_t)dev_hdl, 2658 pec_config_state_regs[i].reg); 2659 } 2660 } 2661 2662 /* Save the MMU configuration states */ 2663 pxu_p->mmu_config_state = pxu_p->pec_config_state + PEC_KEYS; 2664 for (i = 0; i < MMU_KEYS; i++) { 2665 pxu_p->mmu_config_state[i] = 2666 CSR_XR((caddr_t)dev_hdl, mmu_config_state_regs[i]); 2667 } 2668 2669 /* Save the interrupt mapping registers */ 2670 pxu_p->ib_intr_map = pxu_p->mmu_config_state + MMU_KEYS; 2671 for (i = 0; i < INTERRUPT_MAPPING_ENTRIES; i++) { 2672 pxu_p->ib_intr_map[i] = 2673 CSRA_XR((caddr_t)dev_hdl, INTERRUPT_MAPPING, i); 2674 } 2675 2676 /* Save the IB configuration states */ 2677 pxu_p->ib_config_state = pxu_p->ib_intr_map + INTERRUPT_MAPPING_ENTRIES; 2678 for (i = 0; i < IB_KEYS; i++) { 2679 pxu_p->ib_config_state[i] = 2680 CSR_XR((caddr_t)dev_hdl, ib_config_state_regs[i]); 2681 } 2682 2683 return (H_EOK); 2684 } 2685 2686 void 2687 hvio_resume(devhandle_t dev_hdl, devino_t devino, pxu_t *pxu_p) 2688 { 2689 int total_size; 2690 sysino_t sysino; 2691 int i; 2692 2693 /* Make sure that suspend actually did occur */ 2694 if (!pxu_p->pec_config_state) { 2695 return; 2696 } 2697 2698 /* Restore IB configuration states */ 2699 for (i = 0; i < IB_KEYS; i++) { 2700 CSR_XS((caddr_t)dev_hdl, ib_config_state_regs[i], 2701 pxu_p->ib_config_state[i]); 2702 } 2703 2704 /* 2705 * Restore the interrupt mapping registers 2706 * And make sure the intrs are idle. 2707 */ 2708 for (i = 0; i < INTERRUPT_MAPPING_ENTRIES; i++) { 2709 CSRA_FS((caddr_t)dev_hdl, INTERRUPT_CLEAR, i, 2710 ENTRIES_INT_STATE, INTERRUPT_IDLE_STATE); 2711 CSRA_XS((caddr_t)dev_hdl, INTERRUPT_MAPPING, i, 2712 pxu_p->ib_intr_map[i]); 2713 } 2714 2715 /* Restore MMU configuration states */ 2716 /* Clear the cache. */ 2717 CSR_XS((caddr_t)dev_hdl, MMU_TTE_CACHE_INVALIDATE, -1ull); 2718 2719 for (i = 0; i < MMU_KEYS; i++) { 2720 CSR_XS((caddr_t)dev_hdl, mmu_config_state_regs[i], 2721 pxu_p->mmu_config_state[i]); 2722 } 2723 2724 /* Restore PEC configuration states */ 2725 /* Make sure all reset bits are low until error is detected */ 2726 CSR_XS((caddr_t)dev_hdl, LPU_RESET, 0ull); 2727 2728 for (i = 0; i < PEC_KEYS; i++) { 2729 if ((pec_config_state_regs[i].chip == PX_CHIP_TYPE(pxu_p)) || 2730 (pec_config_state_regs[i].chip == PX_CHIP_UNIDENTIFIED)) { 2731 CSR_XS((caddr_t)dev_hdl, pec_config_state_regs[i].reg, 2732 pxu_p->pec_config_state[i]); 2733 } 2734 } 2735 2736 /* Enable PCI-E interrupt */ 2737 (void) hvio_intr_devino_to_sysino(dev_hdl, pxu_p, devino, &sysino); 2738 2739 (void) hvio_intr_setstate(dev_hdl, sysino, INTR_IDLE_STATE); 2740 2741 total_size = PEC_SIZE + MMU_SIZE + IB_SIZE + IB_MAP_SIZE; 2742 kmem_free(pxu_p->pec_config_state, total_size); 2743 2744 pxu_p->pec_config_state = NULL; 2745 pxu_p->mmu_config_state = NULL; 2746 pxu_p->ib_config_state = NULL; 2747 pxu_p->ib_intr_map = NULL; 2748 2749 msiq_resume(dev_hdl, pxu_p); 2750 } 2751 2752 uint64_t 2753 hvio_cb_suspend(devhandle_t dev_hdl, pxu_t *pxu_p) 2754 { 2755 uint64_t *config_state, *cb_regs; 2756 int i, cb_size, cb_keys; 2757 2758 switch (PX_CHIP_TYPE(pxu_p)) { 2759 case PX_CHIP_OBERON: 2760 cb_size = UBC_SIZE; 2761 cb_keys = UBC_KEYS; 2762 cb_regs = ubc_config_state_regs; 2763 break; 2764 case PX_CHIP_FIRE: 2765 cb_size = JBC_SIZE; 2766 cb_keys = JBC_KEYS; 2767 cb_regs = jbc_config_state_regs; 2768 break; 2769 default: 2770 DBG(DBG_CB, NULL, "hvio_cb_suspend - unknown chip type: 0x%x\n", 2771 PX_CHIP_TYPE(pxu_p)); 2772 break; 2773 } 2774 2775 config_state = kmem_zalloc(cb_size, KM_NOSLEEP); 2776 2777 if (config_state == NULL) { 2778 return (H_EIO); 2779 } 2780 2781 /* Save the configuration states */ 2782 pxu_p->xcb_config_state = config_state; 2783 for (i = 0; i < cb_keys; i++) { 2784 pxu_p->xcb_config_state[i] = 2785 CSR_XR((caddr_t)dev_hdl, cb_regs[i]); 2786 } 2787 2788 return (H_EOK); 2789 } 2790 2791 void 2792 hvio_cb_resume(devhandle_t pci_dev_hdl, devhandle_t xbus_dev_hdl, 2793 devino_t devino, pxu_t *pxu_p) 2794 { 2795 sysino_t sysino; 2796 uint64_t *cb_regs; 2797 int i, cb_size, cb_keys; 2798 2799 switch (PX_CHIP_TYPE(pxu_p)) { 2800 case PX_CHIP_OBERON: 2801 cb_size = UBC_SIZE; 2802 cb_keys = UBC_KEYS; 2803 cb_regs = ubc_config_state_regs; 2804 /* 2805 * No reason to have any reset bits high until an error is 2806 * detected on the link. 2807 */ 2808 CSR_XS((caddr_t)xbus_dev_hdl, UBC_ERROR_STATUS_CLEAR, -1ull); 2809 break; 2810 case PX_CHIP_FIRE: 2811 cb_size = JBC_SIZE; 2812 cb_keys = JBC_KEYS; 2813 cb_regs = jbc_config_state_regs; 2814 /* 2815 * No reason to have any reset bits high until an error is 2816 * detected on the link. 2817 */ 2818 CSR_XS((caddr_t)xbus_dev_hdl, JBC_ERROR_STATUS_CLEAR, -1ull); 2819 break; 2820 default: 2821 DBG(DBG_CB, NULL, "hvio_cb_resume - unknown chip type: 0x%x\n", 2822 PX_CHIP_TYPE(pxu_p)); 2823 break; 2824 } 2825 2826 ASSERT(pxu_p->xcb_config_state); 2827 2828 /* Restore the configuration states */ 2829 for (i = 0; i < cb_keys; i++) { 2830 CSR_XS((caddr_t)xbus_dev_hdl, cb_regs[i], 2831 pxu_p->xcb_config_state[i]); 2832 } 2833 2834 /* Enable XBC interrupt */ 2835 (void) hvio_intr_devino_to_sysino(pci_dev_hdl, pxu_p, devino, &sysino); 2836 2837 (void) hvio_intr_setstate(pci_dev_hdl, sysino, INTR_IDLE_STATE); 2838 2839 kmem_free(pxu_p->xcb_config_state, cb_size); 2840 2841 pxu_p->xcb_config_state = NULL; 2842 } 2843 2844 static uint64_t 2845 msiq_suspend(devhandle_t dev_hdl, pxu_t *pxu_p) 2846 { 2847 size_t bufsz; 2848 volatile uint64_t *cur_p; 2849 int i; 2850 2851 bufsz = MSIQ_STATE_SIZE + MSIQ_MAPPING_SIZE + MSIQ_OTHER_SIZE; 2852 if ((pxu_p->msiq_config_state = kmem_zalloc(bufsz, KM_NOSLEEP)) == 2853 NULL) 2854 return (H_EIO); 2855 2856 cur_p = pxu_p->msiq_config_state; 2857 2858 /* Save each EQ state */ 2859 for (i = 0; i < EVENT_QUEUE_STATE_ENTRIES; i++, cur_p++) 2860 *cur_p = CSRA_XR((caddr_t)dev_hdl, EVENT_QUEUE_STATE, i); 2861 2862 /* Save MSI mapping registers */ 2863 for (i = 0; i < MSI_MAPPING_ENTRIES; i++, cur_p++) 2864 *cur_p = CSRA_XR((caddr_t)dev_hdl, MSI_MAPPING, i); 2865 2866 /* Save all other MSIQ registers */ 2867 for (i = 0; i < MSIQ_OTHER_KEYS; i++, cur_p++) 2868 *cur_p = CSR_XR((caddr_t)dev_hdl, msiq_config_other_regs[i]); 2869 return (H_EOK); 2870 } 2871 2872 static void 2873 msiq_resume(devhandle_t dev_hdl, pxu_t *pxu_p) 2874 { 2875 size_t bufsz; 2876 uint64_t *cur_p, state; 2877 int i; 2878 2879 bufsz = MSIQ_STATE_SIZE + MSIQ_MAPPING_SIZE + MSIQ_OTHER_SIZE; 2880 cur_p = pxu_p->msiq_config_state; 2881 /* 2882 * Initialize EQ base address register and 2883 * Interrupt Mondo Data 0 register. 2884 */ 2885 (void) hvio_msiq_init(dev_hdl, pxu_p); 2886 2887 /* Restore EQ states */ 2888 for (i = 0; i < EVENT_QUEUE_STATE_ENTRIES; i++, cur_p++) { 2889 state = (*cur_p) & EVENT_QUEUE_STATE_ENTRIES_STATE_MASK; 2890 if ((state == EQ_ACTIVE_STATE) || (state == EQ_ERROR_STATE)) 2891 CSRA_BS((caddr_t)dev_hdl, EVENT_QUEUE_CONTROL_SET, 2892 i, ENTRIES_EN); 2893 } 2894 2895 /* Restore MSI mapping */ 2896 for (i = 0; i < MSI_MAPPING_ENTRIES; i++, cur_p++) 2897 CSRA_XS((caddr_t)dev_hdl, MSI_MAPPING, i, *cur_p); 2898 2899 /* 2900 * Restore all other registers. MSI 32 bit address and 2901 * MSI 64 bit address are restored as part of this. 2902 */ 2903 for (i = 0; i < MSIQ_OTHER_KEYS; i++, cur_p++) 2904 CSR_XS((caddr_t)dev_hdl, msiq_config_other_regs[i], *cur_p); 2905 2906 kmem_free(pxu_p->msiq_config_state, bufsz); 2907 pxu_p->msiq_config_state = NULL; 2908 } 2909 2910 /* 2911 * sends PME_Turn_Off message to put the link in L2/L3 ready state. 2912 * called by px_goto_l23ready. 2913 * returns DDI_SUCCESS or DDI_FAILURE 2914 */ 2915 int 2916 px_send_pme_turnoff(caddr_t csr_base) 2917 { 2918 volatile uint64_t reg; 2919 2920 reg = CSR_XR(csr_base, TLU_PME_TURN_OFF_GENERATE); 2921 /* If already pending, return failure */ 2922 if (reg & (1ull << TLU_PME_TURN_OFF_GENERATE_PTO)) { 2923 DBG(DBG_PWR, NULL, "send_pme_turnoff: pending PTO bit " 2924 "tlu_pme_turn_off_generate = %x\n", reg); 2925 return (DDI_FAILURE); 2926 } 2927 2928 /* write to PME_Turn_off reg to boradcast */ 2929 reg |= (1ull << TLU_PME_TURN_OFF_GENERATE_PTO); 2930 CSR_XS(csr_base, TLU_PME_TURN_OFF_GENERATE, reg); 2931 2932 return (DDI_SUCCESS); 2933 } 2934 2935 /* 2936 * Checks for link being in L1idle state. 2937 * Returns 2938 * DDI_SUCCESS - if the link is in L1idle 2939 * DDI_FAILURE - if the link is not in L1idle 2940 */ 2941 int 2942 px_link_wait4l1idle(caddr_t csr_base) 2943 { 2944 uint8_t ltssm_state; 2945 int ntries = px_max_l1_tries; 2946 2947 while (ntries > 0) { 2948 ltssm_state = CSR_FR(csr_base, LPU_LTSSM_STATUS1, LTSSM_STATE); 2949 if (ltssm_state == LPU_LTSSM_L1_IDLE || (--ntries <= 0)) 2950 break; 2951 delay(1); 2952 } 2953 DBG(DBG_PWR, NULL, "check_for_l1idle: ltssm_state %x\n", ltssm_state); 2954 return ((ltssm_state == LPU_LTSSM_L1_IDLE) ? DDI_SUCCESS : DDI_FAILURE); 2955 } 2956 2957 /* 2958 * Tranisition the link to L0, after it is down. 2959 */ 2960 int 2961 px_link_retrain(caddr_t csr_base) 2962 { 2963 volatile uint64_t reg; 2964 2965 reg = CSR_XR(csr_base, TLU_CONTROL); 2966 if (!(reg & (1ull << TLU_REMAIN_DETECT_QUIET))) { 2967 DBG(DBG_PWR, NULL, "retrain_link: detect.quiet bit not set\n"); 2968 return (DDI_FAILURE); 2969 } 2970 2971 /* Clear link down bit in TLU Other Event Clear Status Register. */ 2972 CSR_BS(csr_base, TLU_OTHER_EVENT_STATUS_CLEAR, LDN_P); 2973 2974 /* Clear Drain bit in TLU Status Register */ 2975 CSR_BS(csr_base, TLU_STATUS, DRAIN); 2976 2977 /* Clear Remain in Detect.Quiet bit in TLU Control Register */ 2978 reg = CSR_XR(csr_base, TLU_CONTROL); 2979 reg &= ~(1ull << TLU_REMAIN_DETECT_QUIET); 2980 CSR_XS(csr_base, TLU_CONTROL, reg); 2981 2982 return (DDI_SUCCESS); 2983 } 2984 2985 void 2986 px_enable_detect_quiet(caddr_t csr_base) 2987 { 2988 volatile uint64_t tlu_ctrl; 2989 2990 tlu_ctrl = CSR_XR(csr_base, TLU_CONTROL); 2991 tlu_ctrl |= (1ull << TLU_REMAIN_DETECT_QUIET); 2992 CSR_XS(csr_base, TLU_CONTROL, tlu_ctrl); 2993 } 2994 2995 static uint_t 2996 oberon_hp_pwron(caddr_t csr_base) 2997 { 2998 volatile uint64_t reg; 2999 boolean_t link_retry, link_up; 3000 int loop, i; 3001 3002 DBG(DBG_HP, NULL, "oberon_hp_pwron the slot\n"); 3003 3004 /* Check Leaf Reset status */ 3005 reg = CSR_XR(csr_base, ILU_ERROR_LOG_ENABLE); 3006 if (!(reg & (1ull << ILU_ERROR_LOG_ENABLE_SPARE3))) { 3007 DBG(DBG_HP, NULL, "oberon_hp_pwron fails: leaf not reset\n"); 3008 goto fail; 3009 } 3010 3011 /* Check Slot status */ 3012 reg = CSR_XR(csr_base, TLU_SLOT_STATUS); 3013 if (!(reg & (1ull << TLU_SLOT_STATUS_PSD)) || 3014 (reg & (1ull << TLU_SLOT_STATUS_MRLS))) { 3015 DBG(DBG_HP, NULL, "oberon_hp_pwron fails: slot status %lx\n", 3016 reg); 3017 goto fail; 3018 } 3019 3020 /* Blink power LED, this is done from pciehpc already */ 3021 3022 /* Turn on slot power */ 3023 CSR_BS(csr_base, HOTPLUG_CONTROL, PWREN); 3024 3025 /* power fault detection */ 3026 delay(drv_usectohz(25000)); 3027 CSR_BS(csr_base, TLU_SLOT_STATUS, PWFD); 3028 CSR_BC(csr_base, HOTPLUG_CONTROL, PWREN); 3029 3030 /* wait to check power state */ 3031 delay(drv_usectohz(25000)); 3032 3033 if (!CSR_BR(csr_base, TLU_SLOT_STATUS, PWFD)) { 3034 DBG(DBG_HP, NULL, "oberon_hp_pwron fails: power fault\n"); 3035 goto fail1; 3036 } 3037 3038 /* power is good */ 3039 CSR_BS(csr_base, HOTPLUG_CONTROL, PWREN); 3040 3041 delay(drv_usectohz(25000)); 3042 CSR_BS(csr_base, TLU_SLOT_STATUS, PWFD); 3043 CSR_BS(csr_base, TLU_SLOT_CONTROL, PWFDEN); 3044 3045 /* Turn on slot clock */ 3046 CSR_BS(csr_base, HOTPLUG_CONTROL, CLKEN); 3047 3048 link_up = B_FALSE; 3049 link_retry = B_FALSE; 3050 3051 for (loop = 0; (loop < link_retry_count) && (link_up == B_FALSE); 3052 loop++) { 3053 if (link_retry == B_TRUE) { 3054 DBG(DBG_HP, NULL, "oberon_hp_pwron : retry link loop " 3055 "%d\n", loop); 3056 CSR_BS(csr_base, TLU_CONTROL, DRN_TR_DIS); 3057 CSR_XS(csr_base, FLP_PORT_CONTROL, 0x1); 3058 delay(drv_usectohz(10000)); 3059 CSR_BC(csr_base, TLU_CONTROL, DRN_TR_DIS); 3060 CSR_BS(csr_base, TLU_DIAGNOSTIC, IFC_DIS); 3061 CSR_BC(csr_base, HOTPLUG_CONTROL, N_PERST); 3062 delay(drv_usectohz(50000)); 3063 } 3064 3065 /* Release PCI-E Reset */ 3066 delay(drv_usectohz(wait_perst)); 3067 CSR_BS(csr_base, HOTPLUG_CONTROL, N_PERST); 3068 3069 /* 3070 * Open events' mask 3071 * This should be done from pciehpc already 3072 */ 3073 3074 /* Enable PCIE port */ 3075 delay(drv_usectohz(wait_enable_port)); 3076 CSR_BS(csr_base, TLU_CONTROL, DRN_TR_DIS); 3077 CSR_XS(csr_base, FLP_PORT_CONTROL, 0x20); 3078 3079 /* wait for the link up */ 3080 for (i = 0; (i < 2) && (link_up == B_FALSE); i++) { 3081 delay(drv_usectohz(100000)); 3082 reg = CSR_XR(csr_base, DLU_LINK_LAYER_STATUS); 3083 3084 if ((((reg >> DLU_LINK_LAYER_STATUS_INIT_FC_SM_STS) & 3085 DLU_LINK_LAYER_STATUS_INIT_FC_SM_STS_MASK) == 3086 DLU_LINK_LAYER_STATUS_INIT_FC_SM_STS_FC_INIT_DONE) && 3087 (reg & (1ull << DLU_LINK_LAYER_STATUS_DLUP_STS)) && 3088 ((reg & DLU_LINK_LAYER_STATUS_LNK_STATE_MACH_STS_MASK) 3089 == 3090 DLU_LINK_LAYER_STATUS_LNK_STATE_MACH_STS_DL_ACTIVE)) { 3091 DBG(DBG_HP, NULL, "oberon_hp_pwron : link is up\n"); 3092 link_up = B_TRUE; 3093 } else 3094 link_retry = B_TRUE; 3095 } 3096 } 3097 3098 if (link_up == B_FALSE) { 3099 DBG(DBG_HP, NULL, "oberon_hp_pwron fails to enable " 3100 "PCI-E port\n"); 3101 goto fail2; 3102 } 3103 3104 /* link is up */ 3105 CSR_BC(csr_base, TLU_DIAGNOSTIC, IFC_DIS); 3106 CSR_BS(csr_base, FLP_PORT_ACTIVE_STATUS, TRAIN_ERROR); 3107 CSR_BS(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR, TE_P); 3108 CSR_BS(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR, TE_S); 3109 CSR_BC(csr_base, TLU_CONTROL, DRN_TR_DIS); 3110 3111 /* Restore LUP/LDN */ 3112 reg = CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE); 3113 if (px_tlu_oe_log_mask & (1ull << TLU_OTHER_EVENT_STATUS_SET_LUP_P)) 3114 reg |= 1ull << TLU_OTHER_EVENT_STATUS_SET_LUP_P; 3115 if (px_tlu_oe_log_mask & (1ull << TLU_OTHER_EVENT_STATUS_SET_LDN_P)) 3116 reg |= 1ull << TLU_OTHER_EVENT_STATUS_SET_LDN_P; 3117 if (px_tlu_oe_log_mask & (1ull << TLU_OTHER_EVENT_STATUS_SET_LUP_S)) 3118 reg |= 1ull << TLU_OTHER_EVENT_STATUS_SET_LUP_S; 3119 if (px_tlu_oe_log_mask & (1ull << TLU_OTHER_EVENT_STATUS_SET_LDN_S)) 3120 reg |= 1ull << TLU_OTHER_EVENT_STATUS_SET_LDN_S; 3121 CSR_XS(csr_base, TLU_OTHER_EVENT_LOG_ENABLE, reg); 3122 3123 /* 3124 * Initialize Leaf 3125 * SPLS = 00b, SPLV = 11001b, i.e. 25W 3126 */ 3127 reg = CSR_XR(csr_base, TLU_SLOT_CAPABILITIES); 3128 reg &= ~(TLU_SLOT_CAPABILITIES_SPLS_MASK << 3129 TLU_SLOT_CAPABILITIES_SPLS); 3130 reg &= ~(TLU_SLOT_CAPABILITIES_SPLV_MASK << 3131 TLU_SLOT_CAPABILITIES_SPLS); 3132 reg |= (0x19 << TLU_SLOT_CAPABILITIES_SPLS); 3133 CSR_XS(csr_base, TLU_SLOT_CAPABILITIES, reg); 3134 3135 /* Turn on Power LED */ 3136 reg = CSR_XR(csr_base, TLU_SLOT_CONTROL); 3137 reg &= ~PCIE_SLOTCTL_PWR_INDICATOR_MASK; 3138 reg = pcie_slotctl_pwr_indicator_set(reg, 3139 PCIE_SLOTCTL_INDICATOR_STATE_ON); 3140 CSR_XS(csr_base, TLU_SLOT_CONTROL, reg); 3141 3142 /* Notify to SCF */ 3143 if (CSR_BR(csr_base, HOTPLUG_CONTROL, SLOTPON)) 3144 CSR_BC(csr_base, HOTPLUG_CONTROL, SLOTPON); 3145 else 3146 CSR_BS(csr_base, HOTPLUG_CONTROL, SLOTPON); 3147 3148 return (DDI_SUCCESS); 3149 3150 fail2: 3151 /* Link up is failed */ 3152 CSR_BS(csr_base, FLP_PORT_CONTROL, PORT_DIS); 3153 CSR_BC(csr_base, HOTPLUG_CONTROL, N_PERST); 3154 delay(drv_usectohz(150)); 3155 3156 CSR_BC(csr_base, HOTPLUG_CONTROL, CLKEN); 3157 delay(drv_usectohz(100)); 3158 3159 fail1: 3160 CSR_BC(csr_base, TLU_SLOT_CONTROL, PWFDEN); 3161 3162 CSR_BC(csr_base, HOTPLUG_CONTROL, PWREN); 3163 3164 reg = CSR_XR(csr_base, TLU_SLOT_CONTROL); 3165 reg &= ~PCIE_SLOTCTL_PWR_INDICATOR_MASK; 3166 reg = pcie_slotctl_pwr_indicator_set(reg, 3167 PCIE_SLOTCTL_INDICATOR_STATE_OFF); 3168 CSR_XS(csr_base, TLU_SLOT_CONTROL, reg); 3169 3170 CSR_BC(csr_base, TLU_SLOT_STATUS, PWFD); 3171 3172 fail: 3173 return (DDI_FAILURE); 3174 } 3175 3176 static uint_t 3177 oberon_hp_pwroff(caddr_t csr_base) 3178 { 3179 volatile uint64_t reg; 3180 volatile uint64_t reg_tluue, reg_tluce; 3181 3182 DBG(DBG_HP, NULL, "oberon_hp_pwroff the slot\n"); 3183 3184 /* Blink power LED, this is done from pciehpc already */ 3185 3186 /* Clear Slot Event */ 3187 CSR_BS(csr_base, TLU_SLOT_STATUS, PSDC); 3188 CSR_BS(csr_base, TLU_SLOT_STATUS, PWFD); 3189 3190 /* DRN_TR_DIS on */ 3191 CSR_BS(csr_base, TLU_CONTROL, DRN_TR_DIS); 3192 delay(drv_usectohz(10000)); 3193 3194 /* Disable LUP/LDN */ 3195 reg = CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE); 3196 reg &= ~((1ull << TLU_OTHER_EVENT_STATUS_SET_LDN_P) | 3197 (1ull << TLU_OTHER_EVENT_STATUS_SET_LUP_P) | 3198 (1ull << TLU_OTHER_EVENT_STATUS_SET_LDN_S) | 3199 (1ull << TLU_OTHER_EVENT_STATUS_SET_LUP_S)); 3200 CSR_XS(csr_base, TLU_OTHER_EVENT_LOG_ENABLE, reg); 3201 3202 /* Save the TLU registers */ 3203 reg_tluue = CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE); 3204 reg_tluce = CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_LOG_ENABLE); 3205 /* All clear */ 3206 CSR_XS(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE, 0); 3207 CSR_XS(csr_base, TLU_CORRECTABLE_ERROR_LOG_ENABLE, 0); 3208 3209 /* Disable port */ 3210 CSR_BS(csr_base, FLP_PORT_CONTROL, PORT_DIS); 3211 3212 /* PCIE reset */ 3213 delay(drv_usectohz(10000)); 3214 CSR_BC(csr_base, HOTPLUG_CONTROL, N_PERST); 3215 3216 /* PCIE clock stop */ 3217 delay(drv_usectohz(150)); 3218 CSR_BC(csr_base, HOTPLUG_CONTROL, CLKEN); 3219 3220 /* Turn off slot power */ 3221 delay(drv_usectohz(100)); 3222 CSR_BC(csr_base, TLU_SLOT_CONTROL, PWFDEN); 3223 CSR_BC(csr_base, HOTPLUG_CONTROL, PWREN); 3224 delay(drv_usectohz(25000)); 3225 CSR_BS(csr_base, TLU_SLOT_STATUS, PWFD); 3226 3227 /* write 0 to bit 7 of ILU Error Log Enable Register */ 3228 CSR_BC(csr_base, ILU_ERROR_LOG_ENABLE, SPARE3); 3229 3230 /* Set back TLU registers */ 3231 CSR_XS(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE, reg_tluue); 3232 CSR_XS(csr_base, TLU_CORRECTABLE_ERROR_LOG_ENABLE, reg_tluce); 3233 3234 /* Power LED off */ 3235 reg = CSR_XR(csr_base, TLU_SLOT_CONTROL); 3236 reg &= ~PCIE_SLOTCTL_PWR_INDICATOR_MASK; 3237 reg = pcie_slotctl_pwr_indicator_set(reg, 3238 PCIE_SLOTCTL_INDICATOR_STATE_OFF); 3239 CSR_XS(csr_base, TLU_SLOT_CONTROL, reg); 3240 3241 /* Indicator LED blink */ 3242 reg = CSR_XR(csr_base, TLU_SLOT_CONTROL); 3243 reg &= ~PCIE_SLOTCTL_ATTN_INDICATOR_MASK; 3244 reg = pcie_slotctl_attn_indicator_set(reg, 3245 PCIE_SLOTCTL_INDICATOR_STATE_BLINK); 3246 CSR_XS(csr_base, TLU_SLOT_CONTROL, reg); 3247 3248 /* Notify to SCF */ 3249 if (CSR_BR(csr_base, HOTPLUG_CONTROL, SLOTPON)) 3250 CSR_BC(csr_base, HOTPLUG_CONTROL, SLOTPON); 3251 else 3252 CSR_BC(csr_base, HOTPLUG_CONTROL, SLOTPON); 3253 3254 /* Indicator LED off */ 3255 reg = CSR_XR(csr_base, TLU_SLOT_CONTROL); 3256 reg &= ~PCIE_SLOTCTL_ATTN_INDICATOR_MASK; 3257 reg = pcie_slotctl_attn_indicator_set(reg, 3258 PCIE_SLOTCTL_INDICATOR_STATE_OFF); 3259 CSR_XS(csr_base, TLU_SLOT_CONTROL, reg); 3260 3261 return (DDI_SUCCESS); 3262 } 3263 3264 static uint_t 3265 oberon_hpreg_get(void *cookie, off_t off) 3266 { 3267 caddr_t csr_base = *(caddr_t *)cookie; 3268 volatile uint64_t val = -1ull; 3269 3270 switch (off) { 3271 case PCIE_SLOTCAP: 3272 val = CSR_XR(csr_base, TLU_SLOT_CAPABILITIES); 3273 break; 3274 case PCIE_SLOTCTL: 3275 val = CSR_XR(csr_base, TLU_SLOT_CONTROL); 3276 3277 /* Get the power state */ 3278 val |= (CSR_XR(csr_base, HOTPLUG_CONTROL) & 3279 (1ull << HOTPLUG_CONTROL_PWREN)) ? 3280 0 : PCIE_SLOTCTL_PWR_CONTROL; 3281 break; 3282 case PCIE_SLOTSTS: 3283 val = CSR_XR(csr_base, TLU_SLOT_STATUS); 3284 break; 3285 case PCIE_LINKCAP: 3286 val = CSR_XR(csr_base, TLU_LINK_CAPABILITIES); 3287 break; 3288 case PCIE_LINKSTS: 3289 val = CSR_XR(csr_base, TLU_LINK_STATUS); 3290 break; 3291 default: 3292 DBG(DBG_HP, NULL, "oberon_hpreg_get(): " 3293 "unsupported offset 0x%lx\n", off); 3294 break; 3295 } 3296 3297 return ((uint_t)val); 3298 } 3299 3300 static uint_t 3301 oberon_hpreg_put(void *cookie, off_t off, uint_t val) 3302 { 3303 caddr_t csr_base = *(caddr_t *)cookie; 3304 volatile uint64_t pwr_state_on, pwr_fault; 3305 uint_t pwr_off, ret = DDI_SUCCESS; 3306 3307 DBG(DBG_HP, NULL, "oberon_hpreg_put 0x%lx: cur %x, new %x\n", 3308 off, oberon_hpreg_get(cookie, off), val); 3309 3310 switch (off) { 3311 case PCIE_SLOTCTL: 3312 /* 3313 * Depending on the current state, insertion or removal 3314 * will go through their respective sequences. 3315 */ 3316 pwr_state_on = CSR_BR(csr_base, HOTPLUG_CONTROL, PWREN); 3317 pwr_off = val & PCIE_SLOTCTL_PWR_CONTROL; 3318 3319 if (!pwr_off && !pwr_state_on) 3320 ret = oberon_hp_pwron(csr_base); 3321 else if (pwr_off && pwr_state_on) { 3322 pwr_fault = CSR_XR(csr_base, TLU_SLOT_STATUS) & 3323 (1ull << TLU_SLOT_STATUS_PWFD); 3324 3325 if (pwr_fault) { 3326 DBG(DBG_HP, NULL, "oberon_hpreg_put: power " 3327 "off because of power fault\n"); 3328 CSR_BC(csr_base, HOTPLUG_CONTROL, PWREN); 3329 } 3330 else 3331 ret = oberon_hp_pwroff(csr_base); 3332 } else 3333 CSR_XS(csr_base, TLU_SLOT_CONTROL, val); 3334 break; 3335 case PCIE_SLOTSTS: 3336 CSR_XS(csr_base, TLU_SLOT_STATUS, val); 3337 break; 3338 default: 3339 DBG(DBG_HP, NULL, "oberon_hpreg_put(): " 3340 "unsupported offset 0x%lx\n", off); 3341 ret = DDI_FAILURE; 3342 break; 3343 } 3344 3345 return (ret); 3346 } 3347 3348 int 3349 hvio_hotplug_init(dev_info_t *dip, void *arg) 3350 { 3351 pciehpc_regops_t *regops = (pciehpc_regops_t *)arg; 3352 px_t *px_p = DIP_TO_STATE(dip); 3353 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 3354 volatile uint64_t reg; 3355 3356 if (PX_CHIP_TYPE(pxu_p) == PX_CHIP_OBERON) { 3357 if (!CSR_BR((caddr_t)pxu_p->px_address[PX_REG_CSR], 3358 TLU_SLOT_CAPABILITIES, HP)) { 3359 DBG(DBG_HP, NULL, "%s%d: hotplug capabale not set\n", 3360 ddi_driver_name(dip), ddi_get_instance(dip)); 3361 return (DDI_FAILURE); 3362 } 3363 3364 /* For empty or disconnected slot, disable LUP/LDN */ 3365 if (!CSR_BR((caddr_t)pxu_p->px_address[PX_REG_CSR], 3366 TLU_SLOT_STATUS, PSD) || 3367 !CSR_BR((caddr_t)pxu_p->px_address[PX_REG_CSR], 3368 HOTPLUG_CONTROL, PWREN)) { 3369 3370 reg = CSR_XR((caddr_t)pxu_p->px_address[PX_REG_CSR], 3371 TLU_OTHER_EVENT_LOG_ENABLE); 3372 reg &= ~((1ull << TLU_OTHER_EVENT_STATUS_SET_LDN_P) | 3373 (1ull << TLU_OTHER_EVENT_STATUS_SET_LUP_P) | 3374 (1ull << TLU_OTHER_EVENT_STATUS_SET_LDN_S) | 3375 (1ull << TLU_OTHER_EVENT_STATUS_SET_LUP_S)); 3376 CSR_XS((caddr_t)pxu_p->px_address[PX_REG_CSR], 3377 TLU_OTHER_EVENT_LOG_ENABLE, reg); 3378 } 3379 3380 regops->get = oberon_hpreg_get; 3381 regops->put = oberon_hpreg_put; 3382 3383 /* cookie is the csr_base */ 3384 regops->cookie = (void *)&pxu_p->px_address[PX_REG_CSR]; 3385 3386 return (DDI_SUCCESS); 3387 } 3388 3389 return (DDI_ENOTSUP); 3390 } 3391 3392 int 3393 hvio_hotplug_uninit(dev_info_t *dip) 3394 { 3395 px_t *px_p = DIP_TO_STATE(dip); 3396 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 3397 3398 if (PX_CHIP_TYPE(pxu_p) == PX_CHIP_OBERON) 3399 return (DDI_SUCCESS); 3400 3401 return (DDI_FAILURE); 3402 } 3403