1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * sun4u Fire Error Handling 30 */ 31 32 #include <sys/types.h> 33 #include <sys/ddi.h> 34 #include <sys/sunddi.h> 35 #include <sys/fm/protocol.h> 36 #include <sys/fm/util.h> 37 #include <sys/pcie.h> 38 #include <sys/pcie_impl.h> 39 #include "px_obj.h" 40 #include <px_regs.h> 41 #include <px_csr.h> 42 #include <sys/membar.h> 43 #include <sys/machcpuvar.h> 44 #include <sys/platform_module.h> 45 #include "pcie_pwr.h" 46 #include "px_lib4u.h" 47 #include "px_err.h" 48 #include "px_err_impl.h" 49 #include "oberon_regs.h" 50 51 uint64_t px_tlu_ue_intr_mask = PX_ERR_EN_ALL; 52 uint64_t px_tlu_ue_log_mask = PX_ERR_EN_ALL; 53 uint64_t px_tlu_ue_count_mask = PX_ERR_EN_ALL; 54 55 uint64_t px_tlu_ce_intr_mask = PX_ERR_MASK_NONE; 56 uint64_t px_tlu_ce_log_mask = PX_ERR_MASK_NONE; 57 uint64_t px_tlu_ce_count_mask = PX_ERR_MASK_NONE; 58 59 /* 60 * Do not enable Link Interrupts 61 */ 62 uint64_t px_tlu_oe_intr_mask = PX_ERR_EN_ALL & ~0x80000000800; 63 uint64_t px_tlu_oe_log_mask = PX_ERR_EN_ALL & ~0x80000000800; 64 uint64_t px_tlu_oe_count_mask = PX_ERR_EN_ALL; 65 66 uint64_t px_mmu_intr_mask = PX_ERR_EN_ALL; 67 uint64_t px_mmu_log_mask = PX_ERR_EN_ALL; 68 uint64_t px_mmu_count_mask = PX_ERR_EN_ALL; 69 70 uint64_t px_imu_intr_mask = PX_ERR_EN_ALL; 71 uint64_t px_imu_log_mask = PX_ERR_EN_ALL; 72 uint64_t px_imu_count_mask = PX_ERR_EN_ALL; 73 74 /* 75 * (1ull << ILU_INTERRUPT_ENABLE_IHB_PE_S) | 76 * (1ull << ILU_INTERRUPT_ENABLE_IHB_PE_P); 77 */ 78 uint64_t px_ilu_intr_mask = (((uint64_t)0x10 << 32) | 0x10); 79 uint64_t px_ilu_log_mask = (((uint64_t)0x10 << 32) | 0x10); 80 uint64_t px_ilu_count_mask = PX_ERR_EN_ALL; 81 82 uint64_t px_ubc_intr_mask = PX_ERR_EN_ALL; 83 uint64_t px_ubc_log_mask = PX_ERR_EN_ALL; 84 uint64_t px_ubc_count_mask = PX_ERR_EN_ALL; 85 86 uint64_t px_jbc_intr_mask = PX_ERR_EN_ALL; 87 uint64_t px_jbc_log_mask = PX_ERR_EN_ALL; 88 uint64_t px_jbc_count_mask = PX_ERR_EN_ALL; 89 90 /* 91 * LPU Intr Registers are reverse encoding from the registers above. 92 * 1 = disable 93 * 0 = enable 94 * 95 * Log and Count are however still the same. 96 */ 97 uint64_t px_lpul_intr_mask = LPU_INTR_DISABLE; 98 uint64_t px_lpul_log_mask = PX_ERR_EN_ALL; 99 uint64_t px_lpul_count_mask = PX_ERR_EN_ALL; 100 101 uint64_t px_lpup_intr_mask = LPU_INTR_DISABLE; 102 uint64_t px_lpup_log_mask = PX_ERR_EN_ALL; 103 uint64_t px_lpup_count_mask = PX_ERR_EN_ALL; 104 105 uint64_t px_lpur_intr_mask = LPU_INTR_DISABLE; 106 uint64_t px_lpur_log_mask = PX_ERR_EN_ALL; 107 uint64_t px_lpur_count_mask = PX_ERR_EN_ALL; 108 109 uint64_t px_lpux_intr_mask = LPU_INTR_DISABLE; 110 uint64_t px_lpux_log_mask = PX_ERR_EN_ALL; 111 uint64_t px_lpux_count_mask = PX_ERR_EN_ALL; 112 113 uint64_t px_lpus_intr_mask = LPU_INTR_DISABLE; 114 uint64_t px_lpus_log_mask = PX_ERR_EN_ALL; 115 uint64_t px_lpus_count_mask = PX_ERR_EN_ALL; 116 117 uint64_t px_lpug_intr_mask = LPU_INTR_DISABLE; 118 uint64_t px_lpug_log_mask = PX_ERR_EN_ALL; 119 uint64_t px_lpug_count_mask = PX_ERR_EN_ALL; 120 121 /* 122 * JBC error bit table 123 */ 124 #define JBC_BIT_DESC(bit, hdl, erpt) \ 125 JBC_INTERRUPT_STATUS_ ## bit ## _P, \ 126 0, \ 127 PX_ERR_BIT_HANDLE(hdl), \ 128 PX_ERPT_SEND(erpt), \ 129 PX_ERR_JBC_CLASS(bit) }, \ 130 { JBC_INTERRUPT_STATUS_ ## bit ## _S, \ 131 0, \ 132 PX_ERR_BIT_HANDLE(hdl), \ 133 PX_ERPT_SEND(erpt), \ 134 PX_ERR_JBC_CLASS(bit) 135 px_err_bit_desc_t px_err_jbc_tbl[] = { 136 /* JBC FATAL - see io erpt doc, section 1.1 */ 137 { JBC_BIT_DESC(MB_PEA, fatal_hw, jbc_fatal) }, 138 { JBC_BIT_DESC(CPE, fatal_hw, jbc_fatal) }, 139 { JBC_BIT_DESC(APE, fatal_hw, jbc_fatal) }, 140 { JBC_BIT_DESC(PIO_CPE, fatal_hw, jbc_fatal) }, 141 { JBC_BIT_DESC(JTCEEW, fatal_hw, jbc_fatal) }, 142 { JBC_BIT_DESC(JTCEEI, fatal_hw, jbc_fatal) }, 143 { JBC_BIT_DESC(JTCEER, fatal_hw, jbc_fatal) }, 144 145 /* JBC MERGE - see io erpt doc, section 1.2 */ 146 { JBC_BIT_DESC(MB_PER, jbc_merge, jbc_merge) }, 147 { JBC_BIT_DESC(MB_PEW, jbc_merge, jbc_merge) }, 148 149 /* JBC Jbusint IN - see io erpt doc, section 1.3 */ 150 { JBC_BIT_DESC(UE_ASYN, fatal_gos, jbc_in) }, 151 { JBC_BIT_DESC(CE_ASYN, non_fatal, jbc_in) }, 152 { JBC_BIT_DESC(JTE, fatal_gos, jbc_in) }, 153 { JBC_BIT_DESC(JBE, jbc_jbusint_in, jbc_in) }, 154 { JBC_BIT_DESC(JUE, jbc_jbusint_in, jbc_in) }, 155 { JBC_BIT_DESC(ICISE, fatal_gos, jbc_in) }, 156 { JBC_BIT_DESC(WR_DPE, jbc_jbusint_in, jbc_in) }, 157 { JBC_BIT_DESC(RD_DPE, jbc_jbusint_in, jbc_in) }, 158 { JBC_BIT_DESC(ILL_BMW, jbc_jbusint_in, jbc_in) }, 159 { JBC_BIT_DESC(ILL_BMR, jbc_jbusint_in, jbc_in) }, 160 { JBC_BIT_DESC(BJC, jbc_jbusint_in, jbc_in) }, 161 162 /* JBC Jbusint Out - see io erpt doc, section 1.4 */ 163 { JBC_BIT_DESC(IJP, fatal_gos, jbc_out) }, 164 165 /* 166 * JBC Dmcint ODCD - see io erpt doc, section 1.5 167 * 168 * Error bits which can be set via a bad PCItool access go through 169 * jbc_safe_acc instead. 170 */ 171 { JBC_BIT_DESC(PIO_UNMAP_RD, jbc_safe_acc, jbc_odcd) }, 172 { JBC_BIT_DESC(ILL_ACC_RD, jbc_safe_acc, jbc_odcd) }, 173 { JBC_BIT_DESC(PIO_UNMAP, jbc_safe_acc, jbc_odcd) }, 174 { JBC_BIT_DESC(PIO_DPE, jbc_dmcint_odcd, jbc_odcd) }, 175 { JBC_BIT_DESC(PIO_CPE, non_fatal, jbc_odcd) }, 176 { JBC_BIT_DESC(ILL_ACC, jbc_safe_acc, jbc_odcd) }, 177 178 /* JBC Dmcint IDC - see io erpt doc, section 1.6 */ 179 { JBC_BIT_DESC(UNSOL_RD, non_fatal, jbc_idc) }, 180 { JBC_BIT_DESC(UNSOL_INTR, non_fatal, jbc_idc) }, 181 182 /* JBC CSR - see io erpt doc, section 1.7 */ 183 { JBC_BIT_DESC(EBUS_TO, jbc_csr, jbc_csr) } 184 }; 185 186 #define px_err_jbc_keys \ 187 (sizeof (px_err_jbc_tbl)) / (sizeof (px_err_bit_desc_t)) 188 189 /* 190 * UBC error bit table 191 */ 192 #define UBC_BIT_DESC(bit, hdl, erpt) \ 193 UBC_INTERRUPT_STATUS_ ## bit ## _P, \ 194 0, \ 195 PX_ERR_BIT_HANDLE(hdl), \ 196 PX_ERPT_SEND(erpt), \ 197 PX_ERR_UBC_CLASS(bit) }, \ 198 { UBC_INTERRUPT_STATUS_ ## bit ## _S, \ 199 0, \ 200 PX_ERR_BIT_HANDLE(hdl), \ 201 PX_ERPT_SEND(erpt), \ 202 PX_ERR_UBC_CLASS(bit) 203 px_err_bit_desc_t px_err_ubc_tbl[] = { 204 /* UBC FATAL */ 205 { UBC_BIT_DESC(DMARDUEA, non_fatal, ubc_fatal) }, 206 { UBC_BIT_DESC(DMAWTUEA, fatal_sw, ubc_fatal) }, 207 { UBC_BIT_DESC(MEMRDAXA, fatal_sw, ubc_fatal) }, 208 { UBC_BIT_DESC(MEMWTAXA, fatal_sw, ubc_fatal) }, 209 { UBC_BIT_DESC(DMARDUEB, non_fatal, ubc_fatal) }, 210 { UBC_BIT_DESC(DMAWTUEB, fatal_sw, ubc_fatal) }, 211 { UBC_BIT_DESC(MEMRDAXB, fatal_sw, ubc_fatal) }, 212 { UBC_BIT_DESC(MEMWTAXB, fatal_sw, ubc_fatal) }, 213 { UBC_BIT_DESC(PIOWTUE, fatal_sw, ubc_fatal) }, 214 { UBC_BIT_DESC(PIOWBEUE, fatal_sw, ubc_fatal) }, 215 { UBC_BIT_DESC(PIORBEUE, fatal_sw, ubc_fatal) } 216 }; 217 218 #define px_err_ubc_keys \ 219 (sizeof (px_err_ubc_tbl)) / (sizeof (px_err_bit_desc_t)) 220 221 222 char *ubc_class_eid_qualifier[] = { 223 "-mem", 224 "-channel", 225 "-cpu", 226 "-path" 227 }; 228 229 230 /* 231 * DMC error bit tables 232 */ 233 #define IMU_BIT_DESC(bit, hdl, erpt) \ 234 IMU_INTERRUPT_STATUS_ ## bit ## _P, \ 235 0, \ 236 PX_ERR_BIT_HANDLE(hdl), \ 237 PX_ERPT_SEND(erpt), \ 238 PX_ERR_DMC_CLASS(bit) }, \ 239 { IMU_INTERRUPT_STATUS_ ## bit ## _S, \ 240 0, \ 241 PX_ERR_BIT_HANDLE(hdl), \ 242 PX_ERPT_SEND(erpt), \ 243 PX_ERR_DMC_CLASS(bit) 244 px_err_bit_desc_t px_err_imu_tbl[] = { 245 /* DMC IMU RDS - see io erpt doc, section 2.1 */ 246 { IMU_BIT_DESC(MSI_MAL_ERR, non_fatal, imu_rds) }, 247 { IMU_BIT_DESC(MSI_PAR_ERR, fatal_stuck, imu_rds) }, 248 { IMU_BIT_DESC(PMEACK_MES_NOT_EN, imu_rbne, imu_rds) }, 249 { IMU_BIT_DESC(PMPME_MES_NOT_EN, imu_pme, imu_rds) }, 250 { IMU_BIT_DESC(FATAL_MES_NOT_EN, imu_rbne, imu_rds) }, 251 { IMU_BIT_DESC(NONFATAL_MES_NOT_EN, imu_rbne, imu_rds) }, 252 { IMU_BIT_DESC(COR_MES_NOT_EN, imu_rbne, imu_rds) }, 253 { IMU_BIT_DESC(MSI_NOT_EN, imu_rbne, imu_rds) }, 254 255 /* DMC IMU SCS - see io erpt doc, section 2.2 */ 256 { IMU_BIT_DESC(EQ_NOT_EN, imu_rbne, imu_rds) }, 257 258 /* DMC IMU - see io erpt doc, section 2.3 */ 259 { IMU_BIT_DESC(EQ_OVER, imu_eq_ovfl, imu) } 260 }; 261 262 #define px_err_imu_keys (sizeof (px_err_imu_tbl)) / (sizeof (px_err_bit_desc_t)) 263 264 /* mmu errors */ 265 #define MMU_BIT_DESC(bit, hdl, erpt) \ 266 MMU_INTERRUPT_STATUS_ ## bit ## _P, \ 267 0, \ 268 PX_ERR_BIT_HANDLE(hdl), \ 269 PX_ERPT_SEND(erpt), \ 270 PX_ERR_DMC_CLASS(bit) }, \ 271 { MMU_INTERRUPT_STATUS_ ## bit ## _S, \ 272 0, \ 273 PX_ERR_BIT_HANDLE(hdl), \ 274 PX_ERPT_SEND(erpt), \ 275 PX_ERR_DMC_CLASS(bit) 276 px_err_bit_desc_t px_err_mmu_tbl[] = { 277 /* DMC MMU TFAR/TFSR - see io erpt doc, section 2.4 */ 278 { MMU_BIT_DESC(BYP_ERR, mmu_rbne, mmu_tfar_tfsr) }, 279 { MMU_BIT_DESC(BYP_OOR, mmu_tfa, mmu_tfar_tfsr) }, 280 { MMU_BIT_DESC(TRN_ERR, mmu_rbne, mmu_tfar_tfsr) }, 281 { MMU_BIT_DESC(TRN_OOR, mmu_tfa, mmu_tfar_tfsr) }, 282 { MMU_BIT_DESC(TTE_INV, mmu_tfa, mmu_tfar_tfsr) }, 283 { MMU_BIT_DESC(TTE_PRT, mmu_tfa, mmu_tfar_tfsr) }, 284 { MMU_BIT_DESC(TTC_DPE, mmu_tfa, mmu_tfar_tfsr) }, 285 { MMU_BIT_DESC(TBW_DME, mmu_tblwlk, mmu_tfar_tfsr) }, 286 { MMU_BIT_DESC(TBW_UDE, mmu_tblwlk, mmu_tfar_tfsr) }, 287 { MMU_BIT_DESC(TBW_ERR, mmu_tblwlk, mmu_tfar_tfsr) }, 288 { MMU_BIT_DESC(TBW_DPE, mmu_tblwlk, mmu_tfar_tfsr) }, 289 290 /* DMC MMU - see io erpt doc, section 2.5 */ 291 { MMU_BIT_DESC(TTC_CAE, non_fatal, mmu) } 292 }; 293 #define px_err_mmu_keys (sizeof (px_err_mmu_tbl)) / (sizeof (px_err_bit_desc_t)) 294 295 296 /* 297 * PEC error bit tables 298 */ 299 #define ILU_BIT_DESC(bit, hdl, erpt) \ 300 ILU_INTERRUPT_STATUS_ ## bit ## _P, \ 301 0, \ 302 PX_ERR_BIT_HANDLE(hdl), \ 303 PX_ERPT_SEND(erpt), \ 304 PX_ERR_PEC_CLASS(bit) }, \ 305 { ILU_INTERRUPT_STATUS_ ## bit ## _S, \ 306 0, \ 307 PX_ERR_BIT_HANDLE(hdl), \ 308 PX_ERPT_SEND(erpt), \ 309 PX_ERR_PEC_CLASS(bit) 310 px_err_bit_desc_t px_err_ilu_tbl[] = { 311 /* PEC ILU none - see io erpt doc, section 3.1 */ 312 { ILU_BIT_DESC(IHB_PE, fatal_gos, pec_ilu) } 313 }; 314 #define px_err_ilu_keys \ 315 (sizeof (px_err_ilu_tbl)) / (sizeof (px_err_bit_desc_t)) 316 317 /* 318 * PEC UE errors implementation is incomplete pending PCIE generic 319 * fabric rules. Must handle both PRIMARY and SECONDARY errors. 320 */ 321 /* pec ue errors */ 322 #define TLU_UC_BIT_DESC(bit, hdl, erpt) \ 323 TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _P, \ 324 0, \ 325 PX_ERR_BIT_HANDLE(hdl), \ 326 PX_ERPT_SEND(erpt), \ 327 PX_ERR_PEC_CLASS(bit) }, \ 328 { TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _S, \ 329 0, \ 330 PX_ERR_BIT_HANDLE(hdl), \ 331 PX_ERPT_SEND(erpt), \ 332 PX_ERR_PEC_CLASS(bit) 333 #define TLU_UC_OB_BIT_DESC(bit, hdl, erpt) \ 334 TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _P, \ 335 0, \ 336 PX_ERR_BIT_HANDLE(hdl), \ 337 PX_ERPT_SEND(erpt), \ 338 PX_ERR_PEC_OB_CLASS(bit) }, \ 339 { TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _S, \ 340 0, \ 341 PX_ERR_BIT_HANDLE(hdl), \ 342 PX_ERPT_SEND(erpt), \ 343 PX_ERR_PEC_CLASS(bit) 344 px_err_bit_desc_t px_err_tlu_ue_tbl[] = { 345 /* PCI-E Receive Uncorrectable Errors - see io erpt doc, section 3.2 */ 346 { TLU_UC_BIT_DESC(UR, pciex_ue, pciex_rx_ue) }, 347 { TLU_UC_BIT_DESC(UC, pciex_ue, pciex_rx_ue) }, 348 349 /* PCI-E Transmit Uncorrectable Errors - see io erpt doc, section 3.3 */ 350 { TLU_UC_OB_BIT_DESC(ECRC, pciex_ue, pciex_rx_ue) }, 351 { TLU_UC_BIT_DESC(CTO, pciex_ue, pciex_tx_ue) }, 352 { TLU_UC_BIT_DESC(ROF, pciex_ue, pciex_tx_ue) }, 353 354 /* PCI-E Rx/Tx Uncorrectable Errors - see io erpt doc, section 3.4 */ 355 { TLU_UC_BIT_DESC(MFP, pciex_ue, pciex_rx_tx_ue) }, 356 { TLU_UC_BIT_DESC(PP, pciex_ue, pciex_rx_tx_ue) }, 357 358 /* Other PCI-E Uncorrectable Errors - see io erpt doc, section 3.5 */ 359 { TLU_UC_BIT_DESC(FCP, pciex_ue, pciex_ue) }, 360 { TLU_UC_BIT_DESC(DLP, pciex_ue, pciex_ue) }, 361 { TLU_UC_BIT_DESC(TE, pciex_ue, pciex_ue) }, 362 363 /* Not used */ 364 { TLU_UC_BIT_DESC(CA, pciex_ue, do_not) } 365 }; 366 #define px_err_tlu_ue_keys \ 367 (sizeof (px_err_tlu_ue_tbl)) / (sizeof (px_err_bit_desc_t)) 368 369 370 /* 371 * PEC CE errors implementation is incomplete pending PCIE generic 372 * fabric rules. 373 */ 374 /* pec ce errors */ 375 #define TLU_CE_BIT_DESC(bit, hdl, erpt) \ 376 TLU_CORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _P, \ 377 0, \ 378 PX_ERR_BIT_HANDLE(hdl), \ 379 PX_ERPT_SEND(erpt), \ 380 PX_ERR_PEC_CLASS(bit) }, \ 381 { TLU_CORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _S, \ 382 0, \ 383 PX_ERR_BIT_HANDLE(hdl), \ 384 PX_ERPT_SEND(erpt), \ 385 PX_ERR_PEC_CLASS(bit) 386 px_err_bit_desc_t px_err_tlu_ce_tbl[] = { 387 /* PCI-E Correctable Errors - see io erpt doc, section 3.6 */ 388 { TLU_CE_BIT_DESC(RTO, pciex_ce, pciex_ce) }, 389 { TLU_CE_BIT_DESC(RNR, pciex_ce, pciex_ce) }, 390 { TLU_CE_BIT_DESC(BDP, pciex_ce, pciex_ce) }, 391 { TLU_CE_BIT_DESC(BTP, pciex_ce, pciex_ce) }, 392 { TLU_CE_BIT_DESC(RE, pciex_ce, pciex_ce) } 393 }; 394 #define px_err_tlu_ce_keys \ 395 (sizeof (px_err_tlu_ce_tbl)) / (sizeof (px_err_bit_desc_t)) 396 397 398 /* pec oe errors */ 399 #define TLU_OE_BIT_DESC(bit, hdl, erpt) \ 400 TLU_OTHER_EVENT_STATUS_CLEAR_ ## bit ## _P, \ 401 0, \ 402 PX_ERR_BIT_HANDLE(hdl), \ 403 PX_ERPT_SEND(erpt), \ 404 PX_ERR_PEC_CLASS(bit) }, \ 405 { TLU_OTHER_EVENT_STATUS_CLEAR_ ## bit ## _S, \ 406 0, \ 407 PX_ERR_BIT_HANDLE(hdl), \ 408 PX_ERPT_SEND(erpt), \ 409 PX_ERR_PEC_CLASS(bit) 410 #define TLU_OE_OB_BIT_DESC(bit, hdl, erpt) \ 411 TLU_OTHER_EVENT_STATUS_CLEAR_ ## bit ## _P, \ 412 0, \ 413 PX_ERR_BIT_HANDLE(hdl), \ 414 PX_ERPT_SEND(erpt), \ 415 PX_ERR_PEC_OB_CLASS(bit) }, \ 416 { TLU_OTHER_EVENT_STATUS_CLEAR_ ## bit ## _S, \ 417 0, \ 418 PX_ERR_BIT_HANDLE(hdl), \ 419 PX_ERPT_SEND(erpt), \ 420 PX_ERR_PEC_OB_CLASS(bit) 421 px_err_bit_desc_t px_err_tlu_oe_tbl[] = { 422 /* 423 * TLU Other Event Status (receive only) - see io erpt doc, section 3.7 424 */ 425 { TLU_OE_BIT_DESC(MRC, fatal_hw, pciex_rx_oe) }, 426 427 /* TLU Other Event Status (rx + tx) - see io erpt doc, section 3.8 */ 428 { TLU_OE_BIT_DESC(WUC, non_fatal, pciex_rx_tx_oe) }, 429 { TLU_OE_BIT_DESC(RUC, non_fatal, pciex_rx_tx_oe) }, 430 { TLU_OE_BIT_DESC(CRS, non_fatal, pciex_rx_tx_oe) }, 431 432 /* TLU Other Event - see io erpt doc, section 3.9 */ 433 { TLU_OE_BIT_DESC(IIP, fatal_gos, pciex_oe) }, 434 { TLU_OE_BIT_DESC(EDP, fatal_gos, pciex_oe) }, 435 { TLU_OE_BIT_DESC(EHP, fatal_gos, pciex_oe) }, 436 { TLU_OE_OB_BIT_DESC(TLUEITMO, fatal_gos, pciex_oe) }, 437 { TLU_OE_BIT_DESC(LIN, non_fatal, pciex_oe) }, 438 { TLU_OE_BIT_DESC(LRS, non_fatal, pciex_oe) }, 439 { TLU_OE_BIT_DESC(LDN, tlu_ldn, pciex_oe) }, 440 { TLU_OE_BIT_DESC(LUP, tlu_lup, pciex_oe) }, 441 { TLU_OE_BIT_DESC(ERU, fatal_gos, pciex_oe) }, 442 { TLU_OE_BIT_DESC(ERO, fatal_gos, pciex_oe) }, 443 { TLU_OE_BIT_DESC(EMP, fatal_gos, pciex_oe) }, 444 { TLU_OE_BIT_DESC(EPE, fatal_gos, pciex_oe) }, 445 { TLU_OE_BIT_DESC(ERP, fatal_gos, pciex_oe) }, 446 { TLU_OE_BIT_DESC(EIP, fatal_gos, pciex_oe) } 447 }; 448 449 #define px_err_tlu_oe_keys \ 450 (sizeof (px_err_tlu_oe_tbl)) / (sizeof (px_err_bit_desc_t)) 451 452 453 /* 454 * All the following tables below are for LPU Interrupts. These interrupts 455 * are *NOT* error interrupts, but event status interrupts. 456 * 457 * These events are probably of most interest to: 458 * o Hotplug 459 * o Power Management 460 * o etc... 461 * 462 * There are also a few events that would be interresting for FMA. 463 * Again none of the regiseters below state that an error has occured 464 * or that data has been lost. If anything, they give status that an 465 * error is *about* to occur. examples 466 * o INT_SKP_ERR - indicates clock between fire and child is too far 467 * off and is most unlikely able to compensate 468 * o INT_TX_PAR_ERR - A parity error occured in ONE lane. This is 469 * HW recoverable, but will like end up as a future 470 * fabric error as well. 471 * 472 * For now, we don't care about any of these errors and should be ignore, 473 * but cleared. 474 */ 475 476 /* LPU Link Interrupt Table */ 477 #define LPUL_BIT_DESC(bit, hdl, erpt) \ 478 LPU_LINK_LAYER_INTERRUPT_AND_STATUS_INT_ ## bit, \ 479 0, \ 480 NULL, \ 481 NULL, \ 482 "" 483 px_err_bit_desc_t px_err_lpul_tbl[] = { 484 { LPUL_BIT_DESC(LINK_ERR_ACT, NULL, NULL) } 485 }; 486 #define px_err_lpul_keys \ 487 (sizeof (px_err_lpul_tbl)) / (sizeof (px_err_bit_desc_t)) 488 489 /* LPU Physical Interrupt Table */ 490 #define LPUP_BIT_DESC(bit, hdl, erpt) \ 491 LPU_PHY_LAYER_INTERRUPT_AND_STATUS_INT_ ## bit, \ 492 0, \ 493 NULL, \ 494 NULL, \ 495 "" 496 px_err_bit_desc_t px_err_lpup_tbl[] = { 497 { LPUP_BIT_DESC(PHY_LAYER_ERR, NULL, NULL) } 498 }; 499 #define px_err_lpup_keys \ 500 (sizeof (px_err_lpup_tbl)) / (sizeof (px_err_bit_desc_t)) 501 502 /* LPU Receive Interrupt Table */ 503 #define LPUR_BIT_DESC(bit, hdl, erpt) \ 504 LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS_INT_ ## bit, \ 505 0, \ 506 NULL, \ 507 NULL, \ 508 "" 509 px_err_bit_desc_t px_err_lpur_tbl[] = { 510 { LPUR_BIT_DESC(RCV_PHY, NULL, NULL) } 511 }; 512 #define px_err_lpur_keys \ 513 (sizeof (px_err_lpur_tbl)) / (sizeof (px_err_bit_desc_t)) 514 515 /* LPU Transmit Interrupt Table */ 516 #define LPUX_BIT_DESC(bit, hdl, erpt) \ 517 LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS_INT_ ## bit, \ 518 0, \ 519 NULL, \ 520 NULL, \ 521 "" 522 px_err_bit_desc_t px_err_lpux_tbl[] = { 523 { LPUX_BIT_DESC(UNMSK, NULL, NULL) } 524 }; 525 #define px_err_lpux_keys \ 526 (sizeof (px_err_lpux_tbl)) / (sizeof (px_err_bit_desc_t)) 527 528 /* LPU LTSSM Interrupt Table */ 529 #define LPUS_BIT_DESC(bit, hdl, erpt) \ 530 LPU_LTSSM_INTERRUPT_AND_STATUS_INT_ ## bit, \ 531 0, \ 532 NULL, \ 533 NULL, \ 534 "" 535 px_err_bit_desc_t px_err_lpus_tbl[] = { 536 { LPUS_BIT_DESC(ANY, NULL, NULL) } 537 }; 538 #define px_err_lpus_keys \ 539 (sizeof (px_err_lpus_tbl)) / (sizeof (px_err_bit_desc_t)) 540 541 /* LPU Gigablaze Glue Interrupt Table */ 542 #define LPUG_BIT_DESC(bit, hdl, erpt) \ 543 LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS_INT_ ## bit, \ 544 0, \ 545 NULL, \ 546 NULL, \ 547 "" 548 px_err_bit_desc_t px_err_lpug_tbl[] = { 549 { LPUG_BIT_DESC(GLOBL_UNMSK, NULL, NULL) } 550 }; 551 #define px_err_lpug_keys \ 552 (sizeof (px_err_lpug_tbl)) / (sizeof (px_err_bit_desc_t)) 553 554 555 /* Mask and Tables */ 556 #define MnT6(pre) \ 557 B_FALSE, \ 558 &px_ ## pre ## _intr_mask, \ 559 &px_ ## pre ## _log_mask, \ 560 &px_ ## pre ## _count_mask, \ 561 px_err_ ## pre ## _tbl, \ 562 px_err_ ## pre ## _keys, \ 563 0 564 565 #define MnT6_ob(pre) \ 566 B_FALSE, \ 567 &px_ ## pre ## _intr_mask, \ 568 &px_ ## pre ## _log_mask, \ 569 &px_ ## pre ## _count_mask, \ 570 px_err_ ## pre ## _ob_tbl, \ 571 px_err_ ## pre ## _ob_keys, \ 572 0 573 574 /* LPU Registers Addresses */ 575 #define LR4(pre) \ 576 NULL, \ 577 LPU_ ## pre ## _INTERRUPT_MASK, \ 578 LPU_ ## pre ## _INTERRUPT_AND_STATUS, \ 579 LPU_ ## pre ## _INTERRUPT_AND_STATUS 580 581 /* LPU Registers Addresses with Irregularities */ 582 #define LR4_FIXME(pre) \ 583 NULL, \ 584 LPU_ ## pre ## _INTERRUPT_MASK, \ 585 LPU_ ## pre ## _LAYER_INTERRUPT_AND_STATUS, \ 586 LPU_ ## pre ## _LAYER_INTERRUPT_AND_STATUS 587 588 /* TLU Registers Addresses */ 589 #define TR4(pre) \ 590 TLU_ ## pre ## _LOG_ENABLE, \ 591 TLU_ ## pre ## _INTERRUPT_ENABLE, \ 592 TLU_ ## pre ## _INTERRUPT_STATUS, \ 593 TLU_ ## pre ## _STATUS_CLEAR 594 595 /* Registers Addresses for JBC, UBC, MMU, IMU and ILU */ 596 #define R4(pre) \ 597 pre ## _ERROR_LOG_ENABLE, \ 598 pre ## _INTERRUPT_ENABLE, \ 599 pre ## _INTERRUPT_STATUS, \ 600 pre ## _ERROR_STATUS_CLEAR 601 602 /* 603 * Register error handling tables. 604 * The ID Field (first field) is identified by an enum px_err_id_t. 605 * It is located in px_err.h 606 */ 607 px_err_reg_desc_t px_err_reg_tbl[] = { 608 { MnT6(jbc), R4(JBC), "JBC Error"}, 609 { MnT6(ubc), R4(UBC), "UBC Error"}, 610 { MnT6(mmu), R4(MMU), "MMU Error"}, 611 { MnT6(imu), R4(IMU), "IMU Error"}, 612 { MnT6(tlu_ue), TR4(UNCORRECTABLE_ERROR), "TLU UE"}, 613 { MnT6(tlu_ce), TR4(CORRECTABLE_ERROR), "TLU CE"}, 614 { MnT6(tlu_oe), TR4(OTHER_EVENT), "TLU OE"}, 615 { MnT6(ilu), R4(ILU), "ILU Error"}, 616 { MnT6(lpul), LR4(LINK_LAYER), "LPU Link Layer"}, 617 { MnT6(lpup), LR4_FIXME(PHY), "LPU Phy Layer"}, 618 { MnT6(lpur), LR4(RECEIVE_PHY), "LPU RX Phy Layer"}, 619 { MnT6(lpux), LR4(TRANSMIT_PHY), "LPU TX Phy Layer"}, 620 { MnT6(lpus), LR4(LTSSM), "LPU LTSSM"}, 621 { MnT6(lpug), LR4(GIGABLAZE_GLUE), "LPU GigaBlaze Glue"}, 622 }; 623 #define PX_ERR_REG_KEYS (sizeof (px_err_reg_tbl)) / (sizeof (px_err_reg_tbl[0])) 624 625 typedef struct px_err_ss { 626 uint64_t err_status[PX_ERR_REG_KEYS]; 627 } px_err_ss_t; 628 629 static void px_err_snapshot(px_t *px_p, px_err_ss_t *ss, boolean_t chk_cb); 630 static int px_err_erpt_and_clr(px_t *px_p, ddi_fm_error_t *derr, 631 px_err_ss_t *ss); 632 static int px_err_check_severity(px_t *px_p, ddi_fm_error_t *derr, 633 int err, int caller); 634 635 /* 636 * px_err_cb_intr: 637 * Interrupt handler for the JBC/UBC block. 638 * o lock 639 * o create derr 640 * o px_err_handle(leaf1, with cb) 641 * o px_err_handle(leaf2, without cb) 642 * o dispatch (leaf1) 643 * o dispatch (leaf2) 644 * o unlock 645 * o handle error: fatal? fm_panic() : return INTR_CLAIMED) 646 */ 647 uint_t 648 px_err_cb_intr(caddr_t arg) 649 { 650 px_fault_t *px_fault_p = (px_fault_t *)arg; 651 dev_info_t *rpdip = px_fault_p->px_fh_dip; 652 px_t *px_p = DIP_TO_STATE(rpdip); 653 int err = PX_OK; 654 int ret = DDI_FM_OK; 655 int fatal = 0; 656 ddi_fm_error_t derr; 657 658 /* Create the derr */ 659 bzero(&derr, sizeof (ddi_fm_error_t)); 660 derr.fme_version = DDI_FME_VERSION; 661 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 662 derr.fme_flag = DDI_FM_ERR_UNEXPECTED; 663 664 mutex_enter(&px_p->px_fm_mutex); 665 666 err |= px_err_handle(px_p, &derr, PX_INTR_CALL, B_TRUE); 667 668 ret = ndi_fm_handler_dispatch(rpdip, NULL, &derr); 669 switch (ret) { 670 case DDI_FM_FATAL: 671 fatal++; 672 break; 673 case DDI_FM_NONFATAL: 674 case DDI_FM_UNKNOWN: 675 default: 676 break; 677 } 678 679 /* Set the intr state to idle for the leaf that received the mondo */ 680 681 (void) px_lib_intr_setstate(rpdip, px_fault_p->px_fh_sysino, 682 INTR_IDLE_STATE); 683 684 mutex_exit(&px_p->px_fm_mutex); 685 686 /* 687 * PX_FATAL_HW error is diagnosed after system recovered from 688 * HW initiated reset, therefore no furthur handling is required. 689 */ 690 if (fatal || err & (PX_FATAL_GOS | PX_FATAL_SW)) 691 PX_FM_PANIC("Fatal System Bus Error has occurred\n"); 692 693 return (DDI_INTR_CLAIMED); 694 } 695 696 /* 697 * px_err_dmc_pec_intr: 698 * Interrupt handler for the DMC/PEC block. 699 * o lock 700 * o create derr 701 * o px_err_handle(leaf, with cb) 702 * o dispatch (leaf) 703 * o unlock 704 * o handle error: fatal? fm_panic() : return INTR_CLAIMED) 705 */ 706 uint_t 707 px_err_dmc_pec_intr(caddr_t arg) 708 { 709 px_fault_t *px_fault_p = (px_fault_t *)arg; 710 dev_info_t *rpdip = px_fault_p->px_fh_dip; 711 px_t *px_p = DIP_TO_STATE(rpdip); 712 int err = PX_OK; 713 int ret = DDI_FM_OK; 714 ddi_fm_error_t derr; 715 716 /* Create the derr */ 717 bzero(&derr, sizeof (ddi_fm_error_t)); 718 derr.fme_version = DDI_FME_VERSION; 719 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 720 derr.fme_flag = DDI_FM_ERR_UNEXPECTED; 721 722 mutex_enter(&px_p->px_fm_mutex); 723 724 /* send ereport/handle/clear fire registers */ 725 err |= px_err_handle(px_p, &derr, PX_INTR_CALL, B_TRUE); 726 727 /* Check all child devices for errors */ 728 ret = ndi_fm_handler_dispatch(rpdip, NULL, &derr); 729 730 /* Set the interrupt state to idle */ 731 (void) px_lib_intr_setstate(rpdip, px_fault_p->px_fh_sysino, 732 INTR_IDLE_STATE); 733 734 mutex_exit(&px_p->px_fm_mutex); 735 736 /* 737 * PX_FATAL_HW indicates a condition recovered from Fatal-Reset, 738 * therefore it does not cause panic. 739 */ 740 if ((err & (PX_FATAL_GOS | PX_FATAL_SW)) || (ret == DDI_FM_FATAL)) 741 PX_FM_PANIC("Fatal System Port Error has occurred\n"); 742 743 return (DDI_INTR_CLAIMED); 744 } 745 746 /* 747 * Error register are being handled by px_hlib xxx_init functions. 748 * They are also called again by px_err_add_intr for mondo62 and 63 749 * from px_cb_attach and px_attach 750 */ 751 void 752 px_err_reg_enable(px_t *px_p, px_err_id_t id) 753 { 754 px_err_reg_desc_t *reg_desc = &px_err_reg_tbl[id]; 755 uint64_t intr_mask = *reg_desc->intr_mask_p; 756 uint64_t log_mask = *reg_desc->log_mask_p; 757 caddr_t csr_base; 758 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 759 760 /* Get the correct CSR BASE */ 761 if (PX_ERR_XBC(id)) 762 csr_base = (caddr_t)pxu_p->px_address[PX_REG_XBC]; 763 else 764 csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 765 766 reg_desc->enabled = B_TRUE; 767 768 /* Enable logs if it exists */ 769 if (reg_desc->log_addr != NULL) 770 CSR_XS(csr_base, reg_desc->log_addr, log_mask); 771 772 /* 773 * For readability you in code you set 1 to enable an interrupt. 774 * But in Fire it's backwards. You set 1 to *disable* an intr. 775 * Reverse the user tunable intr mask field. 776 * 777 * Disable All Errors 778 * Clear All Errors 779 * Enable Errors 780 */ 781 CSR_XS(csr_base, reg_desc->enable_addr, 0); 782 CSR_XS(csr_base, reg_desc->clear_addr, -1); 783 CSR_XS(csr_base, reg_desc->enable_addr, intr_mask); 784 DBG(DBG_ATTACH, NULL, "%s Mask: 0x%llx\n", 785 reg_desc->msg, CSR_XR(csr_base, reg_desc->enable_addr)); 786 DBG(DBG_ATTACH, NULL, "%s Status: 0x%llx\n", 787 reg_desc->msg, CSR_XR(csr_base, reg_desc->status_addr)); 788 DBG(DBG_ATTACH, NULL, "%s Clear: 0x%llx\n", 789 reg_desc->msg, CSR_XR(csr_base, reg_desc->clear_addr)); 790 if (reg_desc->log_addr != NULL) { 791 DBG(DBG_ATTACH, NULL, "%s Log: 0x%llx\n", 792 reg_desc->msg, CSR_XR(csr_base, reg_desc->log_addr)); 793 } 794 } 795 796 void 797 px_err_reg_disable(px_t *px_p, px_err_id_t id) 798 { 799 px_err_reg_desc_t *reg_desc = &px_err_reg_tbl[id]; 800 caddr_t csr_base; 801 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 802 803 /* Get the correct CSR BASE */ 804 if (PX_ERR_XBC(id)) 805 csr_base = (caddr_t)(uintptr_t)pxu_p->px_address[PX_REG_XBC]; 806 else 807 csr_base = (caddr_t)(uintptr_t)pxu_p->px_address[PX_REG_CSR]; 808 809 reg_desc->enabled = B_FALSE; 810 811 switch (id) { 812 case PX_ERR_JBC: 813 case PX_ERR_UBC: 814 case PX_ERR_MMU: 815 case PX_ERR_IMU: 816 case PX_ERR_TLU_UE: 817 case PX_ERR_TLU_CE: 818 case PX_ERR_TLU_OE: 819 case PX_ERR_ILU: 820 if (reg_desc->log_addr != NULL) { 821 CSR_XS(csr_base, reg_desc->log_addr, 0); 822 } 823 CSR_XS(csr_base, reg_desc->enable_addr, 0); 824 break; 825 case PX_ERR_LPU_LINK: 826 case PX_ERR_LPU_PHY: 827 case PX_ERR_LPU_RX: 828 case PX_ERR_LPU_TX: 829 case PX_ERR_LPU_LTSSM: 830 case PX_ERR_LPU_GIGABLZ: 831 if (reg_desc->log_addr != NULL) { 832 CSR_XS(csr_base, reg_desc->log_addr, -1); 833 } 834 CSR_XS(csr_base, reg_desc->enable_addr, -1); 835 break; 836 } 837 } 838 839 /* 840 * px_err_handle: 841 * Common function called by trap, mondo and fabric intr. 842 * o Snap shot current fire registers 843 * o check for safe access 844 * o send ereport and clear snap shot registers 845 * o check severity of snap shot registers 846 * 847 * @param px_p leaf in which to check access 848 * @param derr fm err data structure to be updated 849 * @param caller PX_TRAP_CALL | PX_INTR_CALL 850 * @param chk_cb whether to handle cb registers 851 * @return err PX_OK | PX_NONFATAL | 852 * PX_FATAL_GOS | PX_FATAL_HW | PX_STUCK_FATAL 853 */ 854 int 855 px_err_handle(px_t *px_p, ddi_fm_error_t *derr, int caller, 856 boolean_t chk_cb) 857 { 858 px_err_ss_t ss; 859 int err = PX_OK; 860 861 ASSERT(MUTEX_HELD(&px_p->px_fm_mutex)); 862 863 /* snap shot the current fire registers */ 864 px_err_snapshot(px_p, &ss, chk_cb); 865 866 /* check for safe access */ 867 px_err_safeacc_check(px_p, derr); 868 869 /* send ereports/handle/clear registers */ 870 err = px_err_erpt_and_clr(px_p, derr, &ss); 871 872 /* check for error severity */ 873 err = px_err_check_severity(px_p, derr, err, caller); 874 875 /* Mark the On Trap Handle if an error occured */ 876 if (err != PX_OK) { 877 px_pec_t *pec_p = px_p->px_pec_p; 878 on_trap_data_t *otd = pec_p->pec_ontrap_data; 879 880 if ((otd != NULL) && (otd->ot_prot & OT_DATA_ACCESS)) 881 otd->ot_trap |= OT_DATA_ACCESS; 882 } 883 884 return (err); 885 } 886 887 /* 888 * Static function 889 */ 890 891 /* 892 * px_err_snapshot: 893 * Take a current snap shot of all the fire error registers. This includes 894 * JBC/UBC, DMC, and PEC, unless chk_cb == false; 895 * 896 * @param px_p leaf in which to take the snap shot. 897 * @param ss pre-allocated memory to store the snap shot. 898 * @param chk_cb boolean on whether to store jbc/ubc register. 899 */ 900 static void 901 px_err_snapshot(px_t *px_p, px_err_ss_t *ss, boolean_t chk_cb) 902 { 903 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 904 caddr_t xbc_csr_base = (caddr_t)pxu_p->px_address[PX_REG_XBC]; 905 caddr_t pec_csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 906 px_err_reg_desc_t *reg_desc; 907 int reg_id; 908 909 switch (PX_CHIP_TYPE(pxu_p)) { 910 case PX_CHIP_OBERON: 911 reg_id = PX_ERR_UBC; 912 break; 913 case PX_CHIP_FIRE: 914 reg_id = PX_ERR_JBC; 915 break; 916 default: 917 DBG(DBG_ERR_INTR, NULL, "px_err_snapshot - " 918 "unknown chip type: 0x%x\n", PX_CHIP_TYPE(pxu_p)); 919 reg_id = 0; 920 break; 921 } 922 923 /* snapshot CB interrupt status */ 924 if (chk_cb == B_TRUE) { 925 reg_desc = &px_err_reg_tbl[reg_id]; 926 /* Only look at enabled groups. */ 927 if (reg_desc->enabled == B_TRUE) { 928 ss->err_status[reg_id] = CSR_XR(xbc_csr_base, 929 reg_desc->status_addr); 930 } 931 } else { 932 ss->err_status[reg_id] = 0; 933 } 934 935 /* snapshot DMC/PEC interrupt status */ 936 for (reg_id = 2; reg_id < PX_ERR_REG_KEYS; reg_id += 1) { 937 reg_desc = &px_err_reg_tbl[reg_id]; 938 /* Only look at enabled groups. */ 939 if (reg_desc->enabled == B_TRUE) { 940 ss->err_status[reg_id] = CSR_XR(pec_csr_base, 941 reg_desc->status_addr); 942 } 943 } 944 } 945 946 /* 947 * px_err_erpt_and_clr: 948 * This function does the following thing to all the fire registers based 949 * on an earlier snap shot. 950 * o Send ereport 951 * o Handle the error 952 * o Clear the error 953 * 954 * @param px_p leaf in which to take the snap shot. 955 * @param derr fm err in which the ereport is to be based on 956 * @param ss pre-allocated memory to store the snap shot. 957 */ 958 static int 959 px_err_erpt_and_clr(px_t *px_p, ddi_fm_error_t *derr, px_err_ss_t *ss) 960 { 961 dev_info_t *rpdip = px_p->px_dip; 962 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 963 caddr_t csr_base; 964 px_err_reg_desc_t *err_reg_tbl; 965 px_err_bit_desc_t *err_bit_tbl; 966 px_err_bit_desc_t *err_bit_desc; 967 968 uint64_t *log_mask, *count_mask; 969 uint64_t status_addr, clear_addr; 970 uint64_t ss_reg; 971 972 int (*err_handler)(); 973 int (*erpt_handler)(); 974 int reg_id, key; 975 int err = PX_OK; 976 int biterr; 977 978 ASSERT(MUTEX_HELD(&px_p->px_fm_mutex)); 979 980 /* send erport/handle/clear JBC errors */ 981 for (reg_id = 0; reg_id < PX_ERR_REG_KEYS; reg_id += 1) { 982 /* Get the correct register description table */ 983 err_reg_tbl = &px_err_reg_tbl[reg_id]; 984 985 /* Only look at enabled groups. */ 986 if (err_reg_tbl->enabled != B_TRUE) 987 continue; 988 989 /* Get the correct CSR BASE */ 990 if (PX_ERR_XBC(reg_id)) 991 csr_base = (caddr_t)pxu_p->px_address[PX_REG_XBC]; 992 else 993 csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 994 995 /* Get pointers to masks and register addresses */ 996 log_mask = err_reg_tbl->log_mask_p; 997 count_mask = err_reg_tbl->count_mask_p; 998 status_addr = err_reg_tbl->status_addr; 999 clear_addr = err_reg_tbl->clear_addr; 1000 ss_reg = ss->err_status[reg_id]; 1001 1002 /* Get the register BIT description table */ 1003 err_bit_tbl = err_reg_tbl->err_bit_tbl; 1004 1005 /* For each known bit in the register send erpt and handle */ 1006 for (key = 0; key < err_reg_tbl->err_bit_keys; key += 1) { 1007 /* Get the bit description table for this register */ 1008 err_bit_desc = &err_bit_tbl[key]; 1009 1010 /* 1011 * If the ss_reg is set for this bit, 1012 * send ereport and handle 1013 */ 1014 if (BIT_TST(ss_reg, err_bit_desc->bit)) { 1015 /* Increment the counter if necessary */ 1016 if (BIT_TST(*count_mask, err_bit_desc->bit)) { 1017 err_bit_desc->counter++; 1018 } 1019 1020 /* Error Handle for this bit */ 1021 err_handler = err_bit_desc->err_handler; 1022 if (err_handler) { 1023 biterr = err_handler(rpdip, 1024 csr_base, 1025 derr, 1026 err_reg_tbl, 1027 err_bit_desc); 1028 err |= biterr; 1029 } 1030 1031 /* Send the ereport if it's an UNEXPECTED err */ 1032 erpt_handler = err_bit_desc->erpt_handler; 1033 if ((derr->fme_flag == DDI_FM_ERR_UNEXPECTED) && 1034 (biterr != PX_OK)) { 1035 if (erpt_handler) 1036 (void) erpt_handler(rpdip, 1037 csr_base, 1038 ss_reg, 1039 derr, 1040 err_bit_desc->bit, 1041 err_bit_desc->class_name); 1042 } 1043 } 1044 } 1045 /* Print register status */ 1046 if (ss_reg & *log_mask) 1047 DBG(DBG_ERR_INTR, rpdip, "<%x>=%16llx %s\n", 1048 status_addr, ss_reg, err_reg_tbl->msg); 1049 1050 /* Clear the register and error */ 1051 CSR_XS(csr_base, clear_addr, ss_reg); 1052 } 1053 1054 return (err); 1055 } 1056 1057 /* 1058 * px_err_check_severity: 1059 * Check the severity of the fire error based on an earlier snapshot 1060 * 1061 * @param px_p leaf in which to take the snap shot. 1062 * @param derr fm err in which the ereport is to be based on 1063 * @param ss pre-allocated memory to store the snap shot. 1064 */ 1065 static int 1066 px_err_check_severity(px_t *px_p, ddi_fm_error_t *derr, int err, int caller) 1067 { 1068 px_pec_t *pec_p = px_p->px_pec_p; 1069 boolean_t is_safeacc = B_FALSE; 1070 1071 /* nothing to do if called with no error */ 1072 if (err == PX_OK) 1073 return (err); 1074 1075 /* Cautious access error handling */ 1076 switch (derr->fme_flag) { 1077 case DDI_FM_ERR_EXPECTED: 1078 if (caller == PX_TRAP_CALL) { 1079 /* 1080 * for ddi_caut_get treat all events as nonfatal 1081 * The trampoline will set err_ena = 0, 1082 * err_status = NONFATAL. 1083 */ 1084 derr->fme_status = DDI_FM_NONFATAL; 1085 is_safeacc = B_TRUE; 1086 } else { 1087 /* 1088 * For ddi_caut_put treat all events as nonfatal. Here 1089 * we have the handle and can call ndi_fm_acc_err_set(). 1090 */ 1091 derr->fme_status = DDI_FM_NONFATAL; 1092 ndi_fm_acc_err_set(pec_p->pec_acc_hdl, derr); 1093 is_safeacc = B_TRUE; 1094 } 1095 break; 1096 case DDI_FM_ERR_PEEK: 1097 case DDI_FM_ERR_POKE: 1098 /* 1099 * For ddi_peek/poke treat all events as nonfatal. 1100 */ 1101 is_safeacc = B_TRUE; 1102 break; 1103 default: 1104 is_safeacc = B_FALSE; 1105 } 1106 1107 /* 1108 * The third argument "err" is passed in as error status from checking 1109 * Fire register, re-adjust error status from safe access. 1110 */ 1111 if (is_safeacc && !(err & PX_FATAL_GOS)) 1112 return (PX_NONFATAL); 1113 1114 return (err); 1115 } 1116 1117 /* predefined convenience functions */ 1118 /* ARGSUSED */ 1119 int 1120 px_err_fatal_hw_handle(dev_info_t *rpdip, caddr_t csr_base, 1121 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1122 px_err_bit_desc_t *err_bit_descr) 1123 { 1124 return (PX_FATAL_HW); 1125 } 1126 1127 /* ARGSUSED */ 1128 int 1129 px_err_fatal_gos_handle(dev_info_t *rpdip, caddr_t csr_base, 1130 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1131 px_err_bit_desc_t *err_bit_descr) 1132 { 1133 return (PX_FATAL_GOS); 1134 } 1135 1136 /* ARGSUSED */ 1137 int 1138 px_err_fatal_stuck_handle(dev_info_t *rpdip, caddr_t csr_base, 1139 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1140 px_err_bit_desc_t *err_bit_descr) 1141 { 1142 return (PX_STUCK_FATAL); 1143 } 1144 1145 /* ARGSUSED */ 1146 int 1147 px_err_fatal_sw_handle(dev_info_t *rpdip, caddr_t csr_base, 1148 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1149 px_err_bit_desc_t *err_bit_descr) 1150 { 1151 return (PX_FATAL_SW); 1152 } 1153 1154 /* ARGSUSED */ 1155 int 1156 px_err_non_fatal_handle(dev_info_t *rpdip, caddr_t csr_base, 1157 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1158 px_err_bit_desc_t *err_bit_descr) 1159 { 1160 return (PX_NONFATAL); 1161 } 1162 1163 /* ARGSUSED */ 1164 int 1165 px_err_ok_handle(dev_info_t *rpdip, caddr_t csr_base, ddi_fm_error_t *derr, 1166 px_err_reg_desc_t *err_reg_descr, px_err_bit_desc_t *err_bit_descr) 1167 { 1168 return (PX_OK); 1169 } 1170 1171 /* ARGSUSED */ 1172 int 1173 px_err_unknown_handle(dev_info_t *rpdip, caddr_t csr_base, ddi_fm_error_t *derr, 1174 px_err_reg_desc_t *err_reg_descr, px_err_bit_desc_t *err_bit_descr) 1175 { 1176 return (PX_ERR_UNKNOWN); 1177 } 1178 1179 /* ARGSUSED */ 1180 PX_ERPT_SEND_DEC(do_not) 1181 { 1182 return (PX_OK); 1183 } 1184 1185 /* UBC FATAL - see io erpt doc, section 1.1 */ 1186 /* ARGSUSED */ 1187 PX_ERPT_SEND_DEC(ubc_fatal) 1188 { 1189 char buf[FM_MAX_CLASS]; 1190 uint64_t memory_ue_log, marked; 1191 char unum[FM_MAX_CLASS]; 1192 int unum_length; 1193 uint64_t device_id = 0; 1194 uint8_t cpu_version = 0; 1195 nvlist_t *resource = NULL; 1196 1197 unum[0] = '\0'; 1198 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1199 1200 memory_ue_log = CSR_XR(csr_base, UBC_MEMORY_UE_LOG); 1201 marked = (memory_ue_log >> UBC_MEMORY_UE_LOG_MARKED) & 1202 UBC_MEMORY_UE_LOG_MARKED_MASK; 1203 1204 if ((strstr(class_name, "ubc.piowtue") != NULL) || 1205 (strstr(class_name, "ubc.piowbeue") != NULL) || 1206 (strstr(class_name, "ubc.piorbeue") != NULL) || 1207 (strstr(class_name, "ubc.dmarduea") != NULL) || 1208 (strstr(class_name, "ubc.dmardueb") != NULL)) { 1209 int eid = (memory_ue_log >> UBC_MEMORY_UE_LOG_EID) & 1210 UBC_MEMORY_UE_LOG_EID_MASK; 1211 (void) strncat(buf, ubc_class_eid_qualifier[eid], 1212 FM_MAX_CLASS); 1213 1214 if (eid == UBC_EID_MEM) { 1215 uint64_t phys_addr = memory_ue_log & 1216 MMU_OBERON_PADDR_MASK; 1217 uint64_t offset = (uint64_t)-1; 1218 1219 resource = fm_nvlist_create(NULL); 1220 if (&plat_get_mem_unum) { 1221 if ((plat_get_mem_unum(0, 1222 phys_addr, 0, B_TRUE, 0, unum, 1223 FM_MAX_CLASS, &unum_length)) != 0) 1224 unum[0] = '\0'; 1225 } 1226 fm_fmri_mem_set(resource, FM_MEM_SCHEME_VERSION, 1227 NULL, unum, NULL, offset); 1228 1229 } else if (eid == UBC_EID_CPU) { 1230 int cpuid = (marked & UBC_MARKED_MAX_CPUID_MASK); 1231 char sbuf[21]; /* sizeof (UINT64_MAX) + '\0' */ 1232 1233 resource = fm_nvlist_create(NULL); 1234 cpu_version = cpunodes[cpuid].version; 1235 device_id = cpunodes[cpuid].device_id; 1236 (void) snprintf(sbuf, sizeof (sbuf), "%lX", 1237 device_id); 1238 (void) fm_fmri_cpu_set(resource, 1239 FM_CPU_SCHEME_VERSION, NULL, cpuid, 1240 &cpu_version, sbuf); 1241 } 1242 } 1243 1244 if (resource) { 1245 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1246 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1247 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1248 OBERON_UBC_ELE, DATA_TYPE_UINT64, 1249 CSR_XR(csr_base, UBC_ERROR_LOG_ENABLE), 1250 OBERON_UBC_IE, DATA_TYPE_UINT64, 1251 CSR_XR(csr_base, UBC_INTERRUPT_ENABLE), 1252 OBERON_UBC_IS, DATA_TYPE_UINT64, 1253 CSR_XR(csr_base, UBC_INTERRUPT_STATUS), 1254 OBERON_UBC_ESS, DATA_TYPE_UINT64, 1255 CSR_XR(csr_base, UBC_ERROR_STATUS_SET), 1256 OBERON_UBC_MUE, DATA_TYPE_UINT64, memory_ue_log, 1257 OBERON_UBC_UNUM, DATA_TYPE_STRING, unum, 1258 OBERON_UBC_DID, DATA_TYPE_UINT64, device_id, 1259 OBERON_UBC_CPUV, DATA_TYPE_UINT32, cpu_version, 1260 OBERON_UBC_RESOURCE, DATA_TYPE_NVLIST, resource, 1261 NULL); 1262 fm_nvlist_destroy(resource, FM_NVA_FREE); 1263 } else { 1264 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1265 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1266 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1267 OBERON_UBC_ELE, DATA_TYPE_UINT64, 1268 CSR_XR(csr_base, UBC_ERROR_LOG_ENABLE), 1269 OBERON_UBC_IE, DATA_TYPE_UINT64, 1270 CSR_XR(csr_base, UBC_INTERRUPT_ENABLE), 1271 OBERON_UBC_IS, DATA_TYPE_UINT64, 1272 CSR_XR(csr_base, UBC_INTERRUPT_STATUS), 1273 OBERON_UBC_ESS, DATA_TYPE_UINT64, 1274 CSR_XR(csr_base, UBC_ERROR_STATUS_SET), 1275 OBERON_UBC_MUE, DATA_TYPE_UINT64, memory_ue_log, 1276 OBERON_UBC_UNUM, DATA_TYPE_STRING, unum, 1277 OBERON_UBC_DID, DATA_TYPE_UINT64, device_id, 1278 OBERON_UBC_CPUV, DATA_TYPE_UINT32, cpu_version, 1279 NULL); 1280 } 1281 1282 return (PX_OK); 1283 } 1284 1285 /* JBC FATAL - see io erpt doc, section 1.1 */ 1286 PX_ERPT_SEND_DEC(jbc_fatal) 1287 { 1288 char buf[FM_MAX_CLASS]; 1289 boolean_t pri = PX_ERR_IS_PRI(bit); 1290 1291 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1292 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1293 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1294 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1295 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1296 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1297 FIRE_JBC_IE, DATA_TYPE_UINT64, 1298 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1299 FIRE_JBC_IS, DATA_TYPE_UINT64, 1300 ss_reg, 1301 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1302 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1303 FIRE_JBC_FEL1, DATA_TYPE_UINT64, 1304 CSR_XR(csr_base, FATAL_ERROR_LOG_1), 1305 FIRE_JBC_FEL2, DATA_TYPE_UINT64, 1306 CSR_XR(csr_base, FATAL_ERROR_LOG_2), 1307 NULL); 1308 1309 return (PX_OK); 1310 } 1311 1312 /* JBC MERGE - see io erpt doc, section 1.2 */ 1313 PX_ERPT_SEND_DEC(jbc_merge) 1314 { 1315 char buf[FM_MAX_CLASS]; 1316 boolean_t pri = PX_ERR_IS_PRI(bit); 1317 1318 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1319 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1320 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1321 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1322 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1323 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1324 FIRE_JBC_IE, DATA_TYPE_UINT64, 1325 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1326 FIRE_JBC_IS, DATA_TYPE_UINT64, 1327 ss_reg, 1328 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1329 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1330 FIRE_JBC_MTEL, DATA_TYPE_UINT64, 1331 CSR_XR(csr_base, MERGE_TRANSACTION_ERROR_LOG), 1332 NULL); 1333 1334 return (PX_OK); 1335 } 1336 1337 /* 1338 * JBC Merge buffer nonfatal errors: 1339 * Merge buffer parity error (rd_buf): dma:read:M:nonfatal 1340 * Merge buffer parity error (wr_buf): dma:write:M:nonfatal 1341 */ 1342 /* ARGSUSED */ 1343 int 1344 px_err_jbc_merge_handle(dev_info_t *rpdip, caddr_t csr_base, 1345 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1346 px_err_bit_desc_t *err_bit_descr) 1347 { 1348 boolean_t pri = PX_ERR_IS_PRI(err_bit_descr->bit); 1349 uint64_t paddr; 1350 int ret; 1351 1352 if (!pri) 1353 return (PX_FATAL_GOS); 1354 1355 paddr = CSR_XR(csr_base, MERGE_TRANSACTION_ERROR_LOG); 1356 paddr &= MERGE_TRANSACTION_ERROR_LOG_ADDRESS_MASK; 1357 1358 ret = px_handle_lookup( 1359 rpdip, DMA_HANDLE, derr->fme_ena, (void *)paddr); 1360 1361 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1362 } 1363 1364 /* JBC Jbusint IN - see io erpt doc, section 1.3 */ 1365 PX_ERPT_SEND_DEC(jbc_in) 1366 { 1367 char buf[FM_MAX_CLASS]; 1368 boolean_t pri = PX_ERR_IS_PRI(bit); 1369 1370 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1371 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1372 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1373 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1374 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1375 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1376 FIRE_JBC_IE, DATA_TYPE_UINT64, 1377 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1378 FIRE_JBC_IS, DATA_TYPE_UINT64, 1379 ss_reg, 1380 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1381 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1382 FIRE_JBC_JITEL1, DATA_TYPE_UINT64, 1383 CSR_XR(csr_base, JBCINT_IN_TRANSACTION_ERROR_LOG), 1384 FIRE_JBC_JITEL2, DATA_TYPE_UINT64, 1385 CSR_XR(csr_base, JBCINT_IN_TRANSACTION_ERROR_LOG_2), 1386 NULL); 1387 1388 return (PX_OK); 1389 } 1390 1391 /* 1392 * JBC Jbusint IN nonfatal errors: PA logged in Jbusint In Transaction Error 1393 * Log Reg[42:0]. 1394 * CE async fault error: nonfatal 1395 * Jbus bus error: dma::nonfatal 1396 * Jbus unmapped error: pio|dma:rdwr:M:nonfatal 1397 * Write data parity error: pio/write:M:nonfatal 1398 * Read data parity error: pio/read:M:nonfatal 1399 * Illegal NCWR bytemask: pio:write:M:nonfatal 1400 * Illegal NCRD bytemask: pio:write:M:nonfatal 1401 * Invalid jbus transaction: nonfatal 1402 */ 1403 /* ARGSUSED */ 1404 int 1405 px_err_jbc_jbusint_in_handle(dev_info_t *rpdip, caddr_t csr_base, 1406 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1407 px_err_bit_desc_t *err_bit_descr) 1408 { 1409 boolean_t pri = PX_ERR_IS_PRI(err_bit_descr->bit); 1410 uint64_t paddr; 1411 int ret; 1412 1413 if (!pri) 1414 return (PX_FATAL_GOS); 1415 1416 paddr = CSR_XR(csr_base, JBCINT_IN_TRANSACTION_ERROR_LOG); 1417 paddr &= JBCINT_IN_TRANSACTION_ERROR_LOG_ADDRESS_MASK; 1418 1419 ret = px_handle_lookup( 1420 rpdip, DMA_HANDLE, derr->fme_ena, (void *)paddr); 1421 1422 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1423 } 1424 1425 1426 /* JBC Jbusint Out - see io erpt doc, section 1.4 */ 1427 PX_ERPT_SEND_DEC(jbc_out) 1428 { 1429 char buf[FM_MAX_CLASS]; 1430 boolean_t pri = PX_ERR_IS_PRI(bit); 1431 1432 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1433 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1434 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1435 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1436 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1437 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1438 FIRE_JBC_IE, DATA_TYPE_UINT64, 1439 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1440 FIRE_JBC_IS, DATA_TYPE_UINT64, 1441 ss_reg, 1442 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1443 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1444 FIRE_JBC_JOTEL1, DATA_TYPE_UINT64, 1445 CSR_XR(csr_base, JBCINT_OUT_TRANSACTION_ERROR_LOG), 1446 FIRE_JBC_JOTEL2, DATA_TYPE_UINT64, 1447 CSR_XR(csr_base, JBCINT_OUT_TRANSACTION_ERROR_LOG_2), 1448 NULL); 1449 1450 return (PX_OK); 1451 } 1452 1453 /* JBC Dmcint ODCD - see io erpt doc, section 1.5 */ 1454 PX_ERPT_SEND_DEC(jbc_odcd) 1455 { 1456 char buf[FM_MAX_CLASS]; 1457 boolean_t pri = PX_ERR_IS_PRI(bit); 1458 1459 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1460 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1461 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1462 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1463 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1464 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1465 FIRE_JBC_IE, DATA_TYPE_UINT64, 1466 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1467 FIRE_JBC_IS, DATA_TYPE_UINT64, 1468 ss_reg, 1469 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1470 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1471 FIRE_JBC_DMC_ODCD, DATA_TYPE_UINT64, 1472 CSR_XR(csr_base, DMCINT_ODCD_ERROR_LOG), 1473 NULL); 1474 1475 return (PX_OK); 1476 } 1477 1478 /* 1479 * JBC Dmcint ODCO nonfatal errer handling - 1480 * PIO data parity error: pio:write:M:nonfatal 1481 */ 1482 /* ARGSUSED */ 1483 int 1484 px_err_jbc_dmcint_odcd_handle(dev_info_t *rpdip, caddr_t csr_base, 1485 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1486 px_err_bit_desc_t *err_bit_descr) 1487 { 1488 boolean_t pri = PX_ERR_IS_PRI(err_bit_descr->bit); 1489 uint64_t paddr; 1490 int ret; 1491 1492 if (!pri) 1493 return (PX_FATAL_GOS); 1494 1495 paddr = CSR_XR(csr_base, DMCINT_ODCD_ERROR_LOG); 1496 paddr &= DMCINT_ODCD_ERROR_LOG_ADDRESS_MASK; 1497 1498 ret = px_handle_lookup( 1499 rpdip, DMA_HANDLE, derr->fme_ena, (void *)paddr); 1500 1501 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1502 } 1503 1504 /* Does address in DMCINT error log register match address of pcitool access? */ 1505 static boolean_t 1506 px_jbc_pcitool_addr_match(dev_info_t *rpdip, caddr_t csr_base) 1507 { 1508 px_t *px_p = DIP_TO_STATE(rpdip); 1509 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 1510 caddr_t pcitool_addr = pxu_p->pcitool_addr; 1511 caddr_t errlog_addr = 1512 (caddr_t)CSR_FR(csr_base, DMCINT_ODCD_ERROR_LOG, ADDRESS); 1513 1514 return (pcitool_addr == errlog_addr); 1515 } 1516 1517 /* 1518 * JBC Dmcint ODCD errer handling for errors which are forgivable during a safe 1519 * access. (This will be most likely be a PCItool access.) If not a safe 1520 * access context, treat like jbc_dmcint_odcd. 1521 * Unmapped PIO read error: pio:read:M:nonfatal 1522 * Unmapped PIO write error: pio:write:M:nonfatal 1523 * Invalid PIO write to PCIe cfg/io, csr, ebus or i2c bus: pio:write:nonfatal 1524 * Invalid PIO read to PCIe cfg/io, csr, ebus or i2c bus: pio:read:nonfatal 1525 */ 1526 /* ARGSUSED */ 1527 int 1528 px_err_jbc_safe_acc_handle(dev_info_t *rpdip, caddr_t csr_base, 1529 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1530 px_err_bit_desc_t *err_bit_descr) 1531 { 1532 boolean_t pri = PX_ERR_IS_PRI(err_bit_descr->bit); 1533 1534 if (!pri) 1535 return (PX_FATAL_GOS); 1536 /* 1537 * Got an error which is forgivable during a PCItool access. 1538 * 1539 * Don't do handler check since the error may otherwise be unfairly 1540 * attributed to a device. Just return. 1541 * 1542 * Note: There is a hole here in that a legitimate error can come in 1543 * while a PCItool access is in play and be forgiven. This is possible 1544 * though not likely. 1545 */ 1546 if ((derr->fme_flag != DDI_FM_ERR_UNEXPECTED) && 1547 (px_jbc_pcitool_addr_match(rpdip, csr_base))) 1548 return (PX_FATAL_SW); 1549 1550 return (px_err_jbc_dmcint_odcd_handle(rpdip, csr_base, derr, 1551 err_reg_descr, err_bit_descr)); 1552 } 1553 1554 /* JBC Dmcint IDC - see io erpt doc, section 1.6 */ 1555 PX_ERPT_SEND_DEC(jbc_idc) 1556 { 1557 char buf[FM_MAX_CLASS]; 1558 boolean_t pri = PX_ERR_IS_PRI(bit); 1559 1560 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1561 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1562 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1563 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1564 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1565 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1566 FIRE_JBC_IE, DATA_TYPE_UINT64, 1567 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1568 FIRE_JBC_IS, DATA_TYPE_UINT64, 1569 ss_reg, 1570 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1571 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1572 FIRE_JBC_DMC_IDC, DATA_TYPE_UINT64, 1573 CSR_XR(csr_base, DMCINT_IDC_ERROR_LOG), 1574 NULL); 1575 1576 return (PX_OK); 1577 } 1578 1579 /* JBC CSR - see io erpt doc, section 1.7 */ 1580 PX_ERPT_SEND_DEC(jbc_csr) 1581 { 1582 char buf[FM_MAX_CLASS]; 1583 boolean_t pri = PX_ERR_IS_PRI(bit); 1584 1585 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1586 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1587 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1588 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1589 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1590 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1591 FIRE_JBC_IE, DATA_TYPE_UINT64, 1592 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1593 FIRE_JBC_IS, DATA_TYPE_UINT64, 1594 ss_reg, 1595 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1596 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1597 "jbc-error-reg", DATA_TYPE_UINT64, 1598 CSR_XR(csr_base, CSR_ERROR_LOG), 1599 NULL); 1600 1601 return (PX_OK); 1602 } 1603 1604 /* 1605 * JBC CSR errer handling - 1606 * Ebus ready timeout error: pio:rdwr:M:nonfatal 1607 */ 1608 /* ARGSUSED */ 1609 int 1610 px_err_jbc_csr_handle(dev_info_t *rpdip, caddr_t csr_base, 1611 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1612 px_err_bit_desc_t *err_bit_descr) 1613 { 1614 boolean_t pri = PX_ERR_IS_PRI(err_bit_descr->bit); 1615 uint64_t paddr; 1616 int ret; 1617 1618 if (!pri) 1619 return (PX_FATAL_GOS); 1620 1621 paddr = CSR_XR(csr_base, CSR_ERROR_LOG); 1622 paddr &= CSR_ERROR_LOG_ADDRESS_MASK; 1623 1624 ret = px_handle_lookup( 1625 rpdip, DMA_HANDLE, derr->fme_ena, (void *)paddr); 1626 1627 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1628 } 1629 1630 /* JBC Dmcint IDC - see io erpt doc, section 1.6 */ 1631 1632 /* DMC IMU RDS - see io erpt doc, section 2.1 */ 1633 PX_ERPT_SEND_DEC(imu_rds) 1634 { 1635 char buf[FM_MAX_CLASS]; 1636 boolean_t pri = PX_ERR_IS_PRI(bit); 1637 1638 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1639 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1640 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1641 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1642 FIRE_IMU_ELE, DATA_TYPE_UINT64, 1643 CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE), 1644 FIRE_IMU_IE, DATA_TYPE_UINT64, 1645 CSR_XR(csr_base, IMU_INTERRUPT_ENABLE), 1646 FIRE_IMU_IS, DATA_TYPE_UINT64, 1647 ss_reg, 1648 FIRE_IMU_ESS, DATA_TYPE_UINT64, 1649 CSR_XR(csr_base, IMU_ERROR_STATUS_SET), 1650 FIRE_IMU_RDS, DATA_TYPE_UINT64, 1651 CSR_XR(csr_base, IMU_RDS_ERROR_LOG), 1652 NULL); 1653 1654 return (PX_OK); 1655 } 1656 1657 /* imu function to handle all Received but Not Enabled errors */ 1658 /* ARGSUSED */ 1659 int 1660 px_err_imu_rbne_handle(dev_info_t *rpdip, caddr_t csr_base, 1661 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1662 px_err_bit_desc_t *err_bit_descr) 1663 { 1664 uint64_t imu_log_enable, imu_intr_enable; 1665 int mask = BITMASK(err_bit_descr->bit); 1666 int err = PX_NONFATAL; 1667 1668 imu_log_enable = CSR_XR(csr_base, err_reg_descr->log_addr); 1669 imu_intr_enable = CSR_XR(csr_base, err_reg_descr->enable_addr); 1670 1671 /* 1672 * If matching bit is not set, meaning corresponding rbne not 1673 * enabled, then receiving it indicates some sort of malfunction 1674 * possibly in hardware. 1675 * 1676 * Other wise, software may have intentionally disabled certain 1677 * errors for a period of time within which the occuring of the 1678 * disabled errors become rbne, that is non fatal. 1679 */ 1680 1681 if (!(imu_log_enable & imu_intr_enable & mask)) 1682 err = PX_FATAL_GOS; 1683 1684 return (err); 1685 } 1686 1687 /* 1688 * No platforms uses PME. Any PME received is simply logged 1689 * for analysis. 1690 */ 1691 /* ARGSUSED */ 1692 int 1693 px_err_imu_pme_handle(dev_info_t *rpdip, caddr_t csr_base, 1694 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1695 px_err_bit_desc_t *err_bit_descr) 1696 { 1697 px_t *px_p = DIP_TO_STATE(rpdip); 1698 1699 px_p->px_pme_ignored++; 1700 return (PX_NONFATAL); 1701 } 1702 1703 /* handle EQ overflow */ 1704 /* ARGSUSED */ 1705 int 1706 px_err_imu_eq_ovfl_handle(dev_info_t *rpdip, caddr_t csr_base, 1707 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1708 px_err_bit_desc_t *err_bit_descr) 1709 { 1710 px_t *px_p = DIP_TO_STATE(rpdip); 1711 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 1712 msiqid_t eqno; 1713 pci_msiq_state_t msiq_state; 1714 int err = PX_NONFATAL; 1715 int i; 1716 1717 eqno = msiq_state_p->msiq_1st_msiq_id; 1718 for (i = 0; i < msiq_state_p->msiq_cnt; i++) { 1719 if (px_lib_msiq_getstate(rpdip, eqno, &msiq_state) == 1720 DDI_SUCCESS) { 1721 if (msiq_state == PCI_MSIQ_STATE_ERROR) { 1722 err = PX_FATAL_GOS; 1723 } 1724 } 1725 } 1726 1727 return (err); 1728 } 1729 1730 /* DMC IMU SCS - see io erpt doc, section 2.2 */ 1731 PX_ERPT_SEND_DEC(imu_scs) 1732 { 1733 char buf[FM_MAX_CLASS]; 1734 boolean_t pri = PX_ERR_IS_PRI(bit); 1735 1736 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1737 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1738 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1739 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1740 FIRE_IMU_ELE, DATA_TYPE_UINT64, 1741 CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE), 1742 FIRE_IMU_IE, DATA_TYPE_UINT64, 1743 CSR_XR(csr_base, IMU_INTERRUPT_ENABLE), 1744 FIRE_IMU_IS, DATA_TYPE_UINT64, 1745 ss_reg, 1746 FIRE_IMU_ESS, DATA_TYPE_UINT64, 1747 CSR_XR(csr_base, IMU_ERROR_STATUS_SET), 1748 FIRE_IMU_SCS, DATA_TYPE_UINT64, 1749 CSR_XR(csr_base, IMU_SCS_ERROR_LOG), 1750 NULL); 1751 1752 return (PX_OK); 1753 } 1754 1755 /* DMC IMU - see io erpt doc, section 2.3 */ 1756 PX_ERPT_SEND_DEC(imu) 1757 { 1758 char buf[FM_MAX_CLASS]; 1759 boolean_t pri = PX_ERR_IS_PRI(bit); 1760 1761 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1762 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1763 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1764 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1765 FIRE_IMU_ELE, DATA_TYPE_UINT64, 1766 CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE), 1767 FIRE_IMU_IE, DATA_TYPE_UINT64, 1768 CSR_XR(csr_base, IMU_INTERRUPT_ENABLE), 1769 FIRE_IMU_IS, DATA_TYPE_UINT64, 1770 ss_reg, 1771 FIRE_IMU_ESS, DATA_TYPE_UINT64, 1772 CSR_XR(csr_base, IMU_ERROR_STATUS_SET), 1773 NULL); 1774 1775 return (PX_OK); 1776 } 1777 1778 /* DMC MMU TFAR/TFSR - see io erpt doc, section 2.4 */ 1779 PX_ERPT_SEND_DEC(mmu_tfar_tfsr) 1780 { 1781 char buf[FM_MAX_CLASS]; 1782 boolean_t pri = PX_ERR_IS_PRI(bit); 1783 1784 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1785 1786 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1787 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1788 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1789 FIRE_MMU_ELE, DATA_TYPE_UINT64, 1790 CSR_XR(csr_base, MMU_ERROR_LOG_ENABLE), 1791 FIRE_MMU_IE, DATA_TYPE_UINT64, 1792 CSR_XR(csr_base, MMU_INTERRUPT_ENABLE), 1793 FIRE_MMU_IS, DATA_TYPE_UINT64, 1794 ss_reg, 1795 FIRE_MMU_ESS, DATA_TYPE_UINT64, 1796 CSR_XR(csr_base, MMU_ERROR_STATUS_SET), 1797 FIRE_MMU_TFAR, DATA_TYPE_UINT64, 1798 CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS), 1799 FIRE_MMU_TFSR, DATA_TYPE_UINT64, 1800 CSR_XR(csr_base, MMU_TRANSLATION_FAULT_STATUS), 1801 NULL); 1802 1803 return (PX_OK); 1804 } 1805 1806 /* DMC MMU - see io erpt doc, section 2.5 */ 1807 PX_ERPT_SEND_DEC(mmu) 1808 { 1809 char buf[FM_MAX_CLASS]; 1810 boolean_t pri = PX_ERR_IS_PRI(bit); 1811 1812 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1813 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1814 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1815 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1816 FIRE_MMU_ELE, DATA_TYPE_UINT64, 1817 CSR_XR(csr_base, MMU_ERROR_LOG_ENABLE), 1818 FIRE_MMU_IE, DATA_TYPE_UINT64, 1819 CSR_XR(csr_base, MMU_INTERRUPT_ENABLE), 1820 FIRE_MMU_IS, DATA_TYPE_UINT64, 1821 ss_reg, 1822 FIRE_MMU_ESS, DATA_TYPE_UINT64, 1823 CSR_XR(csr_base, MMU_ERROR_STATUS_SET), 1824 NULL); 1825 1826 return (PX_OK); 1827 } 1828 1829 /* imu function to handle all Received but Not Enabled errors */ 1830 int 1831 px_err_mmu_rbne_handle(dev_info_t *rpdip, caddr_t csr_base, 1832 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1833 px_err_bit_desc_t *err_bit_descr) 1834 { 1835 boolean_t pri = PX_ERR_IS_PRI(err_bit_descr->bit); 1836 uint64_t mmu_log_enable, mmu_intr_enable; 1837 uint64_t mask = BITMASK(err_bit_descr->bit); 1838 uint64_t mmu_tfa, mmu_ctrl; 1839 uint64_t mmu_enable_bit = 0; 1840 int err = PX_NONFATAL; 1841 int ret; 1842 1843 mmu_log_enable = CSR_XR(csr_base, err_reg_descr->log_addr); 1844 mmu_intr_enable = CSR_XR(csr_base, err_reg_descr->enable_addr); 1845 1846 mmu_tfa = CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS); 1847 mmu_ctrl = CSR_XR(csr_base, MMU_CONTROL_AND_STATUS); 1848 1849 switch (err_bit_descr->bit) { 1850 case MMU_INTERRUPT_STATUS_BYP_ERR_P: 1851 mmu_enable_bit = BITMASK(MMU_CONTROL_AND_STATUS_BE); 1852 break; 1853 case MMU_INTERRUPT_STATUS_TRN_ERR_P: 1854 mmu_enable_bit = BITMASK(MMU_CONTROL_AND_STATUS_TE); 1855 break; 1856 default: 1857 mmu_enable_bit = 0; 1858 break; 1859 } 1860 1861 /* 1862 * If the interrupts are enabled and Translation/Bypass Enable bit 1863 * was set, then panic. This error should not have occured. 1864 */ 1865 if (mmu_log_enable & mmu_intr_enable & 1866 (mmu_ctrl & mmu_enable_bit)) { 1867 err = PX_FATAL_GOS; 1868 } else { 1869 if (!pri) 1870 return (PX_FATAL_GOS); 1871 1872 ret = px_handle_lookup( 1873 rpdip, DMA_HANDLE, derr->fme_ena, (void *)mmu_tfa); 1874 err = (ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL; 1875 1876 /* 1877 * S/W bug - this error should always be enabled 1878 */ 1879 1880 /* enable error & intr reporting for this bit */ 1881 CSR_XS(csr_base, MMU_ERROR_LOG_ENABLE, mmu_log_enable | mask); 1882 CSR_XS(csr_base, MMU_INTERRUPT_ENABLE, mmu_intr_enable | mask); 1883 1884 /* enable translation access/bypass enable */ 1885 CSR_XS(csr_base, MMU_CONTROL_AND_STATUS, 1886 mmu_ctrl | mmu_enable_bit); 1887 } 1888 1889 return (err); 1890 } 1891 1892 /* Generic error handling functions that involve MMU Translation Fault Addr */ 1893 /* ARGSUSED */ 1894 int 1895 px_err_mmu_tfa_handle(dev_info_t *rpdip, caddr_t csr_base, 1896 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1897 px_err_bit_desc_t *err_bit_descr) 1898 { 1899 boolean_t pri = PX_ERR_IS_PRI(err_bit_descr->bit); 1900 uint64_t mmu_tfa; 1901 uint_t ret; 1902 1903 if (!pri) 1904 return (PX_FATAL_GOS); 1905 1906 mmu_tfa = CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS); 1907 ret = px_handle_lookup( 1908 rpdip, DMA_HANDLE, derr->fme_ena, (void *)mmu_tfa); 1909 1910 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1911 } 1912 1913 /* MMU Table walk errors */ 1914 /* ARGSUSED */ 1915 int 1916 px_err_mmu_tblwlk_handle(dev_info_t *rpdip, caddr_t csr_base, 1917 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1918 px_err_bit_desc_t *err_bit_descr) 1919 { 1920 boolean_t pri = PX_ERR_IS_PRI(err_bit_descr->bit); 1921 uint64_t mmu_tfa; 1922 uint_t ret; 1923 1924 if (!pri) 1925 return (PX_FATAL_GOS); 1926 1927 mmu_tfa = CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS); 1928 ret = px_handle_lookup( 1929 rpdip, DMA_HANDLE, derr->fme_ena, (void *)mmu_tfa); 1930 1931 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1932 } 1933 1934 /* 1935 * TLU LUP event - if caused by power management activity, then it is expected. 1936 * In all other cases, it is an error. 1937 */ 1938 /* ARGSUSED */ 1939 int 1940 px_err_tlu_lup_handle(dev_info_t *rpdip, caddr_t csr_base, 1941 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1942 px_err_bit_desc_t *err_bit_descr) 1943 { 1944 px_t *px_p = DIP_TO_STATE(rpdip); 1945 1946 /* 1947 * power management code is currently the only segment that sets 1948 * px_lup_pending to indicate its expectation for a healthy LUP 1949 * event. For all other occasions, LUP event should be flaged as 1950 * error condition. 1951 */ 1952 return ((atomic_cas_32(&px_p->px_lup_pending, 1, 0) == 0) ? 1953 PX_NONFATAL : PX_OK); 1954 } 1955 1956 /* 1957 * TLU LDN event - if caused by power management activity, then it is expected. 1958 * In all other cases, it is an error. 1959 */ 1960 /* ARGSUSED */ 1961 int 1962 px_err_tlu_ldn_handle(dev_info_t *rpdip, caddr_t csr_base, 1963 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1964 px_err_bit_desc_t *err_bit_descr) 1965 { 1966 px_t *px_p = DIP_TO_STATE(rpdip); 1967 return ((px_p->px_pm_flags & PX_LDN_EXPECTED) ? PX_OK : PX_NONFATAL); 1968 } 1969 1970 /* PEC ILU none - see io erpt doc, section 3.1 */ 1971 PX_ERPT_SEND_DEC(pec_ilu) 1972 { 1973 char buf[FM_MAX_CLASS]; 1974 boolean_t pri = PX_ERR_IS_PRI(bit); 1975 1976 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1977 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1978 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1979 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1980 FIRE_ILU_ELE, DATA_TYPE_UINT64, 1981 CSR_XR(csr_base, ILU_ERROR_LOG_ENABLE), 1982 FIRE_ILU_IE, DATA_TYPE_UINT64, 1983 CSR_XR(csr_base, ILU_INTERRUPT_ENABLE), 1984 FIRE_ILU_IS, DATA_TYPE_UINT64, 1985 ss_reg, 1986 FIRE_ILU_ESS, DATA_TYPE_UINT64, 1987 CSR_XR(csr_base, ILU_ERROR_STATUS_SET), 1988 NULL); 1989 1990 return (PX_OK); 1991 } 1992 1993 /* PCIEX UE Errors */ 1994 /* ARGSUSED */ 1995 int 1996 px_err_pciex_ue_handle(dev_info_t *rpdip, caddr_t csr_base, 1997 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1998 px_err_bit_desc_t *err_bit_descr) 1999 { 2000 uint32_t mask = (uint32_t)BITMASK(err_bit_descr->bit); 2001 2002 return ((err_bit_descr->bit >= 32 && px_fabric_die_rc_ue_gos) ? 2003 PX_FATAL_GOS : PX_FABRIC_ERR_SEV(mask, px_fabric_die_rc_ue, 2004 px_fabric_die_rc_ue_gos)); 2005 } 2006 2007 /* PCI-E Uncorrectable Errors - see io erpt doc, section 3.2 */ 2008 PX_ERPT_SEND_DEC(pciex_rx_ue) 2009 { 2010 char buf[FM_MAX_CLASS]; 2011 boolean_t pri = PX_ERR_IS_PRI(bit); 2012 2013 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 2014 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 2015 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 2016 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 2017 FIRE_TLU_UELE, DATA_TYPE_UINT64, 2018 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE), 2019 FIRE_TLU_UIE, DATA_TYPE_UINT64, 2020 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE), 2021 FIRE_TLU_UIS, DATA_TYPE_UINT64, 2022 ss_reg, 2023 FIRE_TLU_UESS, DATA_TYPE_UINT64, 2024 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_SET), 2025 FIRE_TLU_RUEH1L, DATA_TYPE_UINT64, 2026 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER1_LOG), 2027 FIRE_TLU_RUEH2L, DATA_TYPE_UINT64, 2028 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER2_LOG), 2029 NULL); 2030 2031 return (PX_OK); 2032 } 2033 2034 /* PCI-E Uncorrectable Errors - see io erpt doc, section 3.3 */ 2035 PX_ERPT_SEND_DEC(pciex_tx_ue) 2036 { 2037 char buf[FM_MAX_CLASS]; 2038 boolean_t pri = PX_ERR_IS_PRI(bit); 2039 2040 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 2041 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 2042 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 2043 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 2044 FIRE_TLU_UELE, DATA_TYPE_UINT64, 2045 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE), 2046 FIRE_TLU_UIE, DATA_TYPE_UINT64, 2047 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE), 2048 FIRE_TLU_UIS, DATA_TYPE_UINT64, 2049 ss_reg, 2050 FIRE_TLU_UESS, DATA_TYPE_UINT64, 2051 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_SET), 2052 FIRE_TLU_TUEH1L, DATA_TYPE_UINT64, 2053 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER1_LOG), 2054 FIRE_TLU_TUEH2L, DATA_TYPE_UINT64, 2055 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER2_LOG), 2056 NULL); 2057 2058 return (PX_OK); 2059 } 2060 2061 /* PCI-E Uncorrectable Errors - see io erpt doc, section 3.4 */ 2062 PX_ERPT_SEND_DEC(pciex_rx_tx_ue) 2063 { 2064 char buf[FM_MAX_CLASS]; 2065 boolean_t pri = PX_ERR_IS_PRI(bit); 2066 2067 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 2068 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 2069 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 2070 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 2071 FIRE_TLU_UELE, DATA_TYPE_UINT64, 2072 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE), 2073 FIRE_TLU_UIE, DATA_TYPE_UINT64, 2074 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE), 2075 FIRE_TLU_UIS, DATA_TYPE_UINT64, 2076 ss_reg, 2077 FIRE_TLU_UESS, DATA_TYPE_UINT64, 2078 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_SET), 2079 FIRE_TLU_RUEH1L, DATA_TYPE_UINT64, 2080 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER1_LOG), 2081 FIRE_TLU_RUEH2L, DATA_TYPE_UINT64, 2082 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER2_LOG), 2083 FIRE_TLU_TUEH1L, DATA_TYPE_UINT64, 2084 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER1_LOG), 2085 FIRE_TLU_TUEH2L, DATA_TYPE_UINT64, 2086 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER2_LOG), 2087 NULL); 2088 2089 return (PX_OK); 2090 } 2091 2092 /* PCI-E Uncorrectable Errors - see io erpt doc, section 3.5 */ 2093 PX_ERPT_SEND_DEC(pciex_ue) 2094 { 2095 char buf[FM_MAX_CLASS]; 2096 boolean_t pri = PX_ERR_IS_PRI(bit); 2097 2098 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 2099 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 2100 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 2101 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 2102 FIRE_TLU_UELE, DATA_TYPE_UINT64, 2103 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE), 2104 FIRE_TLU_UIE, DATA_TYPE_UINT64, 2105 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE), 2106 FIRE_TLU_UIS, DATA_TYPE_UINT64, 2107 ss_reg, 2108 FIRE_TLU_UESS, DATA_TYPE_UINT64, 2109 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_SET), 2110 NULL); 2111 2112 return (PX_OK); 2113 } 2114 2115 /* PCIEX UE Errors */ 2116 /* ARGSUSED */ 2117 int 2118 px_err_pciex_ce_handle(dev_info_t *rpdip, caddr_t csr_base, 2119 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 2120 px_err_bit_desc_t *err_bit_descr) 2121 { 2122 uint32_t mask = (uint32_t)BITMASK(err_bit_descr->bit); 2123 2124 return ((err_bit_descr->bit >= 32 && px_fabric_die_rc_ce_gos) ? 2125 PX_FATAL_GOS : PX_FABRIC_ERR_SEV(mask, px_fabric_die_rc_ce, 2126 px_fabric_die_rc_ce_gos)); 2127 } 2128 2129 /* PCI-E Correctable Errors - see io erpt doc, section 3.6 */ 2130 PX_ERPT_SEND_DEC(pciex_ce) 2131 { 2132 char buf[FM_MAX_CLASS]; 2133 boolean_t pri = PX_ERR_IS_PRI(bit); 2134 2135 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 2136 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 2137 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 2138 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 2139 FIRE_TLU_CELE, DATA_TYPE_UINT64, 2140 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_LOG_ENABLE), 2141 FIRE_TLU_CIE, DATA_TYPE_UINT64, 2142 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_INTERRUPT_ENABLE), 2143 FIRE_TLU_CIS, DATA_TYPE_UINT64, 2144 ss_reg, 2145 FIRE_TLU_CESS, DATA_TYPE_UINT64, 2146 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_STATUS_SET), 2147 NULL); 2148 2149 return (PX_OK); 2150 } 2151 2152 /* TLU Other Event Status (receive only) - see io erpt doc, section 3.7 */ 2153 PX_ERPT_SEND_DEC(pciex_rx_oe) 2154 { 2155 char buf[FM_MAX_CLASS]; 2156 boolean_t pri = PX_ERR_IS_PRI(bit); 2157 2158 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 2159 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 2160 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 2161 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 2162 FIRE_TLU_OEELE, DATA_TYPE_UINT64, 2163 CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE), 2164 FIRE_TLU_OEIE, DATA_TYPE_UINT64, 2165 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_ENABLE), 2166 FIRE_TLU_OEIS, DATA_TYPE_UINT64, 2167 ss_reg, 2168 FIRE_TLU_OEESS, DATA_TYPE_UINT64, 2169 CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_SET), 2170 FIRE_TLU_RUEH1L, DATA_TYPE_UINT64, 2171 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG), 2172 FIRE_TLU_RUEH2L, DATA_TYPE_UINT64, 2173 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG), 2174 NULL); 2175 2176 return (PX_OK); 2177 } 2178 2179 /* TLU Other Event Status (rx + tx) - see io erpt doc, section 3.8 */ 2180 PX_ERPT_SEND_DEC(pciex_rx_tx_oe) 2181 { 2182 char buf[FM_MAX_CLASS]; 2183 boolean_t pri = PX_ERR_IS_PRI(bit); 2184 2185 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 2186 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 2187 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 2188 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 2189 FIRE_TLU_OEELE, DATA_TYPE_UINT64, 2190 CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE), 2191 FIRE_TLU_OEIE, DATA_TYPE_UINT64, 2192 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_ENABLE), 2193 FIRE_TLU_OEIS, DATA_TYPE_UINT64, 2194 ss_reg, 2195 FIRE_TLU_OEESS, DATA_TYPE_UINT64, 2196 CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_SET), 2197 FIRE_TLU_ROEEH1L, DATA_TYPE_UINT64, 2198 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG), 2199 FIRE_TLU_ROEEH2L, DATA_TYPE_UINT64, 2200 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG), 2201 FIRE_TLU_TOEEH1L, DATA_TYPE_UINT64, 2202 CSR_XR(csr_base, TLU_TRANSMIT_OTHER_EVENT_HEADER1_LOG), 2203 FIRE_TLU_TOEEH2L, DATA_TYPE_UINT64, 2204 CSR_XR(csr_base, TLU_TRANSMIT_OTHER_EVENT_HEADER2_LOG), 2205 NULL); 2206 2207 return (PX_OK); 2208 } 2209 2210 /* TLU Other Event - see io erpt doc, section 3.9 */ 2211 PX_ERPT_SEND_DEC(pciex_oe) 2212 { 2213 char buf[FM_MAX_CLASS]; 2214 boolean_t pri = PX_ERR_IS_PRI(bit); 2215 2216 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 2217 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 2218 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 2219 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 2220 FIRE_TLU_OEELE, DATA_TYPE_UINT64, 2221 CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE), 2222 FIRE_TLU_OEIE, DATA_TYPE_UINT64, 2223 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_ENABLE), 2224 FIRE_TLU_OEIS, DATA_TYPE_UINT64, 2225 ss_reg, 2226 FIRE_TLU_OEESS, DATA_TYPE_UINT64, 2227 CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_SET), 2228 NULL); 2229 2230 return (PX_OK); 2231 } 2232