1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * sun4u Fire Error Handling 30 */ 31 32 #include <sys/types.h> 33 #include <sys/ddi.h> 34 #include <sys/sunddi.h> 35 #include <sys/fm/protocol.h> 36 #include <sys/fm/util.h> 37 #include <sys/pcie.h> 38 #include <sys/pcie_impl.h> 39 #include "px_obj.h" 40 #include <px_regs.h> 41 #include <px_csr.h> 42 #include <sys/membar.h> 43 #include <sys/machcpuvar.h> 44 #include <sys/platform_module.h> 45 #include "pcie_pwr.h" 46 #include "px_lib4u.h" 47 #include "px_err.h" 48 #include "px_err_impl.h" 49 #include "oberon_regs.h" 50 51 uint64_t px_tlu_ue_intr_mask = PX_ERR_EN_ALL; 52 uint64_t px_tlu_ue_log_mask = PX_ERR_EN_ALL; 53 uint64_t px_tlu_ue_count_mask = PX_ERR_EN_ALL; 54 55 uint64_t px_tlu_ce_intr_mask = PX_ERR_MASK_NONE; 56 uint64_t px_tlu_ce_log_mask = PX_ERR_MASK_NONE; 57 uint64_t px_tlu_ce_count_mask = PX_ERR_MASK_NONE; 58 59 /* 60 * Do not enable Link Interrupts 61 */ 62 uint64_t px_tlu_oe_intr_mask = PX_ERR_EN_ALL & ~0x80000000800; 63 uint64_t px_tlu_oe_log_mask = PX_ERR_EN_ALL & ~0x80000000800; 64 uint64_t px_tlu_oe_count_mask = PX_ERR_EN_ALL; 65 66 uint64_t px_mmu_intr_mask = PX_ERR_EN_ALL; 67 uint64_t px_mmu_log_mask = PX_ERR_EN_ALL; 68 uint64_t px_mmu_count_mask = PX_ERR_EN_ALL; 69 70 uint64_t px_imu_intr_mask = PX_ERR_EN_ALL; 71 uint64_t px_imu_log_mask = PX_ERR_EN_ALL; 72 uint64_t px_imu_count_mask = PX_ERR_EN_ALL; 73 74 /* 75 * (1ull << ILU_INTERRUPT_ENABLE_IHB_PE_S) | 76 * (1ull << ILU_INTERRUPT_ENABLE_IHB_PE_P); 77 */ 78 uint64_t px_ilu_intr_mask = (((uint64_t)0x10 << 32) | 0x10); 79 uint64_t px_ilu_log_mask = (((uint64_t)0x10 << 32) | 0x10); 80 uint64_t px_ilu_count_mask = PX_ERR_EN_ALL; 81 82 uint64_t px_ubc_intr_mask = PX_ERR_EN_ALL; 83 uint64_t px_ubc_log_mask = PX_ERR_EN_ALL; 84 uint64_t px_ubc_count_mask = PX_ERR_EN_ALL; 85 86 uint64_t px_jbc_intr_mask = PX_ERR_EN_ALL; 87 uint64_t px_jbc_log_mask = PX_ERR_EN_ALL; 88 uint64_t px_jbc_count_mask = PX_ERR_EN_ALL; 89 90 /* 91 * LPU Intr Registers are reverse encoding from the registers above. 92 * 1 = disable 93 * 0 = enable 94 * 95 * Log and Count are however still the same. 96 */ 97 uint64_t px_lpul_intr_mask = LPU_INTR_DISABLE; 98 uint64_t px_lpul_log_mask = PX_ERR_EN_ALL; 99 uint64_t px_lpul_count_mask = PX_ERR_EN_ALL; 100 101 uint64_t px_lpup_intr_mask = LPU_INTR_DISABLE; 102 uint64_t px_lpup_log_mask = PX_ERR_EN_ALL; 103 uint64_t px_lpup_count_mask = PX_ERR_EN_ALL; 104 105 uint64_t px_lpur_intr_mask = LPU_INTR_DISABLE; 106 uint64_t px_lpur_log_mask = PX_ERR_EN_ALL; 107 uint64_t px_lpur_count_mask = PX_ERR_EN_ALL; 108 109 uint64_t px_lpux_intr_mask = LPU_INTR_DISABLE; 110 uint64_t px_lpux_log_mask = PX_ERR_EN_ALL; 111 uint64_t px_lpux_count_mask = PX_ERR_EN_ALL; 112 113 uint64_t px_lpus_intr_mask = LPU_INTR_DISABLE; 114 uint64_t px_lpus_log_mask = PX_ERR_EN_ALL; 115 uint64_t px_lpus_count_mask = PX_ERR_EN_ALL; 116 117 uint64_t px_lpug_intr_mask = LPU_INTR_DISABLE; 118 uint64_t px_lpug_log_mask = PX_ERR_EN_ALL; 119 uint64_t px_lpug_count_mask = PX_ERR_EN_ALL; 120 121 /* 122 * JBC error bit table 123 */ 124 #define JBC_BIT_DESC(bit, hdl, erpt) \ 125 JBC_INTERRUPT_STATUS_ ## bit ## _P, \ 126 0, \ 127 PX_ERR_BIT_HANDLE(hdl), \ 128 PX_ERPT_SEND(erpt), \ 129 PX_ERR_JBC_CLASS(bit) }, \ 130 { JBC_INTERRUPT_STATUS_ ## bit ## _S, \ 131 0, \ 132 PX_ERR_BIT_HANDLE(hdl), \ 133 PX_ERPT_SEND(erpt), \ 134 PX_ERR_JBC_CLASS(bit) 135 px_err_bit_desc_t px_err_jbc_tbl[] = { 136 /* JBC FATAL - see io erpt doc, section 1.1 */ 137 { JBC_BIT_DESC(MB_PEA, fatal_hw, jbc_fatal) }, 138 { JBC_BIT_DESC(CPE, fatal_hw, jbc_fatal) }, 139 { JBC_BIT_DESC(APE, fatal_hw, jbc_fatal) }, 140 { JBC_BIT_DESC(PIO_CPE, fatal_hw, jbc_fatal) }, 141 { JBC_BIT_DESC(JTCEEW, fatal_hw, jbc_fatal) }, 142 { JBC_BIT_DESC(JTCEEI, fatal_hw, jbc_fatal) }, 143 { JBC_BIT_DESC(JTCEER, fatal_hw, jbc_fatal) }, 144 145 /* JBC MERGE - see io erpt doc, section 1.2 */ 146 { JBC_BIT_DESC(MB_PER, jbc_merge, jbc_merge) }, 147 { JBC_BIT_DESC(MB_PEW, jbc_merge, jbc_merge) }, 148 149 /* JBC Jbusint IN - see io erpt doc, section 1.3 */ 150 { JBC_BIT_DESC(UE_ASYN, fatal_gos, jbc_in) }, 151 { JBC_BIT_DESC(CE_ASYN, non_fatal, jbc_in) }, 152 { JBC_BIT_DESC(JTE, fatal_gos, jbc_in) }, 153 { JBC_BIT_DESC(JBE, jbc_jbusint_in, jbc_in) }, 154 { JBC_BIT_DESC(JUE, jbc_jbusint_in, jbc_in) }, 155 { JBC_BIT_DESC(ICISE, fatal_gos, jbc_in) }, 156 { JBC_BIT_DESC(WR_DPE, jbc_jbusint_in, jbc_in) }, 157 { JBC_BIT_DESC(RD_DPE, jbc_jbusint_in, jbc_in) }, 158 { JBC_BIT_DESC(ILL_BMW, jbc_jbusint_in, jbc_in) }, 159 { JBC_BIT_DESC(ILL_BMR, jbc_jbusint_in, jbc_in) }, 160 { JBC_BIT_DESC(BJC, jbc_jbusint_in, jbc_in) }, 161 162 /* JBC Jbusint Out - see io erpt doc, section 1.4 */ 163 { JBC_BIT_DESC(IJP, fatal_gos, jbc_out) }, 164 165 /* JBC Dmcint ODCD - see io erpt doc, section 1.5 */ 166 { JBC_BIT_DESC(PIO_UNMAP_RD, jbc_dmcint_odcd, jbc_odcd) }, 167 { JBC_BIT_DESC(ILL_ACC_RD, jbc_dmcint_odcd, jbc_odcd) }, 168 { JBC_BIT_DESC(PIO_UNMAP, jbc_dmcint_odcd, jbc_odcd) }, 169 { JBC_BIT_DESC(PIO_DPE, jbc_dmcint_odcd, jbc_odcd) }, 170 { JBC_BIT_DESC(PIO_CPE, non_fatal, jbc_odcd) }, 171 { JBC_BIT_DESC(ILL_ACC, jbc_dmcint_odcd, jbc_odcd) }, 172 173 /* JBC Dmcint IDC - see io erpt doc, section 1.6 */ 174 { JBC_BIT_DESC(UNSOL_RD, non_fatal, jbc_idc) }, 175 { JBC_BIT_DESC(UNSOL_INTR, non_fatal, jbc_idc) }, 176 177 /* JBC CSR - see io erpt doc, section 1.7 */ 178 { JBC_BIT_DESC(EBUS_TO, jbc_csr, jbc_csr) } 179 }; 180 181 #define px_err_jbc_keys \ 182 (sizeof (px_err_jbc_tbl)) / (sizeof (px_err_bit_desc_t)) 183 184 /* 185 * UBC error bit table 186 */ 187 #define UBC_BIT_DESC(bit, hdl, erpt) \ 188 UBC_INTERRUPT_STATUS_ ## bit ## _P, \ 189 0, \ 190 PX_ERR_BIT_HANDLE(hdl), \ 191 PX_ERPT_SEND(erpt), \ 192 PX_ERR_UBC_CLASS(bit) }, \ 193 { UBC_INTERRUPT_STATUS_ ## bit ## _S, \ 194 0, \ 195 PX_ERR_BIT_HANDLE(hdl), \ 196 PX_ERPT_SEND(erpt), \ 197 PX_ERR_UBC_CLASS(bit) 198 px_err_bit_desc_t px_err_ubc_tbl[] = { 199 /* UBC FATAL */ 200 { UBC_BIT_DESC(DMARDUEA, non_fatal, ubc_fatal) }, 201 { UBC_BIT_DESC(DMAWTUEA, fatal_sw, ubc_fatal) }, 202 { UBC_BIT_DESC(MEMRDAXA, fatal_sw, ubc_fatal) }, 203 { UBC_BIT_DESC(MEMWTAXA, fatal_sw, ubc_fatal) }, 204 { UBC_BIT_DESC(DMARDUEB, non_fatal, ubc_fatal) }, 205 { UBC_BIT_DESC(DMAWTUEB, fatal_sw, ubc_fatal) }, 206 { UBC_BIT_DESC(MEMRDAXB, fatal_sw, ubc_fatal) }, 207 { UBC_BIT_DESC(MEMWTAXB, fatal_sw, ubc_fatal) }, 208 { UBC_BIT_DESC(PIOWTUE, fatal_sw, ubc_fatal) }, 209 { UBC_BIT_DESC(PIOWBEUE, fatal_sw, ubc_fatal) }, 210 { UBC_BIT_DESC(PIORBEUE, fatal_sw, ubc_fatal) } 211 }; 212 213 #define px_err_ubc_keys \ 214 (sizeof (px_err_ubc_tbl)) / (sizeof (px_err_bit_desc_t)) 215 216 217 char *ubc_class_eid_qualifier[] = { 218 "-mem", 219 "-channel", 220 "-cpu", 221 "-path" 222 }; 223 224 225 /* 226 * DMC error bit tables 227 */ 228 #define IMU_BIT_DESC(bit, hdl, erpt) \ 229 IMU_INTERRUPT_STATUS_ ## bit ## _P, \ 230 0, \ 231 PX_ERR_BIT_HANDLE(hdl), \ 232 PX_ERPT_SEND(erpt), \ 233 PX_ERR_DMC_CLASS(bit) }, \ 234 { IMU_INTERRUPT_STATUS_ ## bit ## _S, \ 235 0, \ 236 PX_ERR_BIT_HANDLE(hdl), \ 237 PX_ERPT_SEND(erpt), \ 238 PX_ERR_DMC_CLASS(bit) 239 px_err_bit_desc_t px_err_imu_tbl[] = { 240 /* DMC IMU RDS - see io erpt doc, section 2.1 */ 241 { IMU_BIT_DESC(MSI_MAL_ERR, non_fatal, imu_rds) }, 242 { IMU_BIT_DESC(MSI_PAR_ERR, fatal_stuck, imu_rds) }, 243 { IMU_BIT_DESC(PMEACK_MES_NOT_EN, imu_rbne, imu_rds) }, 244 { IMU_BIT_DESC(PMPME_MES_NOT_EN, imu_pme, imu_rds) }, 245 { IMU_BIT_DESC(FATAL_MES_NOT_EN, imu_rbne, imu_rds) }, 246 { IMU_BIT_DESC(NONFATAL_MES_NOT_EN, imu_rbne, imu_rds) }, 247 { IMU_BIT_DESC(COR_MES_NOT_EN, imu_rbne, imu_rds) }, 248 { IMU_BIT_DESC(MSI_NOT_EN, imu_rbne, imu_rds) }, 249 250 /* DMC IMU SCS - see io erpt doc, section 2.2 */ 251 { IMU_BIT_DESC(EQ_NOT_EN, imu_rbne, imu_rds) }, 252 253 /* DMC IMU - see io erpt doc, section 2.3 */ 254 { IMU_BIT_DESC(EQ_OVER, imu_eq_ovfl, imu) } 255 }; 256 257 #define px_err_imu_keys (sizeof (px_err_imu_tbl)) / (sizeof (px_err_bit_desc_t)) 258 259 /* mmu errors */ 260 #define MMU_BIT_DESC(bit, hdl, erpt) \ 261 MMU_INTERRUPT_STATUS_ ## bit ## _P, \ 262 0, \ 263 PX_ERR_BIT_HANDLE(hdl), \ 264 PX_ERPT_SEND(erpt), \ 265 PX_ERR_DMC_CLASS(bit) }, \ 266 { MMU_INTERRUPT_STATUS_ ## bit ## _S, \ 267 0, \ 268 PX_ERR_BIT_HANDLE(hdl), \ 269 PX_ERPT_SEND(erpt), \ 270 PX_ERR_DMC_CLASS(bit) 271 px_err_bit_desc_t px_err_mmu_tbl[] = { 272 /* DMC MMU TFAR/TFSR - see io erpt doc, section 2.4 */ 273 { MMU_BIT_DESC(BYP_ERR, mmu_rbne, mmu_tfar_tfsr) }, 274 { MMU_BIT_DESC(BYP_OOR, mmu_tfa, mmu_tfar_tfsr) }, 275 { MMU_BIT_DESC(TRN_ERR, mmu_rbne, mmu_tfar_tfsr) }, 276 { MMU_BIT_DESC(TRN_OOR, mmu_tfa, mmu_tfar_tfsr) }, 277 { MMU_BIT_DESC(TTE_INV, mmu_tfa, mmu_tfar_tfsr) }, 278 { MMU_BIT_DESC(TTE_PRT, mmu_tfa, mmu_tfar_tfsr) }, 279 { MMU_BIT_DESC(TTC_DPE, mmu_tfa, mmu_tfar_tfsr) }, 280 { MMU_BIT_DESC(TBW_DME, mmu_tblwlk, mmu_tfar_tfsr) }, 281 { MMU_BIT_DESC(TBW_UDE, mmu_tblwlk, mmu_tfar_tfsr) }, 282 { MMU_BIT_DESC(TBW_ERR, mmu_tblwlk, mmu_tfar_tfsr) }, 283 { MMU_BIT_DESC(TBW_DPE, mmu_tblwlk, mmu_tfar_tfsr) }, 284 285 /* DMC MMU - see io erpt doc, section 2.5 */ 286 { MMU_BIT_DESC(TTC_CAE, non_fatal, mmu) } 287 }; 288 #define px_err_mmu_keys (sizeof (px_err_mmu_tbl)) / (sizeof (px_err_bit_desc_t)) 289 290 291 /* 292 * PEC error bit tables 293 */ 294 #define ILU_BIT_DESC(bit, hdl, erpt) \ 295 ILU_INTERRUPT_STATUS_ ## bit ## _P, \ 296 0, \ 297 PX_ERR_BIT_HANDLE(hdl), \ 298 PX_ERPT_SEND(erpt), \ 299 PX_ERR_PEC_CLASS(bit) }, \ 300 { ILU_INTERRUPT_STATUS_ ## bit ## _S, \ 301 0, \ 302 PX_ERR_BIT_HANDLE(hdl), \ 303 PX_ERPT_SEND(erpt), \ 304 PX_ERR_PEC_CLASS(bit) 305 px_err_bit_desc_t px_err_ilu_tbl[] = { 306 /* PEC ILU none - see io erpt doc, section 3.1 */ 307 { ILU_BIT_DESC(IHB_PE, fatal_gos, pec_ilu) } 308 }; 309 #define px_err_ilu_keys \ 310 (sizeof (px_err_ilu_tbl)) / (sizeof (px_err_bit_desc_t)) 311 312 /* 313 * PEC UE errors implementation is incomplete pending PCIE generic 314 * fabric rules. Must handle both PRIMARY and SECONDARY errors. 315 */ 316 /* pec ue errors */ 317 #define TLU_UC_BIT_DESC(bit, hdl, erpt) \ 318 TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _P, \ 319 0, \ 320 PX_ERR_BIT_HANDLE(hdl), \ 321 PX_ERPT_SEND(erpt), \ 322 PX_ERR_PEC_CLASS(bit) }, \ 323 { TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _S, \ 324 0, \ 325 PX_ERR_BIT_HANDLE(hdl), \ 326 PX_ERPT_SEND(erpt), \ 327 PX_ERR_PEC_CLASS(bit) 328 #define TLU_UC_OB_BIT_DESC(bit, hdl, erpt) \ 329 TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _P, \ 330 0, \ 331 PX_ERR_BIT_HANDLE(hdl), \ 332 PX_ERPT_SEND(erpt), \ 333 PX_ERR_PEC_OB_CLASS(bit) }, \ 334 { TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _S, \ 335 0, \ 336 PX_ERR_BIT_HANDLE(hdl), \ 337 PX_ERPT_SEND(erpt), \ 338 PX_ERR_PEC_CLASS(bit) 339 px_err_bit_desc_t px_err_tlu_ue_tbl[] = { 340 /* PCI-E Receive Uncorrectable Errors - see io erpt doc, section 3.2 */ 341 { TLU_UC_BIT_DESC(UR, pciex_ue, pciex_rx_ue) }, 342 { TLU_UC_BIT_DESC(UC, pciex_ue, pciex_rx_ue) }, 343 344 /* PCI-E Transmit Uncorrectable Errors - see io erpt doc, section 3.3 */ 345 { TLU_UC_OB_BIT_DESC(ECRC, pciex_ue, pciex_rx_ue) }, 346 { TLU_UC_BIT_DESC(CTO, pciex_ue, pciex_tx_ue) }, 347 { TLU_UC_BIT_DESC(ROF, pciex_ue, pciex_tx_ue) }, 348 349 /* PCI-E Rx/Tx Uncorrectable Errors - see io erpt doc, section 3.4 */ 350 { TLU_UC_BIT_DESC(MFP, pciex_ue, pciex_rx_tx_ue) }, 351 { TLU_UC_BIT_DESC(PP, pciex_ue, pciex_rx_tx_ue) }, 352 353 /* Other PCI-E Uncorrectable Errors - see io erpt doc, section 3.5 */ 354 { TLU_UC_BIT_DESC(FCP, pciex_ue, pciex_ue) }, 355 { TLU_UC_BIT_DESC(DLP, pciex_ue, pciex_ue) }, 356 { TLU_UC_BIT_DESC(TE, pciex_ue, pciex_ue) }, 357 358 /* Not used */ 359 { TLU_UC_BIT_DESC(CA, pciex_ue, do_not) } 360 }; 361 #define px_err_tlu_ue_keys \ 362 (sizeof (px_err_tlu_ue_tbl)) / (sizeof (px_err_bit_desc_t)) 363 364 365 /* 366 * PEC CE errors implementation is incomplete pending PCIE generic 367 * fabric rules. 368 */ 369 /* pec ce errors */ 370 #define TLU_CE_BIT_DESC(bit, hdl, erpt) \ 371 TLU_CORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _P, \ 372 0, \ 373 PX_ERR_BIT_HANDLE(hdl), \ 374 PX_ERPT_SEND(erpt), \ 375 PX_ERR_PEC_CLASS(bit) }, \ 376 { TLU_CORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _S, \ 377 0, \ 378 PX_ERR_BIT_HANDLE(hdl), \ 379 PX_ERPT_SEND(erpt), \ 380 PX_ERR_PEC_CLASS(bit) 381 px_err_bit_desc_t px_err_tlu_ce_tbl[] = { 382 /* PCI-E Correctable Errors - see io erpt doc, section 3.6 */ 383 { TLU_CE_BIT_DESC(RTO, pciex_ce, pciex_ce) }, 384 { TLU_CE_BIT_DESC(RNR, pciex_ce, pciex_ce) }, 385 { TLU_CE_BIT_DESC(BDP, pciex_ce, pciex_ce) }, 386 { TLU_CE_BIT_DESC(BTP, pciex_ce, pciex_ce) }, 387 { TLU_CE_BIT_DESC(RE, pciex_ce, pciex_ce) } 388 }; 389 #define px_err_tlu_ce_keys \ 390 (sizeof (px_err_tlu_ce_tbl)) / (sizeof (px_err_bit_desc_t)) 391 392 393 /* pec oe errors */ 394 #define TLU_OE_BIT_DESC(bit, hdl, erpt) \ 395 TLU_OTHER_EVENT_STATUS_CLEAR_ ## bit ## _P, \ 396 0, \ 397 PX_ERR_BIT_HANDLE(hdl), \ 398 PX_ERPT_SEND(erpt), \ 399 PX_ERR_PEC_CLASS(bit) }, \ 400 { TLU_OTHER_EVENT_STATUS_CLEAR_ ## bit ## _S, \ 401 0, \ 402 PX_ERR_BIT_HANDLE(hdl), \ 403 PX_ERPT_SEND(erpt), \ 404 PX_ERR_PEC_CLASS(bit) 405 #define TLU_OE_OB_BIT_DESC(bit, hdl, erpt) \ 406 TLU_OTHER_EVENT_STATUS_CLEAR_ ## bit ## _P, \ 407 0, \ 408 PX_ERR_BIT_HANDLE(hdl), \ 409 PX_ERPT_SEND(erpt), \ 410 PX_ERR_PEC_OB_CLASS(bit) }, \ 411 { TLU_OTHER_EVENT_STATUS_CLEAR_ ## bit ## _S, \ 412 0, \ 413 PX_ERR_BIT_HANDLE(hdl), \ 414 PX_ERPT_SEND(erpt), \ 415 PX_ERR_PEC_OB_CLASS(bit) 416 px_err_bit_desc_t px_err_tlu_oe_tbl[] = { 417 /* 418 * TLU Other Event Status (receive only) - see io erpt doc, section 3.7 419 */ 420 { TLU_OE_BIT_DESC(MRC, fatal_hw, pciex_rx_oe) }, 421 422 /* TLU Other Event Status (rx + tx) - see io erpt doc, section 3.8 */ 423 { TLU_OE_BIT_DESC(WUC, non_fatal, pciex_rx_tx_oe) }, 424 { TLU_OE_BIT_DESC(RUC, non_fatal, pciex_rx_tx_oe) }, 425 { TLU_OE_BIT_DESC(CRS, non_fatal, pciex_rx_tx_oe) }, 426 427 /* TLU Other Event - see io erpt doc, section 3.9 */ 428 { TLU_OE_BIT_DESC(IIP, fatal_gos, pciex_oe) }, 429 { TLU_OE_BIT_DESC(EDP, fatal_gos, pciex_oe) }, 430 { TLU_OE_BIT_DESC(EHP, fatal_gos, pciex_oe) }, 431 { TLU_OE_OB_BIT_DESC(TLUEITMO, fatal_gos, pciex_oe) }, 432 { TLU_OE_BIT_DESC(LIN, non_fatal, pciex_oe) }, 433 { TLU_OE_BIT_DESC(LRS, non_fatal, pciex_oe) }, 434 { TLU_OE_BIT_DESC(LDN, tlu_ldn, pciex_oe) }, 435 { TLU_OE_BIT_DESC(LUP, tlu_lup, pciex_oe) }, 436 { TLU_OE_BIT_DESC(ERU, fatal_gos, pciex_oe) }, 437 { TLU_OE_BIT_DESC(ERO, fatal_gos, pciex_oe) }, 438 { TLU_OE_BIT_DESC(EMP, fatal_gos, pciex_oe) }, 439 { TLU_OE_BIT_DESC(EPE, fatal_gos, pciex_oe) }, 440 { TLU_OE_BIT_DESC(ERP, fatal_gos, pciex_oe) }, 441 { TLU_OE_BIT_DESC(EIP, fatal_gos, pciex_oe) } 442 }; 443 444 #define px_err_tlu_oe_keys \ 445 (sizeof (px_err_tlu_oe_tbl)) / (sizeof (px_err_bit_desc_t)) 446 447 448 /* 449 * All the following tables below are for LPU Interrupts. These interrupts 450 * are *NOT* error interrupts, but event status interrupts. 451 * 452 * These events are probably of most interest to: 453 * o Hotplug 454 * o Power Management 455 * o etc... 456 * 457 * There are also a few events that would be interresting for FMA. 458 * Again none of the regiseters below state that an error has occured 459 * or that data has been lost. If anything, they give status that an 460 * error is *about* to occur. examples 461 * o INT_SKP_ERR - indicates clock between fire and child is too far 462 * off and is most unlikely able to compensate 463 * o INT_TX_PAR_ERR - A parity error occured in ONE lane. This is 464 * HW recoverable, but will like end up as a future 465 * fabric error as well. 466 * 467 * For now, we don't care about any of these errors and should be ignore, 468 * but cleared. 469 */ 470 471 /* LPU Link Interrupt Table */ 472 #define LPUL_BIT_DESC(bit, hdl, erpt) \ 473 LPU_LINK_LAYER_INTERRUPT_AND_STATUS_INT_ ## bit, \ 474 0, \ 475 NULL, \ 476 NULL, \ 477 "" 478 px_err_bit_desc_t px_err_lpul_tbl[] = { 479 { LPUL_BIT_DESC(LINK_ERR_ACT, NULL, NULL) } 480 }; 481 #define px_err_lpul_keys \ 482 (sizeof (px_err_lpul_tbl)) / (sizeof (px_err_bit_desc_t)) 483 484 /* LPU Physical Interrupt Table */ 485 #define LPUP_BIT_DESC(bit, hdl, erpt) \ 486 LPU_PHY_LAYER_INTERRUPT_AND_STATUS_INT_ ## bit, \ 487 0, \ 488 NULL, \ 489 NULL, \ 490 "" 491 px_err_bit_desc_t px_err_lpup_tbl[] = { 492 { LPUP_BIT_DESC(PHY_LAYER_ERR, NULL, NULL) } 493 }; 494 #define px_err_lpup_keys \ 495 (sizeof (px_err_lpup_tbl)) / (sizeof (px_err_bit_desc_t)) 496 497 /* LPU Receive Interrupt Table */ 498 #define LPUR_BIT_DESC(bit, hdl, erpt) \ 499 LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS_INT_ ## bit, \ 500 0, \ 501 NULL, \ 502 NULL, \ 503 "" 504 px_err_bit_desc_t px_err_lpur_tbl[] = { 505 { LPUR_BIT_DESC(RCV_PHY, NULL, NULL) } 506 }; 507 #define px_err_lpur_keys \ 508 (sizeof (px_err_lpur_tbl)) / (sizeof (px_err_bit_desc_t)) 509 510 /* LPU Transmit Interrupt Table */ 511 #define LPUX_BIT_DESC(bit, hdl, erpt) \ 512 LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS_INT_ ## bit, \ 513 0, \ 514 NULL, \ 515 NULL, \ 516 "" 517 px_err_bit_desc_t px_err_lpux_tbl[] = { 518 { LPUX_BIT_DESC(UNMSK, NULL, NULL) } 519 }; 520 #define px_err_lpux_keys \ 521 (sizeof (px_err_lpux_tbl)) / (sizeof (px_err_bit_desc_t)) 522 523 /* LPU LTSSM Interrupt Table */ 524 #define LPUS_BIT_DESC(bit, hdl, erpt) \ 525 LPU_LTSSM_INTERRUPT_AND_STATUS_INT_ ## bit, \ 526 0, \ 527 NULL, \ 528 NULL, \ 529 "" 530 px_err_bit_desc_t px_err_lpus_tbl[] = { 531 { LPUS_BIT_DESC(ANY, NULL, NULL) } 532 }; 533 #define px_err_lpus_keys \ 534 (sizeof (px_err_lpus_tbl)) / (sizeof (px_err_bit_desc_t)) 535 536 /* LPU Gigablaze Glue Interrupt Table */ 537 #define LPUG_BIT_DESC(bit, hdl, erpt) \ 538 LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS_INT_ ## bit, \ 539 0, \ 540 NULL, \ 541 NULL, \ 542 "" 543 px_err_bit_desc_t px_err_lpug_tbl[] = { 544 { LPUG_BIT_DESC(GLOBL_UNMSK, NULL, NULL) } 545 }; 546 #define px_err_lpug_keys \ 547 (sizeof (px_err_lpug_tbl)) / (sizeof (px_err_bit_desc_t)) 548 549 550 /* Mask and Tables */ 551 #define MnT6(pre) \ 552 B_FALSE, \ 553 &px_ ## pre ## _intr_mask, \ 554 &px_ ## pre ## _log_mask, \ 555 &px_ ## pre ## _count_mask, \ 556 px_err_ ## pre ## _tbl, \ 557 px_err_ ## pre ## _keys, \ 558 0 559 560 #define MnT6_ob(pre) \ 561 B_FALSE, \ 562 &px_ ## pre ## _intr_mask, \ 563 &px_ ## pre ## _log_mask, \ 564 &px_ ## pre ## _count_mask, \ 565 px_err_ ## pre ## _ob_tbl, \ 566 px_err_ ## pre ## _ob_keys, \ 567 0 568 569 /* LPU Registers Addresses */ 570 #define LR4(pre) \ 571 NULL, \ 572 LPU_ ## pre ## _INTERRUPT_MASK, \ 573 LPU_ ## pre ## _INTERRUPT_AND_STATUS, \ 574 LPU_ ## pre ## _INTERRUPT_AND_STATUS 575 576 /* LPU Registers Addresses with Irregularities */ 577 #define LR4_FIXME(pre) \ 578 NULL, \ 579 LPU_ ## pre ## _INTERRUPT_MASK, \ 580 LPU_ ## pre ## _LAYER_INTERRUPT_AND_STATUS, \ 581 LPU_ ## pre ## _LAYER_INTERRUPT_AND_STATUS 582 583 /* TLU Registers Addresses */ 584 #define TR4(pre) \ 585 TLU_ ## pre ## _LOG_ENABLE, \ 586 TLU_ ## pre ## _INTERRUPT_ENABLE, \ 587 TLU_ ## pre ## _INTERRUPT_STATUS, \ 588 TLU_ ## pre ## _STATUS_CLEAR 589 590 /* Registers Addresses for JBC, UBC, MMU, IMU and ILU */ 591 #define R4(pre) \ 592 pre ## _ERROR_LOG_ENABLE, \ 593 pre ## _INTERRUPT_ENABLE, \ 594 pre ## _INTERRUPT_STATUS, \ 595 pre ## _ERROR_STATUS_CLEAR 596 597 /* 598 * Register error handling tables. 599 * The ID Field (first field) is identified by an enum px_err_id_t. 600 * It is located in px_err.h 601 */ 602 px_err_reg_desc_t px_err_reg_tbl[] = { 603 { MnT6(jbc), R4(JBC), "JBC Error"}, 604 { MnT6(ubc), R4(UBC), "UBC Error"}, 605 { MnT6(mmu), R4(MMU), "MMU Error"}, 606 { MnT6(imu), R4(IMU), "IMU Error"}, 607 { MnT6(tlu_ue), TR4(UNCORRECTABLE_ERROR), "TLU UE"}, 608 { MnT6(tlu_ce), TR4(CORRECTABLE_ERROR), "TLU CE"}, 609 { MnT6(tlu_oe), TR4(OTHER_EVENT), "TLU OE"}, 610 { MnT6(ilu), R4(ILU), "ILU Error"}, 611 { MnT6(lpul), LR4(LINK_LAYER), "LPU Link Layer"}, 612 { MnT6(lpup), LR4_FIXME(PHY), "LPU Phy Layer"}, 613 { MnT6(lpur), LR4(RECEIVE_PHY), "LPU RX Phy Layer"}, 614 { MnT6(lpux), LR4(TRANSMIT_PHY), "LPU TX Phy Layer"}, 615 { MnT6(lpus), LR4(LTSSM), "LPU LTSSM"}, 616 { MnT6(lpug), LR4(GIGABLAZE_GLUE), "LPU GigaBlaze Glue"}, 617 }; 618 #define PX_ERR_REG_KEYS (sizeof (px_err_reg_tbl)) / (sizeof (px_err_reg_tbl[0])) 619 620 typedef struct px_err_ss { 621 uint64_t err_status[PX_ERR_REG_KEYS]; 622 } px_err_ss_t; 623 624 static void px_err_snapshot(px_t *px_p, px_err_ss_t *ss, boolean_t chk_cb); 625 static int px_err_erpt_and_clr(px_t *px_p, ddi_fm_error_t *derr, 626 px_err_ss_t *ss); 627 static int px_err_check_severity(px_t *px_p, ddi_fm_error_t *derr, 628 int err, int caller); 629 630 /* 631 * px_err_cb_intr: 632 * Interrupt handler for the JBC/UBC block. 633 * o lock 634 * o create derr 635 * o px_err_handle(leaf1, with cb) 636 * o px_err_handle(leaf2, without cb) 637 * o dispatch (leaf1) 638 * o dispatch (leaf2) 639 * o unlock 640 * o handle error: fatal? fm_panic() : return INTR_CLAIMED) 641 */ 642 uint_t 643 px_err_cb_intr(caddr_t arg) 644 { 645 px_fault_t *px_fault_p = (px_fault_t *)arg; 646 dev_info_t *rpdip = px_fault_p->px_fh_dip; 647 px_t *px_p = DIP_TO_STATE(rpdip); 648 int err = PX_OK; 649 int ret = DDI_FM_OK; 650 int fatal = 0; 651 ddi_fm_error_t derr; 652 653 /* Create the derr */ 654 bzero(&derr, sizeof (ddi_fm_error_t)); 655 derr.fme_version = DDI_FME_VERSION; 656 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 657 derr.fme_flag = DDI_FM_ERR_UNEXPECTED; 658 659 mutex_enter(&px_p->px_fm_mutex); 660 661 err |= px_err_handle(px_p, &derr, PX_INTR_CALL, B_TRUE); 662 663 ret = ndi_fm_handler_dispatch(rpdip, NULL, &derr); 664 switch (ret) { 665 case DDI_FM_FATAL: 666 fatal++; 667 break; 668 case DDI_FM_NONFATAL: 669 case DDI_FM_UNKNOWN: 670 default: 671 break; 672 } 673 674 /* Set the intr state to idle for the leaf that received the mondo */ 675 676 (void) px_lib_intr_setstate(rpdip, px_fault_p->px_fh_sysino, 677 INTR_IDLE_STATE); 678 679 mutex_exit(&px_p->px_fm_mutex); 680 681 /* 682 * PX_FATAL_HW error is diagnosed after system recovered from 683 * HW initiated reset, therefore no furthur handling is required. 684 */ 685 if (fatal || err & (PX_FATAL_GOS | PX_FATAL_SW)) 686 PX_FM_PANIC("Fatal System Bus Error has occurred\n"); 687 688 return (DDI_INTR_CLAIMED); 689 } 690 691 /* 692 * px_err_dmc_pec_intr: 693 * Interrupt handler for the DMC/PEC block. 694 * o lock 695 * o create derr 696 * o px_err_handle(leaf, with cb) 697 * o dispatch (leaf) 698 * o unlock 699 * o handle error: fatal? fm_panic() : return INTR_CLAIMED) 700 */ 701 uint_t 702 px_err_dmc_pec_intr(caddr_t arg) 703 { 704 px_fault_t *px_fault_p = (px_fault_t *)arg; 705 dev_info_t *rpdip = px_fault_p->px_fh_dip; 706 px_t *px_p = DIP_TO_STATE(rpdip); 707 int err = PX_OK; 708 int ret = DDI_FM_OK; 709 ddi_fm_error_t derr; 710 711 /* Create the derr */ 712 bzero(&derr, sizeof (ddi_fm_error_t)); 713 derr.fme_version = DDI_FME_VERSION; 714 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 715 derr.fme_flag = DDI_FM_ERR_UNEXPECTED; 716 717 mutex_enter(&px_p->px_fm_mutex); 718 719 /* send ereport/handle/clear fire registers */ 720 err |= px_err_handle(px_p, &derr, PX_INTR_CALL, B_TRUE); 721 722 /* Check all child devices for errors */ 723 ret = ndi_fm_handler_dispatch(rpdip, NULL, &derr); 724 725 /* Set the interrupt state to idle */ 726 (void) px_lib_intr_setstate(rpdip, px_fault_p->px_fh_sysino, 727 INTR_IDLE_STATE); 728 729 mutex_exit(&px_p->px_fm_mutex); 730 731 /* 732 * PX_FATAL_HW indicates a condition recovered from Fatal-Reset, 733 * therefore it does not cause panic. 734 */ 735 if ((err & (PX_FATAL_GOS | PX_FATAL_SW)) || (ret == DDI_FM_FATAL)) 736 PX_FM_PANIC("Fatal System Port Error has occurred\n"); 737 738 return (DDI_INTR_CLAIMED); 739 } 740 741 /* 742 * Error register are being handled by px_hlib xxx_init functions. 743 * They are also called again by px_err_add_intr for mondo62 and 63 744 * from px_cb_attach and px_attach 745 */ 746 void 747 px_err_reg_enable(px_t *px_p, px_err_id_t id) 748 { 749 px_err_reg_desc_t *reg_desc = &px_err_reg_tbl[id]; 750 uint64_t intr_mask = *reg_desc->intr_mask_p; 751 uint64_t log_mask = *reg_desc->log_mask_p; 752 caddr_t csr_base; 753 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 754 755 /* Get the correct CSR BASE */ 756 if (PX_ERR_XBC(id)) 757 csr_base = (caddr_t)pxu_p->px_address[PX_REG_XBC]; 758 else 759 csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 760 761 reg_desc->enabled = B_TRUE; 762 763 /* Enable logs if it exists */ 764 if (reg_desc->log_addr != NULL) 765 CSR_XS(csr_base, reg_desc->log_addr, log_mask); 766 767 /* 768 * For readability you in code you set 1 to enable an interrupt. 769 * But in Fire it's backwards. You set 1 to *disable* an intr. 770 * Reverse the user tunable intr mask field. 771 * 772 * Disable All Errors 773 * Clear All Errors 774 * Enable Errors 775 */ 776 CSR_XS(csr_base, reg_desc->enable_addr, 0); 777 CSR_XS(csr_base, reg_desc->clear_addr, -1); 778 CSR_XS(csr_base, reg_desc->enable_addr, intr_mask); 779 DBG(DBG_ATTACH, NULL, "%s Mask: 0x%llx\n", 780 reg_desc->msg, CSR_XR(csr_base, reg_desc->enable_addr)); 781 DBG(DBG_ATTACH, NULL, "%s Status: 0x%llx\n", 782 reg_desc->msg, CSR_XR(csr_base, reg_desc->status_addr)); 783 DBG(DBG_ATTACH, NULL, "%s Clear: 0x%llx\n", 784 reg_desc->msg, CSR_XR(csr_base, reg_desc->clear_addr)); 785 if (reg_desc->log_addr != NULL) { 786 DBG(DBG_ATTACH, NULL, "%s Log: 0x%llx\n", 787 reg_desc->msg, CSR_XR(csr_base, reg_desc->log_addr)); 788 } 789 } 790 791 void 792 px_err_reg_disable(px_t *px_p, px_err_id_t id) 793 { 794 px_err_reg_desc_t *reg_desc = &px_err_reg_tbl[id]; 795 caddr_t csr_base; 796 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 797 798 /* Get the correct CSR BASE */ 799 if (PX_ERR_XBC(id)) 800 csr_base = (caddr_t)(uintptr_t)pxu_p->px_address[PX_REG_XBC]; 801 else 802 csr_base = (caddr_t)(uintptr_t)pxu_p->px_address[PX_REG_CSR]; 803 804 reg_desc->enabled = B_FALSE; 805 806 switch (id) { 807 case PX_ERR_JBC: 808 case PX_ERR_UBC: 809 case PX_ERR_MMU: 810 case PX_ERR_IMU: 811 case PX_ERR_TLU_UE: 812 case PX_ERR_TLU_CE: 813 case PX_ERR_TLU_OE: 814 case PX_ERR_ILU: 815 if (reg_desc->log_addr != NULL) { 816 CSR_XS(csr_base, reg_desc->log_addr, 0); 817 } 818 CSR_XS(csr_base, reg_desc->enable_addr, 0); 819 break; 820 case PX_ERR_LPU_LINK: 821 case PX_ERR_LPU_PHY: 822 case PX_ERR_LPU_RX: 823 case PX_ERR_LPU_TX: 824 case PX_ERR_LPU_LTSSM: 825 case PX_ERR_LPU_GIGABLZ: 826 if (reg_desc->log_addr != NULL) { 827 CSR_XS(csr_base, reg_desc->log_addr, -1); 828 } 829 CSR_XS(csr_base, reg_desc->enable_addr, -1); 830 break; 831 } 832 } 833 834 /* 835 * px_err_handle: 836 * Common function called by trap, mondo and fabric intr. 837 * o Snap shot current fire registers 838 * o check for safe access 839 * o send ereport and clear snap shot registers 840 * o check severity of snap shot registers 841 * 842 * @param px_p leaf in which to check access 843 * @param derr fm err data structure to be updated 844 * @param caller PX_TRAP_CALL | PX_INTR_CALL 845 * @param chk_cb whether to handle cb registers 846 * @return err PX_OK | PX_NONFATAL | 847 * PX_FATAL_GOS | PX_FATAL_HW | PX_STUCK_FATAL 848 */ 849 int 850 px_err_handle(px_t *px_p, ddi_fm_error_t *derr, int caller, 851 boolean_t chk_cb) 852 { 853 px_err_ss_t ss; 854 int err = PX_OK; 855 856 ASSERT(MUTEX_HELD(&px_p->px_fm_mutex)); 857 858 /* snap shot the current fire registers */ 859 px_err_snapshot(px_p, &ss, chk_cb); 860 861 /* check for safe access */ 862 px_err_safeacc_check(px_p, derr); 863 864 /* send ereports/handle/clear registers */ 865 err = px_err_erpt_and_clr(px_p, derr, &ss); 866 867 /* check for error severity */ 868 err = px_err_check_severity(px_p, derr, err, caller); 869 870 /* Mark the On Trap Handle if an error occured */ 871 if (err != PX_OK) { 872 px_pec_t *pec_p = px_p->px_pec_p; 873 on_trap_data_t *otd = pec_p->pec_ontrap_data; 874 875 if ((otd != NULL) && (otd->ot_prot & OT_DATA_ACCESS)) 876 otd->ot_trap |= OT_DATA_ACCESS; 877 } 878 879 return (err); 880 } 881 882 /* 883 * Static function 884 */ 885 886 /* 887 * px_err_snapshot: 888 * Take a current snap shot of all the fire error registers. This includes 889 * JBC/UBC, DMC, and PEC, unless chk_cb == false; 890 * 891 * @param px_p leaf in which to take the snap shot. 892 * @param ss pre-allocated memory to store the snap shot. 893 * @param chk_cb boolean on whether to store jbc/ubc register. 894 */ 895 static void 896 px_err_snapshot(px_t *px_p, px_err_ss_t *ss, boolean_t chk_cb) 897 { 898 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 899 caddr_t xbc_csr_base = (caddr_t)pxu_p->px_address[PX_REG_XBC]; 900 caddr_t pec_csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 901 px_err_reg_desc_t *reg_desc; 902 int reg_id; 903 904 switch (PX_CHIP_TYPE(pxu_p)) { 905 case PX_CHIP_OBERON: 906 reg_id = PX_ERR_UBC; 907 break; 908 case PX_CHIP_FIRE: 909 reg_id = PX_ERR_JBC; 910 break; 911 default: 912 DBG(DBG_ERR_INTR, NULL, "px_err_snapshot - " 913 "unknown chip type: 0x%x\n", PX_CHIP_TYPE(pxu_p)); 914 reg_id = 0; 915 break; 916 } 917 918 /* snapshot CB interrupt status */ 919 if (chk_cb == B_TRUE) { 920 reg_desc = &px_err_reg_tbl[reg_id]; 921 /* Only look at enabled groups. */ 922 if (reg_desc->enabled == B_TRUE) { 923 ss->err_status[reg_id] = CSR_XR(xbc_csr_base, 924 reg_desc->status_addr); 925 } 926 } else { 927 ss->err_status[reg_id] = 0; 928 } 929 930 /* snapshot DMC/PEC interrupt status */ 931 for (reg_id = 2; reg_id < PX_ERR_REG_KEYS; reg_id += 1) { 932 reg_desc = &px_err_reg_tbl[reg_id]; 933 /* Only look at enabled groups. */ 934 if (reg_desc->enabled == B_TRUE) { 935 ss->err_status[reg_id] = CSR_XR(pec_csr_base, 936 reg_desc->status_addr); 937 } 938 } 939 } 940 941 /* 942 * px_err_erpt_and_clr: 943 * This function does the following thing to all the fire registers based 944 * on an earlier snap shot. 945 * o Send ereport 946 * o Handle the error 947 * o Clear the error 948 * 949 * @param px_p leaf in which to take the snap shot. 950 * @param derr fm err in which the ereport is to be based on 951 * @param ss pre-allocated memory to store the snap shot. 952 */ 953 static int 954 px_err_erpt_and_clr(px_t *px_p, ddi_fm_error_t *derr, px_err_ss_t *ss) 955 { 956 dev_info_t *rpdip = px_p->px_dip; 957 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 958 caddr_t csr_base; 959 px_err_reg_desc_t *err_reg_tbl; 960 px_err_bit_desc_t *err_bit_tbl; 961 px_err_bit_desc_t *err_bit_desc; 962 963 uint64_t *log_mask, *count_mask; 964 uint64_t status_addr, clear_addr; 965 uint64_t ss_reg; 966 967 int (*err_handler)(); 968 int (*erpt_handler)(); 969 int reg_id, key; 970 int err = PX_OK; 971 int biterr; 972 973 ASSERT(MUTEX_HELD(&px_p->px_fm_mutex)); 974 975 /* send erport/handle/clear JBC errors */ 976 for (reg_id = 0; reg_id < PX_ERR_REG_KEYS; reg_id += 1) { 977 /* Get the correct register description table */ 978 err_reg_tbl = &px_err_reg_tbl[reg_id]; 979 980 /* Only look at enabled groups. */ 981 if (err_reg_tbl->enabled != B_TRUE) 982 continue; 983 984 /* Get the correct CSR BASE */ 985 if (PX_ERR_XBC(reg_id)) 986 csr_base = (caddr_t)pxu_p->px_address[PX_REG_XBC]; 987 else 988 csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 989 990 /* Get pointers to masks and register addresses */ 991 log_mask = err_reg_tbl->log_mask_p; 992 count_mask = err_reg_tbl->count_mask_p; 993 status_addr = err_reg_tbl->status_addr; 994 clear_addr = err_reg_tbl->clear_addr; 995 ss_reg = ss->err_status[reg_id]; 996 997 /* Get the register BIT description table */ 998 err_bit_tbl = err_reg_tbl->err_bit_tbl; 999 1000 /* For each known bit in the register send erpt and handle */ 1001 for (key = 0; key < err_reg_tbl->err_bit_keys; key += 1) { 1002 /* Get the bit description table for this register */ 1003 err_bit_desc = &err_bit_tbl[key]; 1004 1005 /* 1006 * If the ss_reg is set for this bit, 1007 * send ereport and handle 1008 */ 1009 if (BIT_TST(ss_reg, err_bit_desc->bit)) { 1010 /* Increment the counter if necessary */ 1011 if (BIT_TST(*count_mask, err_bit_desc->bit)) { 1012 err_bit_desc->counter++; 1013 } 1014 1015 /* Error Handle for this bit */ 1016 err_handler = err_bit_desc->err_handler; 1017 if (err_handler) { 1018 biterr = err_handler(rpdip, 1019 csr_base, 1020 derr, 1021 err_reg_tbl, 1022 err_bit_desc); 1023 err |= biterr; 1024 } 1025 1026 /* Send the ereport if it's an UNEXPECTED err */ 1027 erpt_handler = err_bit_desc->erpt_handler; 1028 if ((derr->fme_flag == DDI_FM_ERR_UNEXPECTED) && 1029 (biterr != PX_OK)) { 1030 if (erpt_handler) 1031 (void) erpt_handler(rpdip, 1032 csr_base, 1033 ss_reg, 1034 derr, 1035 err_bit_desc->bit, 1036 err_bit_desc->class_name); 1037 } 1038 } 1039 } 1040 /* Print register status */ 1041 if (ss_reg & *log_mask) 1042 DBG(DBG_ERR_INTR, rpdip, "<%x>=%16llx %s\n", 1043 status_addr, ss_reg, err_reg_tbl->msg); 1044 1045 /* Clear the register and error */ 1046 CSR_XS(csr_base, clear_addr, ss_reg); 1047 } 1048 1049 return (err); 1050 } 1051 1052 /* 1053 * px_err_check_severity: 1054 * Check the severity of the fire error based on an earlier snapshot 1055 * 1056 * @param px_p leaf in which to take the snap shot. 1057 * @param derr fm err in which the ereport is to be based on 1058 * @param ss pre-allocated memory to store the snap shot. 1059 */ 1060 static int 1061 px_err_check_severity(px_t *px_p, ddi_fm_error_t *derr, int err, int caller) 1062 { 1063 px_pec_t *pec_p = px_p->px_pec_p; 1064 boolean_t is_safeacc = B_FALSE; 1065 1066 /* nothing to do if called with no error */ 1067 if (err == PX_OK) 1068 return (err); 1069 1070 /* Cautious access error handling */ 1071 switch (derr->fme_flag) { 1072 case DDI_FM_ERR_EXPECTED: 1073 if (caller == PX_TRAP_CALL) { 1074 /* 1075 * for ddi_caut_get treat all events as nonfatal 1076 * The trampoline will set err_ena = 0, 1077 * err_status = NONFATAL. 1078 */ 1079 derr->fme_status = DDI_FM_NONFATAL; 1080 is_safeacc = B_TRUE; 1081 } else { 1082 /* 1083 * For ddi_caut_put treat all events as nonfatal. Here 1084 * we have the handle and can call ndi_fm_acc_err_set(). 1085 */ 1086 derr->fme_status = DDI_FM_NONFATAL; 1087 ndi_fm_acc_err_set(pec_p->pec_acc_hdl, derr); 1088 is_safeacc = B_TRUE; 1089 } 1090 break; 1091 case DDI_FM_ERR_PEEK: 1092 case DDI_FM_ERR_POKE: 1093 /* 1094 * For ddi_peek/poke treat all events as nonfatal. 1095 */ 1096 is_safeacc = B_TRUE; 1097 break; 1098 default: 1099 is_safeacc = B_FALSE; 1100 } 1101 1102 /* 1103 * The third argument "err" is passed in as error status from checking 1104 * Fire register, re-adjust error status from safe access. 1105 */ 1106 if (is_safeacc && !(err & PX_FATAL_GOS)) 1107 return (PX_NONFATAL); 1108 1109 return (err); 1110 } 1111 1112 /* predefined convenience functions */ 1113 /* ARGSUSED */ 1114 int 1115 px_err_fatal_hw_handle(dev_info_t *rpdip, caddr_t csr_base, 1116 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1117 px_err_bit_desc_t *err_bit_descr) 1118 { 1119 return (PX_FATAL_HW); 1120 } 1121 1122 /* ARGSUSED */ 1123 int 1124 px_err_fatal_gos_handle(dev_info_t *rpdip, caddr_t csr_base, 1125 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1126 px_err_bit_desc_t *err_bit_descr) 1127 { 1128 return (PX_FATAL_GOS); 1129 } 1130 1131 /* ARGSUSED */ 1132 int 1133 px_err_fatal_stuck_handle(dev_info_t *rpdip, caddr_t csr_base, 1134 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1135 px_err_bit_desc_t *err_bit_descr) 1136 { 1137 return (PX_STUCK_FATAL); 1138 } 1139 1140 /* ARGSUSED */ 1141 int 1142 px_err_fatal_sw_handle(dev_info_t *rpdip, caddr_t csr_base, 1143 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1144 px_err_bit_desc_t *err_bit_descr) 1145 { 1146 return (PX_FATAL_SW); 1147 } 1148 1149 /* ARGSUSED */ 1150 int 1151 px_err_non_fatal_handle(dev_info_t *rpdip, caddr_t csr_base, 1152 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1153 px_err_bit_desc_t *err_bit_descr) 1154 { 1155 return (PX_NONFATAL); 1156 } 1157 1158 /* ARGSUSED */ 1159 int 1160 px_err_ok_handle(dev_info_t *rpdip, caddr_t csr_base, ddi_fm_error_t *derr, 1161 px_err_reg_desc_t *err_reg_descr, px_err_bit_desc_t *err_bit_descr) 1162 { 1163 return (PX_OK); 1164 } 1165 1166 /* ARGSUSED */ 1167 int 1168 px_err_unknown_handle(dev_info_t *rpdip, caddr_t csr_base, ddi_fm_error_t *derr, 1169 px_err_reg_desc_t *err_reg_descr, px_err_bit_desc_t *err_bit_descr) 1170 { 1171 return (PX_ERR_UNKNOWN); 1172 } 1173 1174 /* ARGSUSED */ 1175 PX_ERPT_SEND_DEC(do_not) 1176 { 1177 return (PX_OK); 1178 } 1179 1180 /* UBC FATAL - see io erpt doc, section 1.1 */ 1181 /* ARGSUSED */ 1182 PX_ERPT_SEND_DEC(ubc_fatal) 1183 { 1184 char buf[FM_MAX_CLASS]; 1185 uint64_t memory_ue_log, marked; 1186 char unum[FM_MAX_CLASS]; 1187 int unum_length; 1188 uint64_t device_id = 0; 1189 uint8_t cpu_version = 0; 1190 nvlist_t *resource = NULL; 1191 1192 unum[0] = '\0'; 1193 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1194 1195 memory_ue_log = CSR_XR(csr_base, UBC_MEMORY_UE_LOG); 1196 marked = (memory_ue_log >> UBC_MEMORY_UE_LOG_MARKED) & 1197 UBC_MEMORY_UE_LOG_MARKED_MASK; 1198 1199 if ((strstr(class_name, "ubc.piowtue") != NULL) || 1200 (strstr(class_name, "ubc.piowbeue") != NULL) || 1201 (strstr(class_name, "ubc.piorbeue") != NULL) || 1202 (strstr(class_name, "ubc.dmarduea") != NULL) || 1203 (strstr(class_name, "ubc.dmardueb") != NULL)) { 1204 int eid = (memory_ue_log >> UBC_MEMORY_UE_LOG_EID) & 1205 UBC_MEMORY_UE_LOG_EID_MASK; 1206 (void) strncat(buf, ubc_class_eid_qualifier[eid], 1207 FM_MAX_CLASS); 1208 1209 if (eid == UBC_EID_MEM) { 1210 uint64_t phys_addr = memory_ue_log & 1211 MMU_OBERON_PADDR_MASK; 1212 uint64_t offset = (uint64_t)-1; 1213 1214 resource = fm_nvlist_create(NULL); 1215 if (&plat_get_mem_unum) { 1216 if ((plat_get_mem_unum(0, 1217 phys_addr, 0, B_TRUE, 0, unum, 1218 FM_MAX_CLASS, &unum_length)) != 0) 1219 unum[0] = '\0'; 1220 } 1221 fm_fmri_mem_set(resource, FM_MEM_SCHEME_VERSION, 1222 NULL, unum, NULL, offset); 1223 1224 } else if (eid == UBC_EID_CPU) { 1225 int cpuid = (marked & UBC_MARKED_MAX_CPUID_MASK); 1226 char sbuf[21]; /* sizeof (UINT64_MAX) + '\0' */ 1227 1228 resource = fm_nvlist_create(NULL); 1229 cpu_version = cpunodes[cpuid].version; 1230 device_id = cpunodes[cpuid].device_id; 1231 (void) snprintf(sbuf, sizeof (sbuf), "%lX", 1232 device_id); 1233 (void) fm_fmri_cpu_set(resource, 1234 FM_CPU_SCHEME_VERSION, NULL, cpuid, 1235 &cpu_version, sbuf); 1236 } 1237 } 1238 1239 if (resource) { 1240 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1241 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1242 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1243 OBERON_UBC_ELE, DATA_TYPE_UINT64, 1244 CSR_XR(csr_base, UBC_ERROR_LOG_ENABLE), 1245 OBERON_UBC_IE, DATA_TYPE_UINT64, 1246 CSR_XR(csr_base, UBC_INTERRUPT_ENABLE), 1247 OBERON_UBC_IS, DATA_TYPE_UINT64, 1248 CSR_XR(csr_base, UBC_INTERRUPT_STATUS), 1249 OBERON_UBC_ESS, DATA_TYPE_UINT64, 1250 CSR_XR(csr_base, UBC_ERROR_STATUS_SET), 1251 OBERON_UBC_MUE, DATA_TYPE_UINT64, memory_ue_log, 1252 OBERON_UBC_UNUM, DATA_TYPE_STRING, unum, 1253 OBERON_UBC_DID, DATA_TYPE_UINT64, device_id, 1254 OBERON_UBC_CPUV, DATA_TYPE_UINT32, cpu_version, 1255 OBERON_UBC_RESOURCE, DATA_TYPE_NVLIST, resource, 1256 NULL); 1257 fm_nvlist_destroy(resource, FM_NVA_FREE); 1258 } else { 1259 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1260 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1261 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1262 OBERON_UBC_ELE, DATA_TYPE_UINT64, 1263 CSR_XR(csr_base, UBC_ERROR_LOG_ENABLE), 1264 OBERON_UBC_IE, DATA_TYPE_UINT64, 1265 CSR_XR(csr_base, UBC_INTERRUPT_ENABLE), 1266 OBERON_UBC_IS, DATA_TYPE_UINT64, 1267 CSR_XR(csr_base, UBC_INTERRUPT_STATUS), 1268 OBERON_UBC_ESS, DATA_TYPE_UINT64, 1269 CSR_XR(csr_base, UBC_ERROR_STATUS_SET), 1270 OBERON_UBC_MUE, DATA_TYPE_UINT64, memory_ue_log, 1271 OBERON_UBC_UNUM, DATA_TYPE_STRING, unum, 1272 OBERON_UBC_DID, DATA_TYPE_UINT64, device_id, 1273 OBERON_UBC_CPUV, DATA_TYPE_UINT32, cpu_version, 1274 NULL); 1275 } 1276 1277 return (PX_OK); 1278 } 1279 1280 /* JBC FATAL - see io erpt doc, section 1.1 */ 1281 PX_ERPT_SEND_DEC(jbc_fatal) 1282 { 1283 char buf[FM_MAX_CLASS]; 1284 boolean_t pri = PX_ERR_IS_PRI(bit); 1285 1286 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1287 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1288 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1289 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1290 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1291 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1292 FIRE_JBC_IE, DATA_TYPE_UINT64, 1293 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1294 FIRE_JBC_IS, DATA_TYPE_UINT64, 1295 ss_reg, 1296 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1297 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1298 FIRE_JBC_FEL1, DATA_TYPE_UINT64, 1299 CSR_XR(csr_base, FATAL_ERROR_LOG_1), 1300 FIRE_JBC_FEL2, DATA_TYPE_UINT64, 1301 CSR_XR(csr_base, FATAL_ERROR_LOG_2), 1302 NULL); 1303 1304 return (PX_OK); 1305 } 1306 1307 /* JBC MERGE - see io erpt doc, section 1.2 */ 1308 PX_ERPT_SEND_DEC(jbc_merge) 1309 { 1310 char buf[FM_MAX_CLASS]; 1311 boolean_t pri = PX_ERR_IS_PRI(bit); 1312 1313 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1314 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1315 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1316 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1317 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1318 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1319 FIRE_JBC_IE, DATA_TYPE_UINT64, 1320 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1321 FIRE_JBC_IS, DATA_TYPE_UINT64, 1322 ss_reg, 1323 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1324 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1325 FIRE_JBC_MTEL, DATA_TYPE_UINT64, 1326 CSR_XR(csr_base, MERGE_TRANSACTION_ERROR_LOG), 1327 NULL); 1328 1329 return (PX_OK); 1330 } 1331 1332 /* 1333 * JBC Merge buffer nonfatal errors: 1334 * Merge buffer parity error (rd_buf): dma:read:M:nonfatal 1335 * Merge buffer parity error (wr_buf): dma:write:M:nonfatal 1336 */ 1337 /* ARGSUSED */ 1338 int 1339 px_err_jbc_merge_handle(dev_info_t *rpdip, caddr_t csr_base, 1340 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1341 px_err_bit_desc_t *err_bit_descr) 1342 { 1343 boolean_t pri = PX_ERR_IS_PRI(err_bit_descr->bit); 1344 uint64_t paddr; 1345 int ret; 1346 1347 if (!pri) 1348 return (PX_FATAL_GOS); 1349 1350 paddr = CSR_XR(csr_base, MERGE_TRANSACTION_ERROR_LOG); 1351 paddr &= MERGE_TRANSACTION_ERROR_LOG_ADDRESS_MASK; 1352 1353 ret = px_handle_lookup( 1354 rpdip, DMA_HANDLE, derr->fme_ena, (void *)paddr); 1355 1356 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1357 } 1358 1359 /* JBC Jbusint IN - see io erpt doc, section 1.3 */ 1360 PX_ERPT_SEND_DEC(jbc_in) 1361 { 1362 char buf[FM_MAX_CLASS]; 1363 boolean_t pri = PX_ERR_IS_PRI(bit); 1364 1365 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1366 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1367 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1368 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1369 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1370 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1371 FIRE_JBC_IE, DATA_TYPE_UINT64, 1372 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1373 FIRE_JBC_IS, DATA_TYPE_UINT64, 1374 ss_reg, 1375 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1376 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1377 FIRE_JBC_JITEL1, DATA_TYPE_UINT64, 1378 CSR_XR(csr_base, JBCINT_IN_TRANSACTION_ERROR_LOG), 1379 FIRE_JBC_JITEL2, DATA_TYPE_UINT64, 1380 CSR_XR(csr_base, JBCINT_IN_TRANSACTION_ERROR_LOG_2), 1381 NULL); 1382 1383 return (PX_OK); 1384 } 1385 1386 /* 1387 * JBC Jbusint IN nonfatal errors: PA logged in Jbusint In Transaction Error 1388 * Log Reg[42:0]. 1389 * CE async fault error: nonfatal 1390 * Jbus bus error: dma::nonfatal 1391 * Jbus unmapped error: pio|dma:rdwr:M:nonfatal 1392 * Write data parity error: pio/write:M:nonfatal 1393 * Read data parity error: pio/read:M:nonfatal 1394 * Illegal NCWR bytemask: pio:write:M:nonfatal 1395 * Illegal NCRD bytemask: pio:write:M:nonfatal 1396 * Invalid jbus transaction: nonfatal 1397 */ 1398 /* ARGSUSED */ 1399 int 1400 px_err_jbc_jbusint_in_handle(dev_info_t *rpdip, caddr_t csr_base, 1401 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1402 px_err_bit_desc_t *err_bit_descr) 1403 { 1404 boolean_t pri = PX_ERR_IS_PRI(err_bit_descr->bit); 1405 uint64_t paddr; 1406 int ret; 1407 1408 if (!pri) 1409 return (PX_FATAL_GOS); 1410 1411 paddr = CSR_XR(csr_base, JBCINT_IN_TRANSACTION_ERROR_LOG); 1412 paddr &= JBCINT_IN_TRANSACTION_ERROR_LOG_ADDRESS_MASK; 1413 1414 ret = px_handle_lookup( 1415 rpdip, DMA_HANDLE, derr->fme_ena, (void *)paddr); 1416 1417 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1418 } 1419 1420 1421 /* JBC Jbusint Out - see io erpt doc, section 1.4 */ 1422 PX_ERPT_SEND_DEC(jbc_out) 1423 { 1424 char buf[FM_MAX_CLASS]; 1425 boolean_t pri = PX_ERR_IS_PRI(bit); 1426 1427 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1428 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1429 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1430 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1431 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1432 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1433 FIRE_JBC_IE, DATA_TYPE_UINT64, 1434 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1435 FIRE_JBC_IS, DATA_TYPE_UINT64, 1436 ss_reg, 1437 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1438 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1439 FIRE_JBC_JOTEL1, DATA_TYPE_UINT64, 1440 CSR_XR(csr_base, JBCINT_OUT_TRANSACTION_ERROR_LOG), 1441 FIRE_JBC_JOTEL2, DATA_TYPE_UINT64, 1442 CSR_XR(csr_base, JBCINT_OUT_TRANSACTION_ERROR_LOG_2), 1443 NULL); 1444 1445 return (PX_OK); 1446 } 1447 1448 /* JBC Dmcint ODCD - see io erpt doc, section 1.5 */ 1449 PX_ERPT_SEND_DEC(jbc_odcd) 1450 { 1451 char buf[FM_MAX_CLASS]; 1452 boolean_t pri = PX_ERR_IS_PRI(bit); 1453 1454 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1455 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1456 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1457 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1458 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1459 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1460 FIRE_JBC_IE, DATA_TYPE_UINT64, 1461 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1462 FIRE_JBC_IS, DATA_TYPE_UINT64, 1463 ss_reg, 1464 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1465 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1466 FIRE_JBC_DMC_ODCD, DATA_TYPE_UINT64, 1467 CSR_XR(csr_base, DMCINT_ODCD_ERROR_LOG), 1468 NULL); 1469 1470 return (PX_OK); 1471 } 1472 1473 /* 1474 * JBC Dmcint ODCO nonfatal errer handling - 1475 * Unmapped PIO read error: pio:read:M:nonfatal 1476 * Unmapped PIO write error: pio:write:M:nonfatal 1477 * PIO data parity error: pio:write:M:nonfatal 1478 * Invalid PIO write to PCIe cfg/io, csr, ebus or i2c bus: pio:write:nonfatal 1479 * Invalid PIO read to PCIe cfg/io, csr, ebus or i2c bus: pio:read:nonfatal 1480 */ 1481 /* ARGSUSED */ 1482 int 1483 px_err_jbc_dmcint_odcd_handle(dev_info_t *rpdip, caddr_t csr_base, 1484 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1485 px_err_bit_desc_t *err_bit_descr) 1486 { 1487 boolean_t pri = PX_ERR_IS_PRI(err_bit_descr->bit); 1488 uint64_t paddr; 1489 int ret; 1490 1491 if (!pri) 1492 return (PX_FATAL_GOS); 1493 1494 paddr = CSR_XR(csr_base, DMCINT_ODCD_ERROR_LOG); 1495 paddr &= DMCINT_ODCD_ERROR_LOG_ADDRESS_MASK; 1496 1497 ret = px_handle_lookup( 1498 rpdip, DMA_HANDLE, derr->fme_ena, (void *)paddr); 1499 1500 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1501 } 1502 1503 /* JBC Dmcint IDC - see io erpt doc, section 1.6 */ 1504 PX_ERPT_SEND_DEC(jbc_idc) 1505 { 1506 char buf[FM_MAX_CLASS]; 1507 boolean_t pri = PX_ERR_IS_PRI(bit); 1508 1509 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1510 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1511 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1512 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1513 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1514 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1515 FIRE_JBC_IE, DATA_TYPE_UINT64, 1516 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1517 FIRE_JBC_IS, DATA_TYPE_UINT64, 1518 ss_reg, 1519 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1520 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1521 FIRE_JBC_DMC_IDC, DATA_TYPE_UINT64, 1522 CSR_XR(csr_base, DMCINT_IDC_ERROR_LOG), 1523 NULL); 1524 1525 return (PX_OK); 1526 } 1527 1528 /* JBC CSR - see io erpt doc, section 1.7 */ 1529 PX_ERPT_SEND_DEC(jbc_csr) 1530 { 1531 char buf[FM_MAX_CLASS]; 1532 boolean_t pri = PX_ERR_IS_PRI(bit); 1533 1534 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1535 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1536 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1537 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1538 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1539 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1540 FIRE_JBC_IE, DATA_TYPE_UINT64, 1541 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1542 FIRE_JBC_IS, DATA_TYPE_UINT64, 1543 ss_reg, 1544 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1545 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1546 "jbc-error-reg", DATA_TYPE_UINT64, 1547 CSR_XR(csr_base, CSR_ERROR_LOG), 1548 NULL); 1549 1550 return (PX_OK); 1551 } 1552 1553 /* 1554 * JBC CSR errer handling - 1555 * Ebus ready timeout error: pio:rdwr:M:nonfatal 1556 */ 1557 /* ARGSUSED */ 1558 int 1559 px_err_jbc_csr_handle(dev_info_t *rpdip, caddr_t csr_base, 1560 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1561 px_err_bit_desc_t *err_bit_descr) 1562 { 1563 boolean_t pri = PX_ERR_IS_PRI(err_bit_descr->bit); 1564 uint64_t paddr; 1565 int ret; 1566 1567 if (!pri) 1568 return (PX_FATAL_GOS); 1569 1570 paddr = CSR_XR(csr_base, CSR_ERROR_LOG); 1571 paddr &= CSR_ERROR_LOG_ADDRESS_MASK; 1572 1573 ret = px_handle_lookup( 1574 rpdip, DMA_HANDLE, derr->fme_ena, (void *)paddr); 1575 1576 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1577 } 1578 1579 /* JBC Dmcint IDC - see io erpt doc, section 1.6 */ 1580 1581 /* DMC IMU RDS - see io erpt doc, section 2.1 */ 1582 PX_ERPT_SEND_DEC(imu_rds) 1583 { 1584 char buf[FM_MAX_CLASS]; 1585 boolean_t pri = PX_ERR_IS_PRI(bit); 1586 1587 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1588 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1589 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1590 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1591 FIRE_IMU_ELE, DATA_TYPE_UINT64, 1592 CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE), 1593 FIRE_IMU_IE, DATA_TYPE_UINT64, 1594 CSR_XR(csr_base, IMU_INTERRUPT_ENABLE), 1595 FIRE_IMU_IS, DATA_TYPE_UINT64, 1596 ss_reg, 1597 FIRE_IMU_ESS, DATA_TYPE_UINT64, 1598 CSR_XR(csr_base, IMU_ERROR_STATUS_SET), 1599 FIRE_IMU_RDS, DATA_TYPE_UINT64, 1600 CSR_XR(csr_base, IMU_RDS_ERROR_LOG), 1601 NULL); 1602 1603 return (PX_OK); 1604 } 1605 1606 /* imu function to handle all Received but Not Enabled errors */ 1607 /* ARGSUSED */ 1608 int 1609 px_err_imu_rbne_handle(dev_info_t *rpdip, caddr_t csr_base, 1610 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1611 px_err_bit_desc_t *err_bit_descr) 1612 { 1613 uint64_t imu_log_enable, imu_intr_enable; 1614 int mask = BITMASK(err_bit_descr->bit); 1615 int err = PX_NONFATAL; 1616 1617 imu_log_enable = CSR_XR(csr_base, err_reg_descr->log_addr); 1618 imu_intr_enable = CSR_XR(csr_base, err_reg_descr->enable_addr); 1619 1620 /* 1621 * If matching bit is not set, meaning corresponding rbne not 1622 * enabled, then receiving it indicates some sort of malfunction 1623 * possibly in hardware. 1624 * 1625 * Other wise, software may have intentionally disabled certain 1626 * errors for a period of time within which the occuring of the 1627 * disabled errors become rbne, that is non fatal. 1628 */ 1629 1630 if (!(imu_log_enable & imu_intr_enable & mask)) 1631 err = PX_FATAL_SW; 1632 1633 return (err); 1634 } 1635 1636 /* 1637 * No platforms uses PME. Any PME received is simply logged 1638 * for analysis. 1639 */ 1640 /* ARGSUSED */ 1641 int 1642 px_err_imu_pme_handle(dev_info_t *rpdip, caddr_t csr_base, 1643 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1644 px_err_bit_desc_t *err_bit_descr) 1645 { 1646 px_t *px_p = DIP_TO_STATE(rpdip); 1647 1648 px_p->px_pme_ignored++; 1649 return (PX_NONFATAL); 1650 } 1651 1652 /* handle EQ overflow */ 1653 /* ARGSUSED */ 1654 int 1655 px_err_imu_eq_ovfl_handle(dev_info_t *rpdip, caddr_t csr_base, 1656 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1657 px_err_bit_desc_t *err_bit_descr) 1658 { 1659 px_t *px_p = DIP_TO_STATE(rpdip); 1660 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 1661 msiqid_t eqno; 1662 pci_msiq_state_t msiq_state; 1663 int err = PX_NONFATAL; 1664 int i; 1665 1666 eqno = msiq_state_p->msiq_1st_msiq_id; 1667 for (i = 0; i < msiq_state_p->msiq_cnt; i++) { 1668 if (px_lib_msiq_getstate(rpdip, eqno, &msiq_state) == 1669 DDI_SUCCESS) { 1670 if (msiq_state == PCI_MSIQ_STATE_ERROR) { 1671 err = PX_FATAL_SW; 1672 } 1673 } 1674 } 1675 1676 return (err); 1677 } 1678 1679 /* DMC IMU SCS - see io erpt doc, section 2.2 */ 1680 PX_ERPT_SEND_DEC(imu_scs) 1681 { 1682 char buf[FM_MAX_CLASS]; 1683 boolean_t pri = PX_ERR_IS_PRI(bit); 1684 1685 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1686 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1687 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1688 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1689 FIRE_IMU_ELE, DATA_TYPE_UINT64, 1690 CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE), 1691 FIRE_IMU_IE, DATA_TYPE_UINT64, 1692 CSR_XR(csr_base, IMU_INTERRUPT_ENABLE), 1693 FIRE_IMU_IS, DATA_TYPE_UINT64, 1694 ss_reg, 1695 FIRE_IMU_ESS, DATA_TYPE_UINT64, 1696 CSR_XR(csr_base, IMU_ERROR_STATUS_SET), 1697 FIRE_IMU_SCS, DATA_TYPE_UINT64, 1698 CSR_XR(csr_base, IMU_SCS_ERROR_LOG), 1699 NULL); 1700 1701 return (PX_OK); 1702 } 1703 1704 /* DMC IMU - see io erpt doc, section 2.3 */ 1705 PX_ERPT_SEND_DEC(imu) 1706 { 1707 char buf[FM_MAX_CLASS]; 1708 boolean_t pri = PX_ERR_IS_PRI(bit); 1709 1710 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1711 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1712 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1713 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1714 FIRE_IMU_ELE, DATA_TYPE_UINT64, 1715 CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE), 1716 FIRE_IMU_IE, DATA_TYPE_UINT64, 1717 CSR_XR(csr_base, IMU_INTERRUPT_ENABLE), 1718 FIRE_IMU_IS, DATA_TYPE_UINT64, 1719 ss_reg, 1720 FIRE_IMU_ESS, DATA_TYPE_UINT64, 1721 CSR_XR(csr_base, IMU_ERROR_STATUS_SET), 1722 NULL); 1723 1724 return (PX_OK); 1725 } 1726 1727 /* DMC MMU TFAR/TFSR - see io erpt doc, section 2.4 */ 1728 PX_ERPT_SEND_DEC(mmu_tfar_tfsr) 1729 { 1730 char buf[FM_MAX_CLASS]; 1731 boolean_t pri = PX_ERR_IS_PRI(bit); 1732 1733 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1734 1735 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1736 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1737 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1738 FIRE_MMU_ELE, DATA_TYPE_UINT64, 1739 CSR_XR(csr_base, MMU_ERROR_LOG_ENABLE), 1740 FIRE_MMU_IE, DATA_TYPE_UINT64, 1741 CSR_XR(csr_base, MMU_INTERRUPT_ENABLE), 1742 FIRE_MMU_IS, DATA_TYPE_UINT64, 1743 ss_reg, 1744 FIRE_MMU_ESS, DATA_TYPE_UINT64, 1745 CSR_XR(csr_base, MMU_ERROR_STATUS_SET), 1746 FIRE_MMU_TFAR, DATA_TYPE_UINT64, 1747 CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS), 1748 FIRE_MMU_TFSR, DATA_TYPE_UINT64, 1749 CSR_XR(csr_base, MMU_TRANSLATION_FAULT_STATUS), 1750 NULL); 1751 1752 return (PX_OK); 1753 } 1754 1755 /* DMC MMU - see io erpt doc, section 2.5 */ 1756 PX_ERPT_SEND_DEC(mmu) 1757 { 1758 char buf[FM_MAX_CLASS]; 1759 boolean_t pri = PX_ERR_IS_PRI(bit); 1760 1761 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1762 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1763 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1764 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1765 FIRE_MMU_ELE, DATA_TYPE_UINT64, 1766 CSR_XR(csr_base, MMU_ERROR_LOG_ENABLE), 1767 FIRE_MMU_IE, DATA_TYPE_UINT64, 1768 CSR_XR(csr_base, MMU_INTERRUPT_ENABLE), 1769 FIRE_MMU_IS, DATA_TYPE_UINT64, 1770 ss_reg, 1771 FIRE_MMU_ESS, DATA_TYPE_UINT64, 1772 CSR_XR(csr_base, MMU_ERROR_STATUS_SET), 1773 NULL); 1774 1775 return (PX_OK); 1776 } 1777 1778 /* imu function to handle all Received but Not Enabled errors */ 1779 int 1780 px_err_mmu_rbne_handle(dev_info_t *rpdip, caddr_t csr_base, 1781 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1782 px_err_bit_desc_t *err_bit_descr) 1783 { 1784 boolean_t pri = PX_ERR_IS_PRI(err_bit_descr->bit); 1785 uint64_t mmu_log_enable, mmu_intr_enable; 1786 uint64_t mask = BITMASK(err_bit_descr->bit); 1787 uint64_t mmu_tfa, mmu_ctrl; 1788 uint64_t mmu_enable_bit = 0; 1789 int err = PX_NONFATAL; 1790 int ret; 1791 1792 mmu_log_enable = CSR_XR(csr_base, err_reg_descr->log_addr); 1793 mmu_intr_enable = CSR_XR(csr_base, err_reg_descr->enable_addr); 1794 1795 mmu_tfa = CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS); 1796 mmu_ctrl = CSR_XR(csr_base, MMU_CONTROL_AND_STATUS); 1797 1798 switch (err_bit_descr->bit) { 1799 case MMU_INTERRUPT_STATUS_BYP_ERR_P: 1800 mmu_enable_bit = BITMASK(MMU_CONTROL_AND_STATUS_BE); 1801 break; 1802 case MMU_INTERRUPT_STATUS_TRN_ERR_P: 1803 mmu_enable_bit = BITMASK(MMU_CONTROL_AND_STATUS_TE); 1804 break; 1805 default: 1806 mmu_enable_bit = 0; 1807 break; 1808 } 1809 1810 /* 1811 * If the interrupts are enabled and Translation/Bypass Enable bit 1812 * was set, then panic. This error should not have occured. 1813 */ 1814 if (mmu_log_enable & mmu_intr_enable & 1815 (mmu_ctrl & mmu_enable_bit)) { 1816 err = PX_FATAL_SW; 1817 } else { 1818 if (!pri) 1819 return (PX_FATAL_GOS); 1820 1821 ret = px_handle_lookup( 1822 rpdip, DMA_HANDLE, derr->fme_ena, (void *)mmu_tfa); 1823 err = (ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL; 1824 1825 /* 1826 * S/W bug - this error should always be enabled 1827 */ 1828 1829 /* enable error & intr reporting for this bit */ 1830 CSR_XS(csr_base, MMU_ERROR_LOG_ENABLE, mmu_log_enable | mask); 1831 CSR_XS(csr_base, MMU_INTERRUPT_ENABLE, mmu_intr_enable | mask); 1832 1833 /* enable translation access/bypass enable */ 1834 CSR_XS(csr_base, MMU_CONTROL_AND_STATUS, 1835 mmu_ctrl | mmu_enable_bit); 1836 } 1837 1838 return (err); 1839 } 1840 1841 /* Generic error handling functions that involve MMU Translation Fault Addr */ 1842 /* ARGSUSED */ 1843 int 1844 px_err_mmu_tfa_handle(dev_info_t *rpdip, caddr_t csr_base, 1845 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1846 px_err_bit_desc_t *err_bit_descr) 1847 { 1848 boolean_t pri = PX_ERR_IS_PRI(err_bit_descr->bit); 1849 uint64_t mmu_tfa; 1850 uint_t ret; 1851 1852 if (!pri) 1853 return (PX_FATAL_GOS); 1854 1855 mmu_tfa = CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS); 1856 ret = px_handle_lookup( 1857 rpdip, DMA_HANDLE, derr->fme_ena, (void *)mmu_tfa); 1858 1859 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1860 } 1861 1862 /* MMU Table walk errors */ 1863 /* ARGSUSED */ 1864 int 1865 px_err_mmu_tblwlk_handle(dev_info_t *rpdip, caddr_t csr_base, 1866 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1867 px_err_bit_desc_t *err_bit_descr) 1868 { 1869 boolean_t pri = PX_ERR_IS_PRI(err_bit_descr->bit); 1870 uint64_t mmu_tfa; 1871 uint_t ret; 1872 1873 if (!pri) 1874 return (PX_FATAL_GOS); 1875 1876 mmu_tfa = CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS); 1877 ret = px_handle_lookup( 1878 rpdip, DMA_HANDLE, derr->fme_ena, (void *)mmu_tfa); 1879 1880 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1881 } 1882 1883 /* 1884 * TLU LUP event - if caused by power management activity, then it is expected. 1885 * In all other cases, it is an error. 1886 */ 1887 /* ARGSUSED */ 1888 int 1889 px_err_tlu_lup_handle(dev_info_t *rpdip, caddr_t csr_base, 1890 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1891 px_err_bit_desc_t *err_bit_descr) 1892 { 1893 px_t *px_p = DIP_TO_STATE(rpdip); 1894 1895 /* 1896 * power management code is currently the only segment that sets 1897 * px_lup_pending to indicate its expectation for a healthy LUP 1898 * event. For all other occasions, LUP event should be flaged as 1899 * error condition. 1900 */ 1901 return ((atomic_cas_32(&px_p->px_lup_pending, 1, 0) == 0) ? 1902 PX_NONFATAL : PX_OK); 1903 } 1904 1905 /* 1906 * TLU LDN event - if caused by power management activity, then it is expected. 1907 * In all other cases, it is an error. 1908 */ 1909 /* ARGSUSED */ 1910 int 1911 px_err_tlu_ldn_handle(dev_info_t *rpdip, caddr_t csr_base, 1912 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1913 px_err_bit_desc_t *err_bit_descr) 1914 { 1915 px_t *px_p = DIP_TO_STATE(rpdip); 1916 return ((px_p->px_pm_flags & PX_LDN_EXPECTED) ? PX_OK : PX_NONFATAL); 1917 } 1918 1919 /* PEC ILU none - see io erpt doc, section 3.1 */ 1920 PX_ERPT_SEND_DEC(pec_ilu) 1921 { 1922 char buf[FM_MAX_CLASS]; 1923 boolean_t pri = PX_ERR_IS_PRI(bit); 1924 1925 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1926 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1927 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1928 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1929 FIRE_ILU_ELE, DATA_TYPE_UINT64, 1930 CSR_XR(csr_base, ILU_ERROR_LOG_ENABLE), 1931 FIRE_ILU_IE, DATA_TYPE_UINT64, 1932 CSR_XR(csr_base, ILU_INTERRUPT_ENABLE), 1933 FIRE_ILU_IS, DATA_TYPE_UINT64, 1934 ss_reg, 1935 FIRE_ILU_ESS, DATA_TYPE_UINT64, 1936 CSR_XR(csr_base, ILU_ERROR_STATUS_SET), 1937 NULL); 1938 1939 return (PX_OK); 1940 } 1941 1942 /* PCIEX UE Errors */ 1943 /* ARGSUSED */ 1944 int 1945 px_err_pciex_ue_handle(dev_info_t *rpdip, caddr_t csr_base, 1946 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1947 px_err_bit_desc_t *err_bit_descr) 1948 { 1949 uint32_t mask = (uint32_t)BITMASK(err_bit_descr->bit); 1950 1951 return ((err_bit_descr->bit >= 32 && px_fabric_die_rc_ue_gos) ? 1952 PX_FATAL_GOS : PX_FABRIC_ERR_SEV(mask, px_fabric_die_rc_ue, 1953 px_fabric_die_rc_ue_gos)); 1954 } 1955 1956 /* PCI-E Uncorrectable Errors - see io erpt doc, section 3.2 */ 1957 PX_ERPT_SEND_DEC(pciex_rx_ue) 1958 { 1959 char buf[FM_MAX_CLASS]; 1960 boolean_t pri = PX_ERR_IS_PRI(bit); 1961 1962 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1963 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1964 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1965 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1966 FIRE_TLU_UELE, DATA_TYPE_UINT64, 1967 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE), 1968 FIRE_TLU_UIE, DATA_TYPE_UINT64, 1969 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE), 1970 FIRE_TLU_UIS, DATA_TYPE_UINT64, 1971 ss_reg, 1972 FIRE_TLU_UESS, DATA_TYPE_UINT64, 1973 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_SET), 1974 FIRE_TLU_RUEH1L, DATA_TYPE_UINT64, 1975 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER1_LOG), 1976 FIRE_TLU_RUEH2L, DATA_TYPE_UINT64, 1977 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER2_LOG), 1978 NULL); 1979 1980 return (PX_OK); 1981 } 1982 1983 /* PCI-E Uncorrectable Errors - see io erpt doc, section 3.3 */ 1984 PX_ERPT_SEND_DEC(pciex_tx_ue) 1985 { 1986 char buf[FM_MAX_CLASS]; 1987 boolean_t pri = PX_ERR_IS_PRI(bit); 1988 1989 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1990 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1991 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1992 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1993 FIRE_TLU_UELE, DATA_TYPE_UINT64, 1994 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE), 1995 FIRE_TLU_UIE, DATA_TYPE_UINT64, 1996 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE), 1997 FIRE_TLU_UIS, DATA_TYPE_UINT64, 1998 ss_reg, 1999 FIRE_TLU_UESS, DATA_TYPE_UINT64, 2000 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_SET), 2001 FIRE_TLU_TUEH1L, DATA_TYPE_UINT64, 2002 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER1_LOG), 2003 FIRE_TLU_TUEH2L, DATA_TYPE_UINT64, 2004 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER2_LOG), 2005 NULL); 2006 2007 return (PX_OK); 2008 } 2009 2010 /* PCI-E Uncorrectable Errors - see io erpt doc, section 3.4 */ 2011 PX_ERPT_SEND_DEC(pciex_rx_tx_ue) 2012 { 2013 char buf[FM_MAX_CLASS]; 2014 boolean_t pri = PX_ERR_IS_PRI(bit); 2015 2016 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 2017 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 2018 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 2019 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 2020 FIRE_TLU_UELE, DATA_TYPE_UINT64, 2021 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE), 2022 FIRE_TLU_UIE, DATA_TYPE_UINT64, 2023 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE), 2024 FIRE_TLU_UIS, DATA_TYPE_UINT64, 2025 ss_reg, 2026 FIRE_TLU_UESS, DATA_TYPE_UINT64, 2027 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_SET), 2028 FIRE_TLU_RUEH1L, DATA_TYPE_UINT64, 2029 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER1_LOG), 2030 FIRE_TLU_RUEH2L, DATA_TYPE_UINT64, 2031 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER2_LOG), 2032 FIRE_TLU_TUEH1L, DATA_TYPE_UINT64, 2033 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER1_LOG), 2034 FIRE_TLU_TUEH2L, DATA_TYPE_UINT64, 2035 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER2_LOG), 2036 NULL); 2037 2038 return (PX_OK); 2039 } 2040 2041 /* PCI-E Uncorrectable Errors - see io erpt doc, section 3.5 */ 2042 PX_ERPT_SEND_DEC(pciex_ue) 2043 { 2044 char buf[FM_MAX_CLASS]; 2045 boolean_t pri = PX_ERR_IS_PRI(bit); 2046 2047 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 2048 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 2049 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 2050 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 2051 FIRE_TLU_UELE, DATA_TYPE_UINT64, 2052 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE), 2053 FIRE_TLU_UIE, DATA_TYPE_UINT64, 2054 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE), 2055 FIRE_TLU_UIS, DATA_TYPE_UINT64, 2056 ss_reg, 2057 FIRE_TLU_UESS, DATA_TYPE_UINT64, 2058 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_SET), 2059 NULL); 2060 2061 return (PX_OK); 2062 } 2063 2064 /* PCIEX UE Errors */ 2065 /* ARGSUSED */ 2066 int 2067 px_err_pciex_ce_handle(dev_info_t *rpdip, caddr_t csr_base, 2068 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 2069 px_err_bit_desc_t *err_bit_descr) 2070 { 2071 uint32_t mask = (uint32_t)BITMASK(err_bit_descr->bit); 2072 2073 return ((err_bit_descr->bit >= 32 && px_fabric_die_rc_ce_gos) ? 2074 PX_FATAL_GOS : PX_FABRIC_ERR_SEV(mask, px_fabric_die_rc_ce, 2075 px_fabric_die_rc_ce_gos)); 2076 } 2077 2078 /* PCI-E Correctable Errors - see io erpt doc, section 3.6 */ 2079 PX_ERPT_SEND_DEC(pciex_ce) 2080 { 2081 char buf[FM_MAX_CLASS]; 2082 boolean_t pri = PX_ERR_IS_PRI(bit); 2083 2084 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 2085 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 2086 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 2087 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 2088 FIRE_TLU_CELE, DATA_TYPE_UINT64, 2089 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_LOG_ENABLE), 2090 FIRE_TLU_CIE, DATA_TYPE_UINT64, 2091 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_INTERRUPT_ENABLE), 2092 FIRE_TLU_CIS, DATA_TYPE_UINT64, 2093 ss_reg, 2094 FIRE_TLU_CESS, DATA_TYPE_UINT64, 2095 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_STATUS_SET), 2096 NULL); 2097 2098 return (PX_OK); 2099 } 2100 2101 /* TLU Other Event Status (receive only) - see io erpt doc, section 3.7 */ 2102 PX_ERPT_SEND_DEC(pciex_rx_oe) 2103 { 2104 char buf[FM_MAX_CLASS]; 2105 boolean_t pri = PX_ERR_IS_PRI(bit); 2106 2107 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 2108 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 2109 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 2110 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 2111 FIRE_TLU_OEELE, DATA_TYPE_UINT64, 2112 CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE), 2113 FIRE_TLU_OEIE, DATA_TYPE_UINT64, 2114 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_ENABLE), 2115 FIRE_TLU_OEIS, DATA_TYPE_UINT64, 2116 ss_reg, 2117 FIRE_TLU_OEESS, DATA_TYPE_UINT64, 2118 CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_SET), 2119 FIRE_TLU_RUEH1L, DATA_TYPE_UINT64, 2120 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG), 2121 FIRE_TLU_RUEH2L, DATA_TYPE_UINT64, 2122 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG), 2123 NULL); 2124 2125 return (PX_OK); 2126 } 2127 2128 /* TLU Other Event Status (rx + tx) - see io erpt doc, section 3.8 */ 2129 PX_ERPT_SEND_DEC(pciex_rx_tx_oe) 2130 { 2131 char buf[FM_MAX_CLASS]; 2132 boolean_t pri = PX_ERR_IS_PRI(bit); 2133 2134 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 2135 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 2136 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 2137 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 2138 FIRE_TLU_OEELE, DATA_TYPE_UINT64, 2139 CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE), 2140 FIRE_TLU_OEIE, DATA_TYPE_UINT64, 2141 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_ENABLE), 2142 FIRE_TLU_OEIS, DATA_TYPE_UINT64, 2143 ss_reg, 2144 FIRE_TLU_OEESS, DATA_TYPE_UINT64, 2145 CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_SET), 2146 FIRE_TLU_ROEEH1L, DATA_TYPE_UINT64, 2147 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG), 2148 FIRE_TLU_ROEEH2L, DATA_TYPE_UINT64, 2149 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG), 2150 FIRE_TLU_TOEEH1L, DATA_TYPE_UINT64, 2151 CSR_XR(csr_base, TLU_TRANSMIT_OTHER_EVENT_HEADER1_LOG), 2152 FIRE_TLU_TOEEH2L, DATA_TYPE_UINT64, 2153 CSR_XR(csr_base, TLU_TRANSMIT_OTHER_EVENT_HEADER2_LOG), 2154 NULL); 2155 2156 return (PX_OK); 2157 } 2158 2159 /* TLU Other Event - see io erpt doc, section 3.9 */ 2160 PX_ERPT_SEND_DEC(pciex_oe) 2161 { 2162 char buf[FM_MAX_CLASS]; 2163 boolean_t pri = PX_ERR_IS_PRI(bit); 2164 2165 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 2166 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 2167 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 2168 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 2169 FIRE_TLU_OEELE, DATA_TYPE_UINT64, 2170 CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE), 2171 FIRE_TLU_OEIE, DATA_TYPE_UINT64, 2172 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_ENABLE), 2173 FIRE_TLU_OEIS, DATA_TYPE_UINT64, 2174 ss_reg, 2175 FIRE_TLU_OEESS, DATA_TYPE_UINT64, 2176 CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_SET), 2177 NULL); 2178 2179 return (PX_OK); 2180 } 2181