1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * sun4u Fire Error Handling 31 */ 32 33 #include <sys/types.h> 34 #include <sys/ddi.h> 35 #include <sys/sunddi.h> 36 #include <sys/fm/protocol.h> 37 #include <sys/fm/util.h> 38 #include <sys/pcie.h> 39 #include <sys/pcie_impl.h> 40 #include "px_obj.h" 41 #include <px_regs.h> 42 #include <px_csr.h> 43 #include <sys/membar.h> 44 #include "pcie_pwr.h" 45 #include "px_lib4u.h" 46 #include "px_err.h" 47 #include "px_err_impl.h" 48 49 /* 50 * JBC error bit table 51 */ 52 #define JBC_BIT_DESC(bit, hdl, erpt) \ 53 JBC_INTERRUPT_STATUS_ ## bit ## _P, \ 54 0, \ 55 PX_ERR_BIT_HANDLE(hdl), \ 56 PX_ERPT_SEND(erpt), \ 57 PX_ERR_JBC_CLASS(bit) 58 px_err_bit_desc_t px_err_cb_tbl[] = { 59 /* JBC FATAL - see io erpt doc, section 1.1 */ 60 { JBC_BIT_DESC(MB_PEA, fatal_hw, jbc_fatal) }, 61 { JBC_BIT_DESC(CPE, fatal_hw, jbc_fatal) }, 62 { JBC_BIT_DESC(APE, fatal_hw, jbc_fatal) }, 63 { JBC_BIT_DESC(PIO_CPE, fatal_hw, jbc_fatal) }, 64 { JBC_BIT_DESC(JTCEEW, fatal_hw, jbc_fatal) }, 65 { JBC_BIT_DESC(JTCEEI, fatal_hw, jbc_fatal) }, 66 { JBC_BIT_DESC(JTCEER, fatal_hw, jbc_fatal) }, 67 68 /* JBC MERGE - see io erpt doc, section 1.2 */ 69 { JBC_BIT_DESC(MB_PER, jbc_merge, jbc_merge) }, 70 { JBC_BIT_DESC(MB_PEW, jbc_merge, jbc_merge) }, 71 72 /* JBC Jbusint IN - see io erpt doc, section 1.3 */ 73 { JBC_BIT_DESC(UE_ASYN, fatal_gos, jbc_in) }, 74 { JBC_BIT_DESC(CE_ASYN, jbc_jbusint_in, jbc_in) }, 75 { JBC_BIT_DESC(JTE, fatal_gos, jbc_in) }, 76 { JBC_BIT_DESC(JBE, jbc_jbusint_in, jbc_in) }, 77 { JBC_BIT_DESC(JUE, jbc_jbusint_in, jbc_in) }, 78 { JBC_BIT_DESC(ICISE, fatal_gos, jbc_in) }, 79 { JBC_BIT_DESC(WR_DPE, jbc_jbusint_in, jbc_in) }, 80 { JBC_BIT_DESC(RD_DPE, jbc_jbusint_in, jbc_in) }, 81 { JBC_BIT_DESC(ILL_BMW, jbc_jbusint_in, jbc_in) }, 82 { JBC_BIT_DESC(ILL_BMR, jbc_jbusint_in, jbc_in) }, 83 { JBC_BIT_DESC(BJC, jbc_jbusint_in, jbc_in) }, 84 85 /* JBC Jbusint Out - see io erpt doc, section 1.4 */ 86 { JBC_BIT_DESC(IJP, fatal_gos, jbc_out) }, 87 88 /* JBC Dmcint ODCD - see io erpt doc, section 1.5 */ 89 { JBC_BIT_DESC(PIO_UNMAP_RD, jbc_dmcint_odcd, jbc_odcd) }, 90 { JBC_BIT_DESC(ILL_ACC_RD, jbc_dmcint_odcd, jbc_odcd) }, 91 { JBC_BIT_DESC(PIO_UNMAP, jbc_dmcint_odcd, jbc_odcd) }, 92 { JBC_BIT_DESC(PIO_DPE, jbc_dmcint_odcd, jbc_odcd) }, 93 { JBC_BIT_DESC(PIO_CPE, non_fatal, jbc_odcd) }, 94 { JBC_BIT_DESC(ILL_ACC, jbc_dmcint_odcd, jbc_odcd) }, 95 96 /* JBC Dmcint IDC - see io erpt doc, section 1.6 */ 97 { JBC_BIT_DESC(UNSOL_RD, non_fatal, jbc_idc) }, 98 { JBC_BIT_DESC(UNSOL_INTR, non_fatal, jbc_idc) }, 99 100 /* JBC CSR - see io erpt doc, section 1.7 */ 101 { JBC_BIT_DESC(EBUS_TO, jbc_csr, jbc_csr) } 102 }; 103 104 #define px_err_cb_keys \ 105 (sizeof (px_err_cb_tbl)) / (sizeof (px_err_bit_desc_t)) 106 107 /* 108 * DMC error bit tables 109 */ 110 #define IMU_BIT_DESC(bit, hdl, erpt) \ 111 IMU_INTERRUPT_STATUS_ ## bit ## _P, \ 112 0, \ 113 PX_ERR_BIT_HANDLE(hdl), \ 114 PX_ERPT_SEND(erpt), \ 115 PX_ERR_DMC_CLASS(bit) 116 px_err_bit_desc_t px_err_imu_tbl[] = { 117 /* DMC IMU RDS - see io erpt doc, section 2.1 */ 118 { IMU_BIT_DESC(MSI_MAL_ERR, non_fatal, imu_rds) }, 119 { IMU_BIT_DESC(MSI_PAR_ERR, fatal_stuck, imu_rds) }, 120 { IMU_BIT_DESC(PMEACK_MES_NOT_EN, imu_rbne, imu_rds) }, 121 { IMU_BIT_DESC(PMPME_MES_NOT_EN, imu_pme, imu_rds) }, 122 { IMU_BIT_DESC(FATAL_MES_NOT_EN, imu_rbne, imu_rds) }, 123 { IMU_BIT_DESC(NONFATAL_MES_NOT_EN, imu_rbne, imu_rds) }, 124 { IMU_BIT_DESC(COR_MES_NOT_EN, imu_rbne, imu_rds) }, 125 { IMU_BIT_DESC(MSI_NOT_EN, imu_rbne, imu_rds) }, 126 127 /* DMC IMU SCS - see io erpt doc, section 2.2 */ 128 { IMU_BIT_DESC(EQ_NOT_EN, imu_rbne, imu_rds) }, 129 130 /* DMC IMU - see io erpt doc, section 2.3 */ 131 { IMU_BIT_DESC(EQ_OVER, imu_eq_ovfl, imu) } 132 }; 133 134 #define px_err_imu_keys (sizeof (px_err_imu_tbl)) / (sizeof (px_err_bit_desc_t)) 135 136 /* mmu errors */ 137 #define MMU_BIT_DESC(bit, hdl, erpt) \ 138 MMU_INTERRUPT_STATUS_ ## bit ## _P, \ 139 0, \ 140 PX_ERR_BIT_HANDLE(hdl), \ 141 PX_ERPT_SEND(erpt), \ 142 PX_ERR_DMC_CLASS(bit) 143 px_err_bit_desc_t px_err_mmu_tbl[] = { 144 /* DMC MMU TFAR/TFSR - see io erpt doc, section 2.4 */ 145 { MMU_BIT_DESC(BYP_ERR, mmu_rbne, mmu_tfar_tfsr) }, 146 { MMU_BIT_DESC(BYP_OOR, mmu_tfa, mmu_tfar_tfsr) }, 147 { MMU_BIT_DESC(TRN_ERR, mmu_rbne, mmu_tfar_tfsr) }, 148 { MMU_BIT_DESC(TRN_OOR, mmu_tfa, mmu_tfar_tfsr) }, 149 { MMU_BIT_DESC(TTE_INV, mmu_tfa, mmu_tfar_tfsr) }, 150 { MMU_BIT_DESC(TTE_PRT, mmu_tfa, mmu_tfar_tfsr) }, 151 { MMU_BIT_DESC(TTC_DPE, mmu_tfa, mmu_tfar_tfsr) }, 152 { MMU_BIT_DESC(TBW_DME, mmu_tblwlk, mmu_tfar_tfsr) }, 153 { MMU_BIT_DESC(TBW_UDE, mmu_tblwlk, mmu_tfar_tfsr) }, 154 { MMU_BIT_DESC(TBW_ERR, mmu_tblwlk, mmu_tfar_tfsr) }, 155 { MMU_BIT_DESC(TBW_DPE, mmu_tblwlk, mmu_tfar_tfsr) }, 156 157 /* DMC MMU - see io erpt doc, section 2.5 */ 158 { MMU_BIT_DESC(TTC_CAE, non_fatal, mmu) } 159 }; 160 #define px_err_mmu_keys (sizeof (px_err_mmu_tbl)) / (sizeof (px_err_bit_desc_t)) 161 162 /* 163 * PEC error bit tables 164 */ 165 #define ILU_BIT_DESC(bit, hdl, erpt) \ 166 ILU_INTERRUPT_STATUS_ ## bit ## _P, \ 167 0, \ 168 PX_ERR_BIT_HANDLE(hdl), \ 169 PX_ERPT_SEND(erpt), \ 170 PX_ERR_PEC_CLASS(bit) 171 px_err_bit_desc_t px_err_ilu_tbl[] = { 172 /* PEC ILU none - see io erpt doc, section 3.1 */ 173 { ILU_BIT_DESC(IHB_PE, fatal_gos, pec_ilu) } 174 }; 175 #define px_err_ilu_keys \ 176 (sizeof (px_err_ilu_tbl)) / (sizeof (px_err_bit_desc_t)) 177 178 /* 179 * PEC UE errors implementation is incomplete pending PCIE generic 180 * fabric rules. Must handle both PRIMARY and SECONDARY errors. 181 */ 182 /* pec ue errors */ 183 #define TLU_UC_BIT_DESC(bit, hdl, erpt) \ 184 TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _P, \ 185 0, \ 186 PX_ERR_BIT_HANDLE(hdl), \ 187 PX_ERPT_SEND(erpt), \ 188 PX_ERR_PEC_CLASS(bit) }, \ 189 { TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _S, \ 190 0, \ 191 PX_ERR_BIT_HANDLE(hdl), \ 192 PX_ERPT_SEND(erpt), \ 193 PX_ERR_PEC_CLASS(bit) 194 px_err_bit_desc_t px_err_tlu_ue_tbl[] = { 195 /* PCI-E Receive Uncorrectable Errors - see io erpt doc, section 3.2 */ 196 { TLU_UC_BIT_DESC(UR, pciex_ue, pciex_rx_ue) }, 197 { TLU_UC_BIT_DESC(UC, pciex_ue, pciex_rx_ue) }, 198 199 /* PCI-E Transmit Uncorrectable Errors - see io erpt doc, section 3.3 */ 200 { TLU_UC_BIT_DESC(CTO, pciex_ue, pciex_tx_ue) }, 201 { TLU_UC_BIT_DESC(ROF, pciex_ue, pciex_tx_ue) }, 202 203 /* PCI-E Rx/Tx Uncorrectable Errors - see io erpt doc, section 3.4 */ 204 { TLU_UC_BIT_DESC(MFP, pciex_ue, pciex_rx_tx_ue) }, 205 { TLU_UC_BIT_DESC(PP, pciex_ue, pciex_rx_tx_ue) }, 206 207 /* Other PCI-E Uncorrectable Errors - see io erpt doc, section 3.5 */ 208 { TLU_UC_BIT_DESC(FCP, pciex_ue, pciex_ue) }, 209 { TLU_UC_BIT_DESC(DLP, pciex_ue, pciex_ue) }, 210 { TLU_UC_BIT_DESC(TE, pciex_ue, pciex_ue) }, 211 212 /* Not used */ 213 { TLU_UC_BIT_DESC(CA, pciex_ue, do_not) } 214 }; 215 #define px_err_tlu_ue_keys \ 216 (sizeof (px_err_tlu_ue_tbl)) / (sizeof (px_err_bit_desc_t)) 217 218 /* 219 * PEC CE errors implementation is incomplete pending PCIE generic 220 * fabric rules. 221 */ 222 /* pec ce errors */ 223 #define TLU_CE_BIT_DESC(bit, hdl, erpt) \ 224 TLU_CORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _P, \ 225 0, \ 226 PX_ERR_BIT_HANDLE(hdl), \ 227 PX_ERPT_SEND(erpt), \ 228 PX_ERR_PEC_CLASS(bit) }, \ 229 { TLU_CORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _S, \ 230 0, \ 231 PX_ERR_BIT_HANDLE(hdl), \ 232 PX_ERPT_SEND(erpt), \ 233 PX_ERR_PEC_CLASS(bit) 234 px_err_bit_desc_t px_err_tlu_ce_tbl[] = { 235 /* PCI-E Correctable Errors - see io erpt doc, section 3.6 */ 236 { TLU_CE_BIT_DESC(RTO, pciex_ce, pciex_ce) }, 237 { TLU_CE_BIT_DESC(RNR, pciex_ce, pciex_ce) }, 238 { TLU_CE_BIT_DESC(BDP, pciex_ce, pciex_ce) }, 239 { TLU_CE_BIT_DESC(BTP, pciex_ce, pciex_ce) }, 240 { TLU_CE_BIT_DESC(RE, pciex_ce, pciex_ce) } 241 }; 242 #define px_err_tlu_ce_keys \ 243 (sizeof (px_err_tlu_ce_tbl)) / (sizeof (px_err_bit_desc_t)) 244 245 /* pec oe errors */ 246 #define TLU_OE_BIT_DESC(bit, hdl, erpt) \ 247 TLU_OTHER_EVENT_STATUS_CLEAR_ ## bit ## _P, \ 248 0, \ 249 PX_ERR_BIT_HANDLE(hdl), \ 250 PX_ERPT_SEND(erpt), \ 251 PX_ERR_PEC_CLASS(bit) 252 px_err_bit_desc_t px_err_tlu_oe_tbl[] = { 253 /* 254 * TLU Other Event Status (receive only) - see io erpt doc, section 3.7 255 */ 256 { TLU_OE_BIT_DESC(MRC, fatal_hw, pciex_rx_oe) }, 257 258 /* TLU Other Event Status (rx + tx) - see io erpt doc, section 3.8 */ 259 { TLU_OE_BIT_DESC(WUC, non_fatal, pciex_rx_tx_oe) }, 260 { TLU_OE_BIT_DESC(RUC, non_fatal, pciex_rx_tx_oe) }, 261 { TLU_OE_BIT_DESC(CRS, non_fatal, pciex_rx_tx_oe) }, 262 263 /* TLU Other Event - see io erpt doc, section 3.9 */ 264 { TLU_OE_BIT_DESC(IIP, fatal_gos, pciex_oe) }, 265 { TLU_OE_BIT_DESC(EDP, fatal_gos, pciex_oe) }, 266 { TLU_OE_BIT_DESC(EHP, fatal_gos, pciex_oe) }, 267 { TLU_OE_BIT_DESC(LIN, non_fatal, pciex_oe) }, 268 { TLU_OE_BIT_DESC(LRS, non_fatal, pciex_oe) }, 269 { TLU_OE_BIT_DESC(LDN, non_fatal, pciex_ldn) }, 270 { TLU_OE_BIT_DESC(LUP, tlu_lup, pciex_lup) }, 271 { TLU_OE_BIT_DESC(ERU, fatal_gos, pciex_oe) }, 272 { TLU_OE_BIT_DESC(ERO, fatal_gos, pciex_oe) }, 273 { TLU_OE_BIT_DESC(EMP, fatal_gos, pciex_oe) }, 274 { TLU_OE_BIT_DESC(EPE, fatal_gos, pciex_oe) }, 275 { TLU_OE_BIT_DESC(ERP, fatal_gos, pciex_oe) }, 276 { TLU_OE_BIT_DESC(EIP, fatal_gos, pciex_oe) } 277 }; 278 279 #define px_err_tlu_oe_keys \ 280 (sizeof (px_err_tlu_oe_tbl)) / (sizeof (px_err_bit_desc_t)) 281 282 /* 283 * All the following tables below are for LPU Interrupts. These interrupts 284 * are *NOT* error interrupts, but event status interrupts. 285 * 286 * These events are probably of most interest to: 287 * o Hotplug 288 * o Power Management 289 * o etc... 290 * 291 * There are also a few events that would be interresting for FMA. 292 * Again none of the regiseters below state that an error has occured 293 * or that data has been lost. If anything, they give status that an 294 * error is *about* to occur. examples 295 * o INT_SKP_ERR - indicates clock between fire and child is too far 296 * off and is most unlikely able to compensate 297 * o INT_TX_PAR_ERR - A parity error occured in ONE lane. This is 298 * HW recoverable, but will like end up as a future 299 * fabric error as well. 300 * 301 * For now, we don't care about any of these errors and should be ignore, 302 * but cleared. 303 */ 304 305 /* LPU Link Interrupt Table */ 306 #define LPUL_BIT_DESC(bit, hdl, erpt) \ 307 LPU_LINK_LAYER_INTERRUPT_AND_STATUS_INT_ ## bit, \ 308 0, \ 309 NULL, \ 310 NULL, \ 311 "" 312 px_err_bit_desc_t px_err_lpul_tbl[] = { 313 { LPUL_BIT_DESC(LINK_ERR_ACT, NULL, NULL) } 314 }; 315 #define px_err_lpul_keys \ 316 (sizeof (px_err_lpul_tbl)) / (sizeof (px_err_bit_desc_t)) 317 318 /* LPU Physical Interrupt Table */ 319 #define LPUP_BIT_DESC(bit, hdl, erpt) \ 320 LPU_PHY_LAYER_INTERRUPT_AND_STATUS_INT_ ## bit, \ 321 0, \ 322 NULL, \ 323 NULL, \ 324 "" 325 px_err_bit_desc_t px_err_lpup_tbl[] = { 326 { LPUP_BIT_DESC(PHY_LAYER_ERR, NULL, NULL) } 327 }; 328 #define px_err_lpup_keys \ 329 (sizeof (px_err_lpup_tbl)) / (sizeof (px_err_bit_desc_t)) 330 331 /* LPU Receive Interrupt Table */ 332 #define LPUR_BIT_DESC(bit, hdl, erpt) \ 333 LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS_INT_ ## bit, \ 334 0, \ 335 NULL, \ 336 NULL, \ 337 "" 338 px_err_bit_desc_t px_err_lpur_tbl[] = { 339 { LPUR_BIT_DESC(RCV_PHY, NULL, NULL) } 340 }; 341 #define px_err_lpur_keys \ 342 (sizeof (px_err_lpur_tbl)) / (sizeof (px_err_bit_desc_t)) 343 344 /* LPU Transmit Interrupt Table */ 345 #define LPUX_BIT_DESC(bit, hdl, erpt) \ 346 LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS_INT_ ## bit, \ 347 0, \ 348 NULL, \ 349 NULL, \ 350 "" 351 px_err_bit_desc_t px_err_lpux_tbl[] = { 352 { LPUX_BIT_DESC(UNMSK, NULL, NULL) } 353 }; 354 #define px_err_lpux_keys \ 355 (sizeof (px_err_lpux_tbl)) / (sizeof (px_err_bit_desc_t)) 356 357 /* LPU LTSSM Interrupt Table */ 358 #define LPUS_BIT_DESC(bit, hdl, erpt) \ 359 LPU_LTSSM_INTERRUPT_AND_STATUS_INT_ ## bit, \ 360 0, \ 361 NULL, \ 362 NULL, \ 363 "" 364 px_err_bit_desc_t px_err_lpus_tbl[] = { 365 { LPUS_BIT_DESC(ANY, NULL, NULL) } 366 }; 367 #define px_err_lpus_keys \ 368 (sizeof (px_err_lpus_tbl)) / (sizeof (px_err_bit_desc_t)) 369 370 /* LPU Gigablaze Glue Interrupt Table */ 371 #define LPUG_BIT_DESC(bit, hdl, erpt) \ 372 LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS_INT_ ## bit, \ 373 0, \ 374 NULL, \ 375 NULL, \ 376 "" 377 px_err_bit_desc_t px_err_lpug_tbl[] = { 378 { LPUG_BIT_DESC(GLOBL_UNMSK, NULL, NULL) } 379 }; 380 #define px_err_lpug_keys \ 381 (sizeof (px_err_lpug_tbl)) / (sizeof (px_err_bit_desc_t)) 382 383 384 /* Mask and Tables */ 385 #define MnT6(pre) \ 386 B_FALSE, \ 387 &px_ ## pre ## _intr_mask, \ 388 &px_ ## pre ## _log_mask, \ 389 &px_ ## pre ## _count_mask, \ 390 px_err_ ## pre ## _tbl, \ 391 px_err_ ## pre ## _keys, \ 392 0 393 394 /* LPU Registers Addresses */ 395 #define LR4(pre) \ 396 NULL, \ 397 LPU_ ## pre ## _INTERRUPT_MASK, \ 398 LPU_ ## pre ## _INTERRUPT_AND_STATUS, \ 399 LPU_ ## pre ## _INTERRUPT_AND_STATUS 400 401 /* LPU Registers Addresses with Irregularities */ 402 #define LR4_FIXME(pre) \ 403 NULL, \ 404 LPU_ ## pre ## _INTERRUPT_MASK, \ 405 LPU_ ## pre ## _LAYER_INTERRUPT_AND_STATUS, \ 406 LPU_ ## pre ## _LAYER_INTERRUPT_AND_STATUS 407 408 /* TLU Registers Addresses */ 409 #define TR4(pre) \ 410 TLU_ ## pre ## _LOG_ENABLE, \ 411 TLU_ ## pre ## _INTERRUPT_ENABLE, \ 412 TLU_ ## pre ## _INTERRUPT_STATUS, \ 413 TLU_ ## pre ## _STATUS_CLEAR 414 415 /* Registers Addresses for JBC, MMU, IMU and ILU */ 416 #define R4(pre) \ 417 pre ## _ERROR_LOG_ENABLE, \ 418 pre ## _INTERRUPT_ENABLE, \ 419 pre ## _INTERRUPT_STATUS, \ 420 pre ## _ERROR_STATUS_CLEAR 421 422 /* 423 * Register error handling tables. 424 * The ID Field (first field) is identified by an enum px_err_id_t. 425 * It is located in px_err.h 426 */ 427 px_err_reg_desc_t px_err_reg_tbl[] = { 428 { MnT6(cb), R4(JBC), "JBC Error"}, 429 { MnT6(mmu), R4(MMU), "MMU Error"}, 430 { MnT6(imu), R4(IMU), "IMU Error"}, 431 { MnT6(tlu_ue), TR4(UNCORRECTABLE_ERROR), "TLU UE"}, 432 { MnT6(tlu_ce), TR4(CORRECTABLE_ERROR), "TLU CE"}, 433 { MnT6(tlu_oe), TR4(OTHER_EVENT), "TLU OE"}, 434 { MnT6(ilu), R4(ILU), "ILU Error"}, 435 { MnT6(lpul), LR4(LINK_LAYER), "LPU Link Layer"}, 436 { MnT6(lpup), LR4_FIXME(PHY), "LPU Phy Layer"}, 437 { MnT6(lpur), LR4(RECEIVE_PHY), "LPU RX Phy Layer"}, 438 { MnT6(lpux), LR4(TRANSMIT_PHY), "LPU TX Phy Layer"}, 439 { MnT6(lpus), LR4(LTSSM), "LPU LTSSM"}, 440 { MnT6(lpug), LR4(GIGABLAZE_GLUE), "LPU GigaBlaze Glue"} 441 }; 442 #define PX_ERR_REG_KEYS (sizeof (px_err_reg_tbl)) / (sizeof (px_err_reg_tbl[0])) 443 444 typedef struct px_err_ss { 445 uint64_t err_status[PX_ERR_REG_KEYS]; 446 } px_err_ss_t; 447 448 static void px_err_snapshot(px_t *px_p, px_err_ss_t *ss, boolean_t chkjbc); 449 static int px_err_erpt_and_clr(px_t *px_p, ddi_fm_error_t *derr, 450 px_err_ss_t *ss); 451 static int px_err_check_severity(px_t *px_p, ddi_fm_error_t *derr, 452 int err, int caller); 453 454 /* 455 * px_err_cb_intr: 456 * Interrupt handler for the JBC block. 457 * o lock 458 * o create derr 459 * o px_err_handle(leaf1, with jbc) 460 * o px_err_handle(leaf2, without jbc) 461 * o dispatch (leaf1) 462 * o dispatch (leaf2) 463 * o unlock 464 * o handle error: fatal? fm_panic() : return INTR_CLAIMED) 465 */ 466 uint_t 467 px_err_cb_intr(caddr_t arg) 468 { 469 px_fault_t *px_fault_p = (px_fault_t *)arg; 470 dev_info_t *rpdip = px_fault_p->px_fh_dip; 471 dev_info_t *leafdip; 472 px_t *px_p = DIP_TO_STATE(rpdip); 473 px_cb_t *cb_p = px_p->px_cb_p; 474 int err = PX_OK; 475 int ret = DDI_FM_OK; 476 int fatal = 0; 477 int nonfatal = 0; 478 int unknown = 0; 479 int i; 480 boolean_t chkjbc = B_TRUE; 481 ddi_fm_error_t derr; 482 483 /* Create the derr */ 484 bzero(&derr, sizeof (ddi_fm_error_t)); 485 derr.fme_version = DDI_FME_VERSION; 486 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 487 derr.fme_flag = DDI_FM_ERR_UNEXPECTED; 488 489 mutex_enter(&cb_p->xbc_fm_mutex); 490 491 /* send ereport/handle/clear for ALL fire leaves */ 492 for (i = 0; i < PX_CB_MAX_LEAF; i++) { 493 if ((px_p = cb_p->xbc_px_list[i]) == NULL) 494 continue; 495 496 err |= px_err_handle(px_p, &derr, PX_INTR_CALL, chkjbc); 497 chkjbc = B_FALSE; 498 } 499 500 /* Check all child devices for errors on ALL fire leaves */ 501 for (i = 0; i < PX_CB_MAX_LEAF; i++) { 502 if ((px_p = cb_p->xbc_px_list[i]) != NULL) { 503 leafdip = px_p->px_dip; 504 ret = ndi_fm_handler_dispatch(leafdip, NULL, &derr); 505 switch (ret) { 506 case DDI_FM_FATAL: 507 fatal++; 508 break; 509 case DDI_FM_NONFATAL: 510 nonfatal++; 511 break; 512 case DDI_FM_UNKNOWN: 513 unknown++; 514 break; 515 default: 516 break; 517 } 518 } 519 } 520 521 /* Set the intr state to idle for the leaf that received the mondo */ 522 (void) px_lib_intr_setstate(rpdip, px_fault_p->px_fh_sysino, 523 INTR_IDLE_STATE); 524 525 mutex_exit(&cb_p->xbc_fm_mutex); 526 527 /* 528 * PX_FATAL_HW error is diagnosed after system recovered from 529 * HW initiated reset, therefore no furthur handling is required. 530 */ 531 if (fatal || err & (PX_FATAL_GOS | PX_FATAL_SW)) 532 fm_panic("Fatal System Bus Error has occurred\n"); 533 534 return (DDI_INTR_CLAIMED); 535 } 536 537 /* 538 * px_err_dmc_pec_intr: 539 * Interrupt handler for the DMC/PEC block. 540 * o lock 541 * o create derr 542 * o px_err_handle(leaf, with jbc) 543 * o dispatch (leaf) 544 * o unlock 545 * o handle error: fatal? fm_panic() : return INTR_CLAIMED) 546 */ 547 uint_t 548 px_err_dmc_pec_intr(caddr_t arg) 549 { 550 px_fault_t *px_fault_p = (px_fault_t *)arg; 551 dev_info_t *rpdip = px_fault_p->px_fh_dip; 552 px_t *px_p = DIP_TO_STATE(rpdip); 553 px_cb_t *cb_p = px_p->px_cb_p; 554 int err = PX_OK; 555 int ret = DDI_FM_OK; 556 ddi_fm_error_t derr; 557 558 /* Create the derr */ 559 bzero(&derr, sizeof (ddi_fm_error_t)); 560 derr.fme_version = DDI_FME_VERSION; 561 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 562 derr.fme_flag = DDI_FM_ERR_UNEXPECTED; 563 564 mutex_enter(&cb_p->xbc_fm_mutex); 565 566 /* send ereport/handle/clear fire registers */ 567 err |= px_err_handle(px_p, &derr, PX_INTR_CALL, B_TRUE); 568 569 /* Check all child devices for errors */ 570 ret = ndi_fm_handler_dispatch(rpdip, NULL, &derr); 571 572 /* Set the interrupt state to idle */ 573 (void) px_lib_intr_setstate(rpdip, px_fault_p->px_fh_sysino, 574 INTR_IDLE_STATE); 575 576 mutex_exit(&cb_p->xbc_fm_mutex); 577 578 /* 579 * PX_FATAL_HW indicates a condition recovered from Fatal-Reset, 580 * therefore it does not cause panic. 581 */ 582 if ((err & (PX_FATAL_GOS | PX_FATAL_SW)) || (ret == DDI_FM_FATAL)) 583 fm_panic("Fatal System Port Error has occurred\n"); 584 585 return (DDI_INTR_CLAIMED); 586 } 587 588 /* 589 * Error register are being handled by px_hlib xxx_init functions. 590 * They are also called again by px_err_add_intr for mondo62 and 63 591 * from px_cb_attach and px_attach 592 */ 593 void 594 px_err_reg_enable(px_t *px_p, px_err_id_t id) 595 { 596 px_err_reg_desc_t *reg_desc = &px_err_reg_tbl[id]; 597 uint64_t intr_mask = *reg_desc->intr_mask_p; 598 uint64_t log_mask = *reg_desc->log_mask_p; 599 caddr_t csr_base; 600 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 601 602 if (id == PX_ERR_JBC) 603 csr_base = (caddr_t)pxu_p->px_address[PX_REG_XBC]; 604 else 605 csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 606 607 reg_desc->enabled = B_TRUE; 608 609 /* Enable logs if it exists */ 610 if (reg_desc->log_addr != NULL) 611 CSR_XS(csr_base, reg_desc->log_addr, log_mask); 612 613 /* 614 * For readability you in code you set 1 to enable an interrupt. 615 * But in Fire it's backwards. You set 1 to *disable* an intr. 616 * Reverse the user tunable intr mask field. 617 * 618 * Disable All Errors 619 * Clear All Errors 620 * Enable Errors 621 */ 622 CSR_XS(csr_base, reg_desc->enable_addr, 0); 623 CSR_XS(csr_base, reg_desc->clear_addr, -1); 624 CSR_XS(csr_base, reg_desc->enable_addr, intr_mask); 625 DBG(DBG_ATTACH, NULL, "%s Mask: 0x%llx\n", 626 reg_desc->msg, CSR_XR(csr_base, reg_desc->enable_addr)); 627 DBG(DBG_ATTACH, NULL, "%s Status: 0x%llx\n", 628 reg_desc->msg, CSR_XR(csr_base, reg_desc->status_addr)); 629 DBG(DBG_ATTACH, NULL, "%s Clear: 0x%llx\n", 630 reg_desc->msg, CSR_XR(csr_base, reg_desc->clear_addr)); 631 if (reg_desc->log_addr != NULL) { 632 DBG(DBG_ATTACH, NULL, "%s Log: 0x%llx\n", 633 reg_desc->msg, CSR_XR(csr_base, reg_desc->log_addr)); 634 } 635 } 636 637 void 638 px_err_reg_disable(px_t *px_p, px_err_id_t id) 639 { 640 px_err_reg_desc_t *reg_desc = &px_err_reg_tbl[id]; 641 caddr_t csr_base; 642 643 if (id == PX_ERR_JBC) 644 csr_base = (caddr_t)px_p->px_inos[PX_INTR_XBC]; 645 else 646 csr_base = (caddr_t)px_p->px_inos[PX_INTR_PEC]; 647 648 reg_desc->enabled = B_FALSE; 649 650 switch (id) { 651 case PX_ERR_JBC: 652 case PX_ERR_MMU: 653 case PX_ERR_IMU: 654 case PX_ERR_TLU_UE: 655 case PX_ERR_TLU_CE: 656 case PX_ERR_TLU_OE: 657 case PX_ERR_ILU: 658 if (reg_desc->log_addr != NULL) { 659 CSR_XS(csr_base, reg_desc->log_addr, 0); 660 } 661 CSR_XS(csr_base, reg_desc->enable_addr, 0); 662 break; 663 case PX_ERR_LPU_LINK: 664 case PX_ERR_LPU_PHY: 665 case PX_ERR_LPU_RX: 666 case PX_ERR_LPU_TX: 667 case PX_ERR_LPU_LTSSM: 668 case PX_ERR_LPU_GIGABLZ: 669 if (reg_desc->log_addr != NULL) { 670 CSR_XS(csr_base, reg_desc->log_addr, -1); 671 } 672 CSR_XS(csr_base, reg_desc->enable_addr, -1); 673 break; 674 } 675 } 676 677 /* 678 * px_err_handle: 679 * Common function called by trap, mondo and fabric intr. 680 * o Snap shot current fire registers 681 * o check for safe access 682 * o send ereport and clear snap shot registers 683 * o check severity of snap shot registers 684 * 685 * @param px_p leaf in which to check access 686 * @param derr fm err data structure to be updated 687 * @param caller PX_TRAP_CALL | PX_INTR_CALL 688 * @param chkjbc whether to handle jbc registers 689 * @return err PX_OK | PX_NONFATAL | 690 * PX_FATAL_GOS | PX_FATAL_HW | PX_STUCK_FATAL 691 */ 692 int 693 px_err_handle(px_t *px_p, ddi_fm_error_t *derr, int caller, 694 boolean_t chkjbc) 695 { 696 px_cb_t *cb_p = px_p->px_cb_p; /* for fm_mutex */ 697 px_err_ss_t ss; 698 int err = PX_OK; 699 700 ASSERT(MUTEX_HELD(&cb_p->xbc_fm_mutex)); 701 702 /* snap shot the current fire registers */ 703 px_err_snapshot(px_p, &ss, chkjbc); 704 705 /* check for safe access */ 706 px_err_safeacc_check(px_p, derr); 707 708 /* send ereports/handle/clear registers */ 709 err = px_err_erpt_and_clr(px_p, derr, &ss); 710 711 /* check for error severity */ 712 err = px_err_check_severity(px_p, derr, err, caller); 713 714 /* Mark the On Trap Handle if an error occured */ 715 if (err != PX_OK) { 716 px_pec_t *pec_p = px_p->px_pec_p; 717 on_trap_data_t *otd = pec_p->pec_ontrap_data; 718 719 if ((otd != NULL) && (otd->ot_prot & OT_DATA_ACCESS)) 720 otd->ot_trap |= OT_DATA_ACCESS; 721 } 722 723 return (err); 724 } 725 726 /* 727 * Static function 728 */ 729 730 /* 731 * px_err_snapshot: 732 * Take a current snap shot of all the fire error registers. This includes 733 * JBC, DMC, and PEC, unless chkjbc == false; 734 * 735 * @param px_p leaf in which to take the snap shot. 736 * @param ss pre-allocated memory to store the snap shot. 737 * @param chkjbc boolean on whether to store jbc register. 738 */ 739 static void 740 px_err_snapshot(px_t *px_p, px_err_ss_t *ss, boolean_t chkjbc) 741 { 742 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 743 caddr_t xbc_csr_base = (caddr_t)pxu_p->px_address[PX_REG_XBC]; 744 caddr_t pec_csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 745 px_err_reg_desc_t *reg_desc; 746 int reg_id; 747 748 /* snapshot JBC interrupt status */ 749 reg_id = PX_ERR_JBC; 750 if (chkjbc == B_TRUE) { 751 reg_desc = &px_err_reg_tbl[reg_id]; 752 ss->err_status[reg_id] = CSR_XR(xbc_csr_base, 753 reg_desc->status_addr); 754 } else { 755 ss->err_status[reg_id] = 0; 756 } 757 758 /* snapshot DMC/PEC interrupt status */ 759 for (reg_id = 1; reg_id < PX_ERR_REG_KEYS; reg_id += 1) { 760 reg_desc = &px_err_reg_tbl[reg_id]; 761 ss->err_status[reg_id] = CSR_XR(pec_csr_base, 762 reg_desc->status_addr); 763 } 764 } 765 766 /* 767 * px_err_erpt_and_clr: 768 * This function does the following thing to all the fire registers based 769 * on an earlier snap shot. 770 * o Send ereport 771 * o Handle the error 772 * o Clear the error 773 * 774 * @param px_p leaf in which to take the snap shot. 775 * @param derr fm err in which the ereport is to be based on 776 * @param ss pre-allocated memory to store the snap shot. 777 */ 778 static int 779 px_err_erpt_and_clr(px_t *px_p, ddi_fm_error_t *derr, px_err_ss_t *ss) 780 { 781 dev_info_t *rpdip = px_p->px_dip; 782 px_cb_t *cb_p = px_p->px_cb_p; /* for fm_mutex */ 783 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 784 caddr_t csr_base; 785 px_err_reg_desc_t *err_reg_tbl; 786 px_err_bit_desc_t *err_bit_tbl; 787 px_err_bit_desc_t *err_bit_desc; 788 789 uint64_t *log_mask, *count_mask; 790 uint64_t status_addr, clear_addr; 791 uint64_t ss_reg; 792 793 int (*err_handler)(); 794 int (*erpt_handler)(); 795 int reg_id, key; 796 int err = PX_OK; 797 798 ASSERT(MUTEX_HELD(&cb_p->xbc_fm_mutex)); 799 800 /* send erport/handle/clear JBC errors */ 801 for (reg_id = 0; reg_id < PX_ERR_REG_KEYS; reg_id += 1) { 802 /* Get the correct register description table */ 803 err_reg_tbl = &px_err_reg_tbl[reg_id]; 804 805 /* Get the correct CSR BASE */ 806 if (reg_id == PX_ERR_JBC) { 807 csr_base = (caddr_t)pxu_p->px_address[PX_REG_XBC]; 808 } else { 809 csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 810 } 811 812 /* Get pointers to masks and register addresses */ 813 log_mask = err_reg_tbl->log_mask_p; 814 count_mask = err_reg_tbl->count_mask_p; 815 status_addr = err_reg_tbl->status_addr; 816 clear_addr = err_reg_tbl->clear_addr; 817 ss_reg = ss->err_status[reg_id]; 818 819 /* Get the register BIT description table */ 820 err_bit_tbl = err_reg_tbl->err_bit_tbl; 821 822 /* For each known bit in the register send erpt and handle */ 823 for (key = 0; key < err_reg_tbl->err_bit_keys; key += 1) { 824 /* Get the bit description table for this register */ 825 err_bit_desc = &err_bit_tbl[key]; 826 827 /* 828 * If the ss_reg is set for this bit, 829 * send ereport and handle 830 */ 831 if (BIT_TST(ss_reg, err_bit_desc->bit)) { 832 /* Increment the counter if necessary */ 833 if (BIT_TST(*count_mask, err_bit_desc->bit)) { 834 err_bit_desc->counter++; 835 } 836 837 /* Error Handle for this bit */ 838 err_handler = err_bit_desc->err_handler; 839 if (err_handler) 840 err |= err_handler(rpdip, 841 csr_base, 842 derr, 843 err_reg_tbl, 844 err_bit_desc); 845 846 /* Send the ereport if it's an UNEXPECTED err */ 847 erpt_handler = err_bit_desc->erpt_handler; 848 if (derr->fme_flag == DDI_FM_ERR_UNEXPECTED) { 849 if (erpt_handler) 850 (void) erpt_handler(rpdip, 851 csr_base, 852 ss_reg, 853 derr, 854 err_bit_desc->class_name); 855 } 856 } 857 858 } 859 860 /* Print register status */ 861 if (ss_reg & *log_mask) 862 DBG(DBG_ERR_INTR, rpdip, "<%x>=%16llx %s\n", 863 status_addr, ss_reg, err_reg_tbl->msg); 864 865 /* Clear the register and error */ 866 CSR_XS(csr_base, clear_addr, ss_reg); 867 } 868 869 return (err); 870 } 871 872 /* 873 * px_err_check_severity: 874 * Check the severity of the fire error based on an earlier snapshot 875 * 876 * @param px_p leaf in which to take the snap shot. 877 * @param derr fm err in which the ereport is to be based on 878 * @param ss pre-allocated memory to store the snap shot. 879 */ 880 static int 881 px_err_check_severity(px_t *px_p, ddi_fm_error_t *derr, int err, int caller) 882 { 883 px_pec_t *pec_p = px_p->px_pec_p; 884 boolean_t is_safeacc = B_FALSE; 885 886 /* nothing to do if called with no error */ 887 if (err == PX_OK) 888 return (err); 889 890 /* Cautious access error handling */ 891 switch (derr->fme_flag) { 892 case DDI_FM_ERR_EXPECTED: 893 if (caller == PX_TRAP_CALL) { 894 /* 895 * for ddi_caut_get treat all events as nonfatal 896 * The trampoline will set err_ena = 0, 897 * err_status = NONFATAL. 898 */ 899 derr->fme_status = DDI_FM_NONFATAL; 900 is_safeacc = B_TRUE; 901 } else { 902 /* 903 * For ddi_caut_put treat all events as nonfatal. Here 904 * we have the handle and can call ndi_fm_acc_err_set(). 905 */ 906 derr->fme_status = DDI_FM_NONFATAL; 907 ndi_fm_acc_err_set(pec_p->pec_acc_hdl, derr); 908 is_safeacc = B_TRUE; 909 } 910 break; 911 case DDI_FM_ERR_PEEK: 912 case DDI_FM_ERR_POKE: 913 /* 914 * For ddi_peek/poke treat all events as nonfatal. 915 */ 916 is_safeacc = B_TRUE; 917 break; 918 default: 919 is_safeacc = B_FALSE; 920 } 921 922 /* 923 * The third argument "err" is passed in as error status from checking 924 * Fire register, re-adjust error status from safe access. 925 */ 926 if (is_safeacc && !(err & PX_FATAL_GOS)) 927 return (PX_NONFATAL); 928 929 return (err); 930 } 931 932 /* predefined convenience functions */ 933 /* ARGSUSED */ 934 int 935 px_err_fatal_hw_handle(dev_info_t *rpdip, caddr_t csr_base, 936 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 937 px_err_bit_desc_t *err_bit_descr) 938 { 939 return (PX_FATAL_HW); 940 } 941 942 /* ARGSUSED */ 943 int 944 px_err_fatal_gos_handle(dev_info_t *rpdip, caddr_t csr_base, 945 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 946 px_err_bit_desc_t *err_bit_descr) 947 { 948 return (PX_FATAL_GOS); 949 } 950 951 /* ARGSUSED */ 952 int 953 px_err_fatal_stuck_handle(dev_info_t *rpdip, caddr_t csr_base, 954 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 955 px_err_bit_desc_t *err_bit_descr) 956 { 957 return (PX_STUCK_FATAL); 958 } 959 960 /* ARGSUSED */ 961 int 962 px_err_fatal_sw_handle(dev_info_t *rpdip, caddr_t csr_base, 963 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 964 px_err_bit_desc_t *err_bit_descr) 965 { 966 return (PX_FATAL_SW); 967 } 968 969 /* ARGSUSED */ 970 int 971 px_err_non_fatal_handle(dev_info_t *rpdip, caddr_t csr_base, 972 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 973 px_err_bit_desc_t *err_bit_descr) 974 { 975 return (PX_NONFATAL); 976 } 977 978 /* ARGSUSED */ 979 int 980 px_err_ok_handle(dev_info_t *rpdip, caddr_t csr_base, ddi_fm_error_t *derr, 981 px_err_reg_desc_t *err_reg_descr, px_err_bit_desc_t *err_bit_descr) 982 { 983 return (PX_OK); 984 } 985 986 /* ARGSUSED */ 987 int 988 px_err_unknown_handle(dev_info_t *rpdip, caddr_t csr_base, ddi_fm_error_t *derr, 989 px_err_reg_desc_t *err_reg_descr, px_err_bit_desc_t *err_bit_descr) 990 { 991 return (PX_ERR_UNKNOWN); 992 } 993 994 /* ARGSUSED */ 995 PX_ERPT_SEND_DEC(do_not) 996 { 997 return (PX_OK); 998 } 999 1000 1001 /* JBC FATAL - see io erpt doc, section 1.1 */ 1002 PX_ERPT_SEND_DEC(jbc_fatal) 1003 { 1004 char buf[FM_MAX_CLASS]; 1005 1006 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1007 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1008 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1009 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1010 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1011 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1012 FIRE_JBC_IE, DATA_TYPE_UINT64, 1013 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1014 FIRE_JBC_IS, DATA_TYPE_UINT64, 1015 ss_reg, 1016 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1017 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1018 FIRE_JBC_FEL1, DATA_TYPE_UINT64, 1019 CSR_XR(csr_base, FATAL_ERROR_LOG_1), 1020 FIRE_JBC_FEL2, DATA_TYPE_UINT64, 1021 CSR_XR(csr_base, FATAL_ERROR_LOG_2), 1022 NULL); 1023 1024 return (PX_OK); 1025 } 1026 1027 /* JBC MERGE - see io erpt doc, section 1.2 */ 1028 PX_ERPT_SEND_DEC(jbc_merge) 1029 { 1030 char buf[FM_MAX_CLASS]; 1031 1032 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1033 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1034 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1035 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1036 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1037 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1038 FIRE_JBC_IE, DATA_TYPE_UINT64, 1039 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1040 FIRE_JBC_IS, DATA_TYPE_UINT64, 1041 ss_reg, 1042 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1043 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1044 FIRE_JBC_MTEL, DATA_TYPE_UINT64, 1045 CSR_XR(csr_base, MERGE_TRANSACTION_ERROR_LOG), 1046 NULL); 1047 1048 return (PX_OK); 1049 } 1050 1051 /* 1052 * JBC Merge buffer nonfatal errors: 1053 * Merge buffer parity error (rd_buf): dma:read:M:nonfatal 1054 * Merge buffer parity error (wr_buf): dma:write:M:nonfatal 1055 */ 1056 /* ARGSUSED */ 1057 int 1058 px_err_jbc_merge_handle(dev_info_t *rpdip, caddr_t csr_base, 1059 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1060 px_err_bit_desc_t *err_bit_descr) 1061 { 1062 uint64_t paddr; 1063 int ret; 1064 1065 paddr = CSR_XR(csr_base, MERGE_TRANSACTION_ERROR_LOG); 1066 paddr &= MERGE_TRANSACTION_ERROR_LOG_ADDRESS_MASK; 1067 1068 ret = px_handle_lookup( 1069 rpdip, DMA_HANDLE, derr->fme_ena, (void *)paddr); 1070 1071 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1072 } 1073 1074 /* JBC Jbusint IN - see io erpt doc, section 1.3 */ 1075 PX_ERPT_SEND_DEC(jbc_in) 1076 { 1077 char buf[FM_MAX_CLASS]; 1078 1079 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1080 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1081 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1082 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1083 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1084 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1085 FIRE_JBC_IE, DATA_TYPE_UINT64, 1086 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1087 FIRE_JBC_IS, DATA_TYPE_UINT64, 1088 ss_reg, 1089 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1090 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1091 FIRE_JBC_JITEL1, DATA_TYPE_UINT64, 1092 CSR_XR(csr_base, JBCINT_IN_TRANSACTION_ERROR_LOG), 1093 FIRE_JBC_JITEL2, DATA_TYPE_UINT64, 1094 CSR_XR(csr_base, JBCINT_IN_TRANSACTION_ERROR_LOG_2), 1095 NULL); 1096 1097 return (PX_OK); 1098 } 1099 1100 /* 1101 * JBC Jbusint IN nonfatal errors: PA logged in Jbusint In Transaction Error 1102 * Log Reg[42:0]. 1103 * CE async fault error: nonfatal 1104 * Jbus bus error: dma::nonfatal 1105 * Jbus unmapped error: pio|dma:rdwr:M:nonfatal 1106 * Write data parity error: pio/write:M:nonfatal 1107 * Read data parity error: pio/read:M:nonfatal 1108 * Illegal NCWR bytemask: pio:write:M:nonfatal 1109 * Illegal NCRD bytemask: pio:write:M:nonfatal 1110 * Invalid jbus transaction: nonfatal 1111 */ 1112 /* ARGSUSED */ 1113 int 1114 px_err_jbc_jbusint_in_handle(dev_info_t *rpdip, caddr_t csr_base, 1115 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1116 px_err_bit_desc_t *err_bit_descr) 1117 { 1118 uint64_t paddr; 1119 int ret; 1120 1121 paddr = CSR_XR(csr_base, JBCINT_IN_TRANSACTION_ERROR_LOG); 1122 paddr &= JBCINT_IN_TRANSACTION_ERROR_LOG_ADDRESS_MASK; 1123 1124 ret = px_handle_lookup( 1125 rpdip, DMA_HANDLE, derr->fme_ena, (void *)paddr); 1126 1127 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1128 } 1129 1130 1131 /* JBC Jbusint Out - see io erpt doc, section 1.4 */ 1132 PX_ERPT_SEND_DEC(jbc_out) 1133 { 1134 char buf[FM_MAX_CLASS]; 1135 1136 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1137 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1138 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1139 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1140 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1141 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1142 FIRE_JBC_IE, DATA_TYPE_UINT64, 1143 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1144 FIRE_JBC_IS, DATA_TYPE_UINT64, 1145 ss_reg, 1146 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1147 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1148 FIRE_JBC_JOTEL1, DATA_TYPE_UINT64, 1149 CSR_XR(csr_base, JBCINT_OUT_TRANSACTION_ERROR_LOG), 1150 FIRE_JBC_JOTEL2, DATA_TYPE_UINT64, 1151 CSR_XR(csr_base, JBCINT_OUT_TRANSACTION_ERROR_LOG_2), 1152 NULL); 1153 1154 return (PX_OK); 1155 } 1156 1157 /* JBC Dmcint ODCD - see io erpt doc, section 1.5 */ 1158 PX_ERPT_SEND_DEC(jbc_odcd) 1159 { 1160 char buf[FM_MAX_CLASS]; 1161 1162 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1163 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1164 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1165 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1166 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1167 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1168 FIRE_JBC_IE, DATA_TYPE_UINT64, 1169 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1170 FIRE_JBC_IS, DATA_TYPE_UINT64, 1171 ss_reg, 1172 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1173 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1174 FIRE_JBC_DMC_ODCD, DATA_TYPE_UINT64, 1175 CSR_XR(csr_base, DMCINT_ODCD_ERROR_LOG), 1176 NULL); 1177 1178 return (PX_OK); 1179 } 1180 1181 /* 1182 * JBC Dmcint ODCO nonfatal errer handling - 1183 * Unmapped PIO read error: pio:read:M:nonfatal 1184 * Unmapped PIO write error: pio:write:M:nonfatal 1185 * PIO data parity error: pio:write:M:nonfatal 1186 * Invalid PIO write to PCIe cfg/io, csr, ebus or i2c bus: pio:write:nonfatal 1187 * Invalid PIO read to PCIe cfg/io, csr, ebus or i2c bus: pio:read:nonfatal 1188 */ 1189 /* ARGSUSED */ 1190 int 1191 px_err_jbc_dmcint_odcd_handle(dev_info_t *rpdip, caddr_t csr_base, 1192 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1193 px_err_bit_desc_t *err_bit_descr) 1194 { 1195 uint64_t paddr; 1196 int ret; 1197 1198 paddr = CSR_XR(csr_base, DMCINT_ODCD_ERROR_LOG); 1199 paddr &= DMCINT_ODCD_ERROR_LOG_ADDRESS_MASK; 1200 1201 ret = px_handle_lookup( 1202 rpdip, DMA_HANDLE, derr->fme_ena, (void *)paddr); 1203 1204 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1205 } 1206 1207 /* JBC Dmcint IDC - see io erpt doc, section 1.6 */ 1208 PX_ERPT_SEND_DEC(jbc_idc) 1209 { 1210 char buf[FM_MAX_CLASS]; 1211 1212 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1213 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1214 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1215 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1216 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1217 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1218 FIRE_JBC_IE, DATA_TYPE_UINT64, 1219 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1220 FIRE_JBC_IS, DATA_TYPE_UINT64, 1221 ss_reg, 1222 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1223 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1224 FIRE_JBC_DMC_IDC, DATA_TYPE_UINT64, 1225 CSR_XR(csr_base, DMCINT_IDC_ERROR_LOG), 1226 NULL); 1227 1228 return (PX_OK); 1229 } 1230 1231 /* JBC CSR - see io erpt doc, section 1.7 */ 1232 PX_ERPT_SEND_DEC(jbc_csr) 1233 { 1234 char buf[FM_MAX_CLASS]; 1235 1236 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1237 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1238 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1239 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1240 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1241 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1242 FIRE_JBC_IE, DATA_TYPE_UINT64, 1243 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1244 FIRE_JBC_IS, DATA_TYPE_UINT64, 1245 ss_reg, 1246 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1247 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1248 "jbc-error-reg", DATA_TYPE_UINT64, 1249 CSR_XR(csr_base, CSR_ERROR_LOG), 1250 NULL); 1251 1252 return (PX_OK); 1253 } 1254 1255 /* 1256 * JBC CSR errer handling - 1257 * Ebus ready timeout error: pio:rdwr:M:nonfatal 1258 */ 1259 /* ARGSUSED */ 1260 int 1261 px_err_jbc_csr_handle(dev_info_t *rpdip, caddr_t csr_base, 1262 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1263 px_err_bit_desc_t *err_bit_descr) 1264 { 1265 uint64_t paddr; 1266 int ret; 1267 1268 paddr = CSR_XR(csr_base, CSR_ERROR_LOG); 1269 paddr &= CSR_ERROR_LOG_ADDRESS_MASK; 1270 1271 ret = px_handle_lookup( 1272 rpdip, DMA_HANDLE, derr->fme_ena, (void *)paddr); 1273 1274 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1275 } 1276 1277 /* JBC Dmcint IDC - see io erpt doc, section 1.6 */ 1278 1279 /* DMC IMU RDS - see io erpt doc, section 2.1 */ 1280 PX_ERPT_SEND_DEC(imu_rds) 1281 { 1282 char buf[FM_MAX_CLASS]; 1283 1284 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1285 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1286 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1287 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1288 FIRE_IMU_ELE, DATA_TYPE_UINT64, 1289 CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE), 1290 FIRE_IMU_IE, DATA_TYPE_UINT64, 1291 CSR_XR(csr_base, IMU_INTERRUPT_ENABLE), 1292 FIRE_IMU_IS, DATA_TYPE_UINT64, 1293 ss_reg, 1294 FIRE_IMU_ESS, DATA_TYPE_UINT64, 1295 CSR_XR(csr_base, IMU_ERROR_STATUS_SET), 1296 FIRE_IMU_RDS, DATA_TYPE_UINT64, 1297 CSR_XR(csr_base, IMU_RDS_ERROR_LOG), 1298 NULL); 1299 1300 return (PX_OK); 1301 } 1302 1303 /* imu function to handle all Received but Not Enabled errors */ 1304 /* ARGSUSED */ 1305 int 1306 px_err_imu_rbne_handle(dev_info_t *rpdip, caddr_t csr_base, 1307 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1308 px_err_bit_desc_t *err_bit_descr) 1309 { 1310 uint64_t imu_log_enable, imu_intr_enable; 1311 int mask = BITMASK(err_bit_descr->bit); 1312 int err = PX_NONFATAL; 1313 1314 imu_log_enable = CSR_XR(csr_base, err_reg_descr->log_addr); 1315 imu_intr_enable = CSR_XR(csr_base, err_reg_descr->enable_addr); 1316 1317 /* 1318 * If matching bit is not set, meaning corresponding rbne not 1319 * enabled, then receiving it indicates some sort of malfunction 1320 * possibly in hardware. 1321 * 1322 * Other wise, software may have intentionally disabled certain 1323 * errors for a period of time within which the occuring of the 1324 * disabled errors become rbne, that is non fatal. 1325 */ 1326 if (!(imu_log_enable & imu_intr_enable & mask)) 1327 err = PX_FATAL_SW; 1328 1329 return (err); 1330 } 1331 1332 /* 1333 * No platforms uses PME. Any PME received is simply logged 1334 * for analysis. 1335 */ 1336 /* ARGSUSED */ 1337 int 1338 px_err_imu_pme_handle(dev_info_t *rpdip, caddr_t csr_base, 1339 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1340 px_err_bit_desc_t *err_bit_descr) 1341 { 1342 px_t *px_p = DIP_TO_STATE(rpdip); 1343 1344 px_p->px_pme_ignored++; 1345 return (PX_NONFATAL); 1346 } 1347 1348 /* handle EQ overflow */ 1349 /* ARGSUSED */ 1350 int 1351 px_err_imu_eq_ovfl_handle(dev_info_t *rpdip, caddr_t csr_base, 1352 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1353 px_err_bit_desc_t *err_bit_descr) 1354 { 1355 px_t *px_p = DIP_TO_STATE(rpdip); 1356 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 1357 msiqid_t eqno; 1358 pci_msiq_state_t msiq_state; 1359 int err = PX_NONFATAL; 1360 int i; 1361 1362 eqno = msiq_state_p->msiq_1st_msiq_id; 1363 for (i = 0; i < msiq_state_p->msiq_cnt; i++) { 1364 if (px_lib_msiq_getstate(rpdip, eqno, &msiq_state) == 1365 DDI_SUCCESS) { 1366 if (msiq_state == PCI_MSIQ_STATE_ERROR) { 1367 err = PX_FATAL_SW; 1368 } 1369 } 1370 } 1371 1372 return (err); 1373 } 1374 1375 /* DMC IMU SCS - see io erpt doc, section 2.2 */ 1376 PX_ERPT_SEND_DEC(imu_scs) 1377 { 1378 char buf[FM_MAX_CLASS]; 1379 1380 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1381 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1382 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1383 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1384 FIRE_IMU_ELE, DATA_TYPE_UINT64, 1385 CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE), 1386 FIRE_IMU_IE, DATA_TYPE_UINT64, 1387 CSR_XR(csr_base, IMU_INTERRUPT_ENABLE), 1388 FIRE_IMU_IS, DATA_TYPE_UINT64, 1389 ss_reg, 1390 FIRE_IMU_ESS, DATA_TYPE_UINT64, 1391 CSR_XR(csr_base, IMU_ERROR_STATUS_SET), 1392 FIRE_IMU_SCS, DATA_TYPE_UINT64, 1393 CSR_XR(csr_base, IMU_SCS_ERROR_LOG), 1394 NULL); 1395 1396 return (PX_OK); 1397 } 1398 1399 /* DMC IMU - see io erpt doc, section 2.3 */ 1400 PX_ERPT_SEND_DEC(imu) 1401 { 1402 char buf[FM_MAX_CLASS]; 1403 1404 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1405 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1406 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1407 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1408 FIRE_IMU_ELE, DATA_TYPE_UINT64, 1409 CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE), 1410 FIRE_IMU_IE, DATA_TYPE_UINT64, 1411 CSR_XR(csr_base, IMU_INTERRUPT_ENABLE), 1412 FIRE_IMU_IS, DATA_TYPE_UINT64, 1413 ss_reg, 1414 FIRE_IMU_ESS, DATA_TYPE_UINT64, 1415 CSR_XR(csr_base, IMU_ERROR_STATUS_SET), 1416 NULL); 1417 1418 return (PX_OK); 1419 } 1420 1421 /* DMC MMU TFAR/TFSR - see io erpt doc, section 2.4 */ 1422 PX_ERPT_SEND_DEC(mmu_tfar_tfsr) 1423 { 1424 char buf[FM_MAX_CLASS]; 1425 1426 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1427 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1428 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1429 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1430 FIRE_MMU_ELE, DATA_TYPE_UINT64, 1431 CSR_XR(csr_base, MMU_ERROR_LOG_ENABLE), 1432 FIRE_MMU_IE, DATA_TYPE_UINT64, 1433 CSR_XR(csr_base, MMU_INTERRUPT_ENABLE), 1434 FIRE_MMU_IS, DATA_TYPE_UINT64, 1435 ss_reg, 1436 FIRE_MMU_ESS, DATA_TYPE_UINT64, 1437 CSR_XR(csr_base, MMU_ERROR_STATUS_SET), 1438 FIRE_MMU_TFAR, DATA_TYPE_UINT64, 1439 CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS), 1440 FIRE_MMU_TFSR, DATA_TYPE_UINT64, 1441 CSR_XR(csr_base, MMU_TRANSLATION_FAULT_STATUS), 1442 NULL); 1443 1444 return (PX_OK); 1445 } 1446 1447 /* DMC MMU - see io erpt doc, section 2.5 */ 1448 PX_ERPT_SEND_DEC(mmu) 1449 { 1450 char buf[FM_MAX_CLASS]; 1451 1452 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1453 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1454 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1455 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1456 FIRE_MMU_ELE, DATA_TYPE_UINT64, 1457 CSR_XR(csr_base, MMU_ERROR_LOG_ENABLE), 1458 FIRE_MMU_IE, DATA_TYPE_UINT64, 1459 CSR_XR(csr_base, MMU_INTERRUPT_ENABLE), 1460 FIRE_MMU_IS, DATA_TYPE_UINT64, 1461 ss_reg, 1462 FIRE_MMU_ESS, DATA_TYPE_UINT64, 1463 CSR_XR(csr_base, MMU_ERROR_STATUS_SET), 1464 NULL); 1465 1466 return (PX_OK); 1467 } 1468 1469 /* imu function to handle all Received but Not Enabled errors */ 1470 int 1471 px_err_mmu_rbne_handle(dev_info_t *rpdip, caddr_t csr_base, 1472 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1473 px_err_bit_desc_t *err_bit_descr) 1474 { 1475 uint64_t mmu_log_enable, mmu_intr_enable; 1476 uint64_t mask = BITMASK(err_bit_descr->bit); 1477 uint64_t mmu_tfa, mmu_ctrl; 1478 uint64_t mmu_enable_bit = 0; 1479 int err = PX_NONFATAL; 1480 int ret; 1481 1482 mmu_log_enable = CSR_XR(csr_base, err_reg_descr->log_addr); 1483 mmu_intr_enable = CSR_XR(csr_base, err_reg_descr->enable_addr); 1484 1485 mmu_tfa = CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS); 1486 mmu_ctrl = CSR_XR(csr_base, MMU_CONTROL_AND_STATUS); 1487 1488 switch (err_bit_descr->bit) { 1489 case MMU_INTERRUPT_STATUS_BYP_ERR_P: 1490 mmu_enable_bit = BITMASK(MMU_CONTROL_AND_STATUS_BE); 1491 break; 1492 case MMU_INTERRUPT_STATUS_TRN_ERR_P: 1493 mmu_enable_bit = BITMASK(MMU_CONTROL_AND_STATUS_TE); 1494 break; 1495 default: 1496 mmu_enable_bit = 0; 1497 break; 1498 } 1499 1500 /* 1501 * If the interrupts are enabled and Translation/Bypass Enable bit 1502 * was set, then panic. This error should not have occured. 1503 */ 1504 if (mmu_log_enable & mmu_intr_enable & 1505 (mmu_ctrl & mmu_enable_bit)) { 1506 err = PX_FATAL_SW; 1507 } else { 1508 ret = px_handle_lookup( 1509 rpdip, DMA_HANDLE, derr->fme_ena, (void *)mmu_tfa); 1510 err = (ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL; 1511 1512 /* 1513 * S/W bug - this error should always be enabled 1514 */ 1515 1516 /* enable error & intr reporting for this bit */ 1517 CSR_XS(csr_base, MMU_ERROR_LOG_ENABLE, mmu_log_enable | mask); 1518 CSR_XS(csr_base, MMU_INTERRUPT_ENABLE, mmu_intr_enable | mask); 1519 1520 /* enable translation access/bypass enable */ 1521 CSR_XS(csr_base, MMU_CONTROL_AND_STATUS, 1522 mmu_ctrl | mmu_enable_bit); 1523 } 1524 1525 return (err); 1526 } 1527 1528 /* Generic error handling functions that involve MMU Translation Fault Addr */ 1529 /* ARGSUSED */ 1530 int 1531 px_err_mmu_tfa_handle(dev_info_t *rpdip, caddr_t csr_base, 1532 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1533 px_err_bit_desc_t *err_bit_descr) 1534 { 1535 uint64_t mmu_tfa; 1536 uint_t ret; 1537 1538 mmu_tfa = CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS); 1539 ret = px_handle_lookup( 1540 rpdip, DMA_HANDLE, derr->fme_ena, (void *)mmu_tfa); 1541 1542 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1543 } 1544 1545 /* MMU Table walk errors */ 1546 /* ARGSUSED */ 1547 int 1548 px_err_mmu_tblwlk_handle(dev_info_t *rpdip, caddr_t csr_base, 1549 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1550 px_err_bit_desc_t *err_bit_descr) 1551 { 1552 uint64_t mmu_tfa; 1553 uint_t ret; 1554 1555 mmu_tfa = CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS); 1556 ret = px_handle_lookup( 1557 rpdip, DMA_HANDLE, derr->fme_ena, (void *)mmu_tfa); 1558 1559 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1560 } 1561 1562 /* 1563 * TLU LUP event - power management code is interested in this event. 1564 */ 1565 /* ARGSUSED */ 1566 int 1567 px_err_tlu_lup_handle(dev_info_t *rpdip, caddr_t csr_base, 1568 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1569 px_err_bit_desc_t *err_bit_descr) 1570 { 1571 px_t *px_p = DIP_TO_STATE(rpdip); 1572 1573 /* 1574 * Existense of pm info indicates the power management 1575 * is interested in this event. 1576 */ 1577 if (!PCIE_PMINFO(rpdip) || !PCIE_NEXUS_PMINFO(rpdip)) 1578 return (PX_OK); 1579 1580 mutex_enter(&px_p->px_lup_lock); 1581 px_p->px_lupsoft_pending++; 1582 mutex_exit(&px_p->px_lup_lock); 1583 1584 /* 1585 * Post a soft interrupt to wake up threads waiting for this. 1586 */ 1587 ddi_trigger_softintr(px_p->px_lupsoft_id); 1588 1589 return (PX_OK); 1590 } 1591 1592 /* PEC ILU none - see io erpt doc, section 3.1 */ 1593 PX_ERPT_SEND_DEC(pec_ilu) 1594 { 1595 char buf[FM_MAX_CLASS]; 1596 1597 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1598 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1599 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1600 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1601 FIRE_ILU_ELE, DATA_TYPE_UINT64, 1602 CSR_XR(csr_base, ILU_ERROR_LOG_ENABLE), 1603 FIRE_ILU_IE, DATA_TYPE_UINT64, 1604 CSR_XR(csr_base, ILU_INTERRUPT_ENABLE), 1605 FIRE_ILU_IS, DATA_TYPE_UINT64, 1606 ss_reg, 1607 FIRE_ILU_ESS, DATA_TYPE_UINT64, 1608 CSR_XR(csr_base, ILU_ERROR_STATUS_SET), 1609 NULL); 1610 1611 return (PX_OK); 1612 } 1613 1614 /* PCIEX UE Errors */ 1615 /* ARGSUSED */ 1616 px_err_pciex_ue_handle(dev_info_t *rpdip, caddr_t csr_base, 1617 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1618 px_err_bit_desc_t *err_bit_descr) 1619 { 1620 uint32_t mask = (uint32_t)BITMASK(err_bit_descr->bit); 1621 1622 return ((err_bit_descr->bit >= 32 && px_fabric_die_rc_ue_gos) ? 1623 PX_FATAL_GOS : PX_FABRIC_ERR_SEV(mask, px_fabric_die_rc_ue, 1624 px_fabric_die_rc_ue_gos)); 1625 } 1626 1627 /* PCI-E Uncorrectable Errors - see io erpt doc, section 3.2 */ 1628 PX_ERPT_SEND_DEC(pciex_rx_ue) 1629 { 1630 char buf[FM_MAX_CLASS]; 1631 1632 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1633 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1634 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1635 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1636 FIRE_TLU_UELE, DATA_TYPE_UINT64, 1637 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE), 1638 FIRE_TLU_UIE, DATA_TYPE_UINT64, 1639 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE), 1640 FIRE_TLU_UIS, DATA_TYPE_UINT64, 1641 ss_reg, 1642 FIRE_TLU_UESS, DATA_TYPE_UINT64, 1643 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_SET), 1644 FIRE_TLU_RUEH1L, DATA_TYPE_UINT64, 1645 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER1_LOG), 1646 FIRE_TLU_RUEH2L, DATA_TYPE_UINT64, 1647 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER2_LOG), 1648 NULL); 1649 1650 return (PX_OK); 1651 } 1652 1653 /* PCI-E Uncorrectable Errors - see io erpt doc, section 3.3 */ 1654 PX_ERPT_SEND_DEC(pciex_tx_ue) 1655 { 1656 char buf[FM_MAX_CLASS]; 1657 1658 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1659 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1660 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1661 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1662 FIRE_TLU_UELE, DATA_TYPE_UINT64, 1663 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE), 1664 FIRE_TLU_UIE, DATA_TYPE_UINT64, 1665 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE), 1666 FIRE_TLU_UIS, DATA_TYPE_UINT64, 1667 ss_reg, 1668 FIRE_TLU_UESS, DATA_TYPE_UINT64, 1669 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_SET), 1670 FIRE_TLU_TUEH1L, DATA_TYPE_UINT64, 1671 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER1_LOG), 1672 FIRE_TLU_TUEH2L, DATA_TYPE_UINT64, 1673 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER2_LOG), 1674 NULL); 1675 1676 return (PX_OK); 1677 } 1678 1679 /* PCI-E Uncorrectable Errors - see io erpt doc, section 3.4 */ 1680 PX_ERPT_SEND_DEC(pciex_rx_tx_ue) 1681 { 1682 char buf[FM_MAX_CLASS]; 1683 1684 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1685 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1686 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1687 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1688 FIRE_TLU_UELE, DATA_TYPE_UINT64, 1689 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE), 1690 FIRE_TLU_UIE, DATA_TYPE_UINT64, 1691 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE), 1692 FIRE_TLU_UIS, DATA_TYPE_UINT64, 1693 ss_reg, 1694 FIRE_TLU_UESS, DATA_TYPE_UINT64, 1695 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_SET), 1696 FIRE_TLU_RUEH1L, DATA_TYPE_UINT64, 1697 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER1_LOG), 1698 FIRE_TLU_RUEH2L, DATA_TYPE_UINT64, 1699 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER2_LOG), 1700 FIRE_TLU_TUEH1L, DATA_TYPE_UINT64, 1701 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER1_LOG), 1702 FIRE_TLU_TUEH2L, DATA_TYPE_UINT64, 1703 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER2_LOG), 1704 NULL); 1705 1706 return (PX_OK); 1707 } 1708 1709 /* PCI-E Uncorrectable Errors - see io erpt doc, section 3.5 */ 1710 PX_ERPT_SEND_DEC(pciex_ue) 1711 { 1712 char buf[FM_MAX_CLASS]; 1713 1714 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1715 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1716 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1717 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1718 FIRE_TLU_UELE, DATA_TYPE_UINT64, 1719 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE), 1720 FIRE_TLU_UIE, DATA_TYPE_UINT64, 1721 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE), 1722 FIRE_TLU_UIS, DATA_TYPE_UINT64, 1723 ss_reg, 1724 FIRE_TLU_UESS, DATA_TYPE_UINT64, 1725 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_SET), 1726 NULL); 1727 1728 return (PX_OK); 1729 } 1730 1731 /* PCIEX UE Errors */ 1732 /* ARGSUSED */ 1733 px_err_pciex_ce_handle(dev_info_t *rpdip, caddr_t csr_base, 1734 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1735 px_err_bit_desc_t *err_bit_descr) 1736 { 1737 uint32_t mask = (uint32_t)BITMASK(err_bit_descr->bit); 1738 1739 return ((err_bit_descr->bit >= 32 && px_fabric_die_rc_ce_gos) ? 1740 PX_FATAL_GOS : PX_FABRIC_ERR_SEV(mask, px_fabric_die_rc_ce, 1741 px_fabric_die_rc_ce_gos)); 1742 } 1743 1744 /* PCI-E Correctable Errors - see io erpt doc, section 3.6 */ 1745 PX_ERPT_SEND_DEC(pciex_ce) 1746 { 1747 char buf[FM_MAX_CLASS]; 1748 1749 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1750 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1751 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1752 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1753 FIRE_TLU_CELE, DATA_TYPE_UINT64, 1754 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_LOG_ENABLE), 1755 FIRE_TLU_CIE, DATA_TYPE_UINT64, 1756 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_INTERRUPT_ENABLE), 1757 FIRE_TLU_CIS, DATA_TYPE_UINT64, 1758 ss_reg, 1759 FIRE_TLU_CESS, DATA_TYPE_UINT64, 1760 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_STATUS_SET), 1761 NULL); 1762 1763 return (PX_OK); 1764 } 1765 1766 /* TLU Other Event Status (receive only) - see io erpt doc, section 3.7 */ 1767 PX_ERPT_SEND_DEC(pciex_rx_oe) 1768 { 1769 char buf[FM_MAX_CLASS]; 1770 1771 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1772 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1773 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1774 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1775 FIRE_TLU_OEELE, DATA_TYPE_UINT64, 1776 CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE), 1777 FIRE_TLU_OEIE, DATA_TYPE_UINT64, 1778 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_ENABLE), 1779 FIRE_TLU_OEIS, DATA_TYPE_UINT64, 1780 ss_reg, 1781 FIRE_TLU_OEESS, DATA_TYPE_UINT64, 1782 CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_SET), 1783 FIRE_TLU_RUEH1L, DATA_TYPE_UINT64, 1784 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG), 1785 FIRE_TLU_RUEH2L, DATA_TYPE_UINT64, 1786 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG), 1787 NULL); 1788 1789 return (PX_OK); 1790 } 1791 1792 /* TLU Other Event Status (rx + tx) - see io erpt doc, section 3.8 */ 1793 PX_ERPT_SEND_DEC(pciex_rx_tx_oe) 1794 { 1795 char buf[FM_MAX_CLASS]; 1796 1797 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1798 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1799 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1800 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1801 FIRE_TLU_OEELE, DATA_TYPE_UINT64, 1802 CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE), 1803 FIRE_TLU_OEIE, DATA_TYPE_UINT64, 1804 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_ENABLE), 1805 FIRE_TLU_OEIS, DATA_TYPE_UINT64, 1806 ss_reg, 1807 FIRE_TLU_OEESS, DATA_TYPE_UINT64, 1808 CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_SET), 1809 FIRE_TLU_ROEEH1L, DATA_TYPE_UINT64, 1810 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG), 1811 FIRE_TLU_ROEEH2L, DATA_TYPE_UINT64, 1812 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG), 1813 FIRE_TLU_TOEEH1L, DATA_TYPE_UINT64, 1814 CSR_XR(csr_base, TLU_TRANSMIT_OTHER_EVENT_HEADER1_LOG), 1815 FIRE_TLU_TOEEH2L, DATA_TYPE_UINT64, 1816 CSR_XR(csr_base, TLU_TRANSMIT_OTHER_EVENT_HEADER2_LOG), 1817 NULL); 1818 1819 return (PX_OK); 1820 } 1821 1822 /* TLU Other Event - see io erpt doc, section 3.9 */ 1823 PX_ERPT_SEND_DEC(pciex_oe) 1824 { 1825 char buf[FM_MAX_CLASS]; 1826 1827 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1828 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1829 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1830 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1831 FIRE_TLU_OEELE, DATA_TYPE_UINT64, 1832 CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE), 1833 FIRE_TLU_OEIE, DATA_TYPE_UINT64, 1834 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_ENABLE), 1835 FIRE_TLU_OEIS, DATA_TYPE_UINT64, 1836 ss_reg, 1837 FIRE_TLU_OEESS, DATA_TYPE_UINT64, 1838 CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_SET), 1839 NULL); 1840 1841 return (PX_OK); 1842 } 1843 1844 /* TLU Other Event - Link Down see io erpt doc, section 3.9 */ 1845 PX_ERPT_SEND_DEC(pciex_ldn) 1846 { 1847 px_t *px_p = DIP_TO_STATE(rpdip); 1848 1849 /* 1850 * Don't post ereport, if ldn event is due to 1851 * power management. 1852 */ 1853 if (px_p->px_pm_flags & PX_LDN_EXPECTED) { 1854 px_p->px_pm_flags &= ~PX_LDN_EXPECTED; 1855 return (PX_OK); 1856 } 1857 return (PX_ERPT_SEND(pciex_oe)(rpdip, csr_base, ss_reg, derr, 1858 class_name)); 1859 1860 } 1861 1862 /* TLU Other Event - Link Up see io erpt doc, section 3.9 */ 1863 PX_ERPT_SEND_DEC(pciex_lup) 1864 { 1865 px_t *px_p = DIP_TO_STATE(rpdip); 1866 1867 /* 1868 * Don't post ereport, if lup event is due to 1869 * power management. 1870 */ 1871 if (px_p->px_pm_flags & PX_LUP_EXPECTED) { 1872 px_p->px_pm_flags &= ~PX_LUP_EXPECTED; 1873 return (PX_OK); 1874 } 1875 1876 return (PX_ERPT_SEND(pciex_oe)(rpdip, csr_base, ss_reg, derr, 1877 class_name)); 1878 } 1879