1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_OBERON_REGS_H 27 #define _SYS_OBERON_REGS_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 36 #define UBC_ERROR_LOG_ENABLE 0x471000 37 #define UBC_ERROR_STATUS_CLEAR 0x471018 38 #define UBC_INTERRUPT_ENABLE 0x471008 39 #define UBC_INTERRUPT_STATUS 0x471010 40 #define UBC_INTERRUPT_STATUS_DMARDUEA_P 0 41 #define UBC_INTERRUPT_STATUS_DMAWTUEA_P 1 42 #define UBC_INTERRUPT_STATUS_MEMRDAXA_P 2 43 #define UBC_INTERRUPT_STATUS_MEMWTAXA_P 3 44 #define UBC_INTERRUPT_STATUS_DMARDUEB_P 8 45 #define UBC_INTERRUPT_STATUS_DMAWTUEB_P 9 46 #define UBC_INTERRUPT_STATUS_MEMRDAXB_P 10 47 #define UBC_INTERRUPT_STATUS_MEMWTAXB_P 11 48 #define UBC_INTERRUPT_STATUS_PIOWTUE_P 16 49 #define UBC_INTERRUPT_STATUS_PIOWBEUE_P 17 50 #define UBC_INTERRUPT_STATUS_PIORBEUE_P 18 51 #define UBC_INTERRUPT_STATUS_DMARDUEA_S 32 52 #define UBC_INTERRUPT_STATUS_DMAWTUEA_S 33 53 #define UBC_INTERRUPT_STATUS_MEMRDAXA_S 34 54 #define UBC_INTERRUPT_STATUS_MEMWTAXA_S 35 55 #define UBC_INTERRUPT_STATUS_DMARDUEB_S 40 56 #define UBC_INTERRUPT_STATUS_DMAWTUEB_S 41 57 #define UBC_INTERRUPT_STATUS_MEMRDAXB_S 42 58 #define UBC_INTERRUPT_STATUS_MEMWTAXB_S 43 59 #define UBC_INTERRUPT_STATUS_PIOWTUE_S 48 60 #define UBC_INTERRUPT_STATUS_PIOWBEUE_S 49 61 #define UBC_INTERRUPT_STATUS_PIORBEUE_S 50 62 #define UBC_ERROR_STATUS_SET 0x471020 63 #define UBC_PERFORMANCE_COUNTER_SELECT 0x472000 64 #define UBC_PERFORMANCE_COUNTER_ZERO 0x472008 65 #define UBC_PERFORMANCE_COUNTER_ONE 0x472010 66 #define UBC_PERFORMANCE_COUNTER_SEL_MASKS 0x3f3f 67 #define UBC_MEMORY_UE_LOG 0x471028 68 #define UBC_MEMORY_UE_LOG_EID 60 69 #define UBC_MEMORY_UE_LOG_EID_MASK 0x3 70 #define UBC_MEMORY_UE_LOG_MARKED 48 71 #define UBC_MEMORY_UE_LOG_MARKED_MASK 0x3fff 72 #define UBC_MARKED_MAX_CPUID_MASK 0x1ff 73 /* 74 * Class qualifiers on errors for which EID is valid. 75 */ 76 #define UBC_EID_MEM 0 77 #define UBC_EID_CHANNEL 1 78 #define UBC_EID_CPU 2 79 #define UBC_EID_PATH 3 80 81 #define OBERON_UBC_ID_MAX 64 82 #define OBERON_UBC_ID_IOC 0 83 #define OBERON_UBC_ID_LSB 2 84 85 #define OBERON_PORT_ID_IOC 1 86 #define OBERON_PORT_ID_IOC_MASK 0x03 87 #define OBERON_PORT_ID_LSB 4 88 #define OBERON_PORT_ID_LSB_MASK 0x0F 89 90 #define INTERRUPT_MAPPING_ENTRIES_T_DESTID 21 91 #define INTERRUPT_MAPPING_ENTRIES_T_DESTID_MASK 0x3ff 92 93 #define OBERON_TLU_CONTROL_DRN_TR_DIS 35 94 #define OBERON_TLU_CONTROL_CPLEP_DEN 34 95 #define OBERON_TLU_CONTROL_ECRCCHK_DIS 33 96 #define OBERON_TLU_CONTROL_ECRCGEN_DIS 32 97 98 #define TLU_SLOT_CAPABILITIES_HP 6 99 #define TLU_SLOT_CAPABILITIES_HPSUP 5 100 #define TLU_SLOT_CAPABILITIES_PWINDP 4 101 #define TLU_SLOT_CAPABILITIES_ATINDP 3 102 #define TLU_SLOT_CAPABILITIES_MRLSP 2 103 #define TLU_SLOT_CAPABILITIES_PWCNTLP 1 104 #define TLU_SLOT_CAPABILITIES_ATBTNP 0 105 106 #define DLU_INTERRUPT_MASK 0xe2048 107 #define DLU_INTERRUPT_MASK_MSK_INTERRUPT_EN 31 108 #define DLU_INTERRUPT_MASK_MSK_LINK_LAYER 5 109 #define DLU_INTERRUPT_MASK_MSK_PHY_ERROR 4 110 #define DLU_LINK_LAYER_CONFIG 0xe2200 111 #define DLU_LINK_LAYER_CONFIG_VC0_EN 8 112 #define DLU_LINK_LAYER_CONFIG_TLP_XMIT_FC_EN 3 113 #define DLU_LINK_LAYER_CONFIG_FREQ_ACK_ENABLE 2 114 #define DLU_LINK_LAYER_CONFIG_RETRY_DISABLE 1 115 #define DLU_LINK_LAYER_STATUS 0xe2208 116 #define DLU_LINK_LAYER_STATUS_LNK_STATE_MACH_STS_MASK 0x7 117 #define DLU_LINK_LAYER_STATUS_LNK_STATE_MACH_STS_DL_INACTIVE 0x1 118 #define DLU_LINK_LAYER_STATUS_LNK_STATE_MACH_STS_DL_INIT 0x2 119 #define DLU_LINK_LAYER_STATUS_LNK_STATE_MACH_STS_DL_ACTIVE 0x4 120 #define DLU_LINK_LAYER_STATUS_DLUP_STS 3 121 #define DLU_LINK_LAYER_STATUS_INIT_FC_SM_STS 4 122 #define DLU_LINK_LAYER_STATUS_INIT_FC_SM_STS_MASK 0x3 123 #define DLU_LINK_LAYER_STATUS_INIT_FC_SM_STS_FC_IDLE 0x0 124 #define DLU_LINK_LAYER_STATUS_INIT_FC_SM_STS_FC_INIT_1 0x1 125 #define DLU_LINK_LAYER_STATUS_INIT_FC_SM_STS_FC_INIT_2 0x3 126 #define DLU_LINK_LAYER_STATUS_INIT_FC_SM_STS_FC_INIT_DONE 0x2 127 #define DLU_LINK_LAYER_INTERRUPT_AND_STATUS 0xe2210 128 #define DLU_LINK_LAYER_INTERRUPT_AND_STATUS_INT_LINK_ERR_ACT 31 129 #define DLU_LINK_LAYER_INTERRUPT_AND_STATUS_INT_PARABUS_PE 23 130 #define DLU_LINK_LAYER_INTERRUPT_AND_STATUS_INT_UNSPRTD_DLLP 22 131 #define DLU_LINK_LAYER_INTERRUPT_AND_STATUS_INT_SRC_ERR_TLP 17 132 #define DLU_LINK_LAYER_INTERRUPT_MASK 0xe2220 133 #define DLU_LINK_LAYER_INTERRUPT_MASK_MSK_LINK_ERR_ACT 31 134 #define DLU_LINK_LAYER_INTERRUPT_MASK_MSK_PARABUS_PE 23 135 #define DLU_LINK_LAYER_INTERRUPT_MASK_MSK_UNSPRTD_DLLP 22 136 #define DLU_LINK_LAYER_INTERRUPT_MASK_MSK_SRC_ERR_TLP 17 137 #define DLU_FLOW_CONTROL_UPDATE_CONTROL 0xe2240 138 #define DLU_FLOW_CONTROL_UPDATE_CONTROL_FC0_U_C_EN 2 139 #define DLU_FLOW_CONTROL_UPDATE_CONTROL_FC0_U_NP_EN 1 140 #define DLU_FLOW_CONTROL_UPDATE_CONTROL_FC0_U_P_EN 0 141 #define DLU_TXLINK_REPLAY_TIMER_THRESHOLD 0xe2410 142 #define DLU_TXLINK_REPLAY_TIMER_THRESHOLD_RPLAY_TMR_THR 0 143 #define DLU_TXLINK_REPLAY_TIMER_THRESHOLD_RPLAY_TMR_THR_MASK 0xfffff 144 #define DLU_TXLINK_REPLAY_TIMER_THRESHOLD_DEFAULT 0xc9 145 #define DLU_PORT_CONTROL 0xe2b00 146 #define DLU_PORT_CONTROL_CK_EN 0 147 #define DLU_PORT_STATUS 0xe2b08 148 149 #define MMU_INTERRUPT_STATUS_TTC_DUE_P 8 150 #define MMU_INTERRUPT_STATUS_TTC_DUE_S 40 151 #define ILU_INTERRUPT_STATUS_IHB_UE_P 4 152 #define ILU_INTERRUPT_STATUS_IHB_UE_S 36 153 #define TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_ECRC_P 19 154 #define TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_ECRC_S 51 155 #define TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_POIS_P 12 156 #define TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_POIS_S 44 157 #define TLU_OTHER_EVENT_STATUS_CLEAR_EIUE_P 0 158 #define TLU_OTHER_EVENT_STATUS_CLEAR_EIUE_S 32 159 #define TLU_OTHER_EVENT_STATUS_CLEAR_ERBUE_P 1 160 #define TLU_OTHER_EVENT_STATUS_CLEAR_ERBUE_S 33 161 #define TLU_OTHER_EVENT_STATUS_CLEAR_TLUEITMO_P 7 162 #define TLU_OTHER_EVENT_STATUS_CLEAR_TLUEITMO_S 39 163 #define TLU_OTHER_EVENT_STATUS_CLEAR_EHBUE_P 12 164 #define TLU_OTHER_EVENT_STATUS_CLEAR_EHBUE_S 44 165 #define TLU_OTHER_EVENT_STATUS_CLEAR_EDBUE_P 12 166 #define TLU_OTHER_EVENT_STATUS_CLEAR_EDBUE_S 44 167 168 #define TLU_CONTROL_DRN_TR_DIS 35 169 170 #define TLU_SLOT_CONTROL 0x90038 171 #define TLU_SLOT_CONTROL_PWFDEN 1 172 #define TLU_SLOT_STATUS 0x90040 173 #define TLU_SLOT_STATUS_PSD 6 174 #define TLU_SLOT_STATUS_MRLS 5 175 #define TLU_SLOT_STATUS_CMDCPLT 4 176 #define TLU_SLOT_STATUS_PSDC 3 177 #define TLU_SLOT_STATUS_MRLC 2 178 #define TLU_SLOT_STATUS_PWFD 1 179 #define TLU_SLOT_STATUS_ABTN 0 180 181 #define FLP_PORT_LINK_CONTROL 0xe5008 182 #define FLP_PORT_LINK_CONTROL_RETRAIN 5 183 184 #define FLP_PORT_CONTROL 0xe5200 185 #define FLP_PORT_CONTROL_PORT_DIS 0 186 187 #define FLP_PORT_ACTIVE_STATUS 0xe5240 188 #define FLP_PORT_ACTIVE_STATUS_TRAIN_ERROR 1 189 190 #define HOTPLUG_CONTROL 0x88000 191 #define HOTPLUG_CONTROL_SLOTPON 3 192 #define HOTPLUG_CONTROL_PWREN 2 193 #define HOTPLUG_CONTROL_CLKEN 1 194 #define HOTPLUG_CONTROL_N_PERST 0 195 196 #define DRAIN_CONTROL_STATUS 0x51100 197 #define DRAIN_CONTROL_STATUS_DRAIN 0 198 199 #define PX_PCIEHP_PIL (LOCK_LEVEL - 1) 200 #ifdef __cplusplus 201 } 202 #endif 203 204 #endif /* _SYS_OBERON_REGS_H */ 205