1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* 27 * Schizo specifics implementation: 28 * interrupt mapping register 29 * PBM configuration 30 * ECC and PBM error handling 31 * Iommu mapping handling 32 * Streaming Cache flushing 33 */ 34 35 #include <sys/types.h> 36 #include <sys/kmem.h> 37 #include <sys/sysmacros.h> 38 #include <sys/async.h> 39 #include <sys/systm.h> 40 #include <sys/ivintr.h> 41 #include <sys/machsystm.h> /* lddphys() */ 42 #include <sys/machsystm.h> /* lddphys, intr_dist_add */ 43 #include <sys/iommutsb.h> 44 #include <sys/promif.h> /* prom_printf */ 45 #include <sys/map.h> 46 #include <sys/ddi.h> 47 #include <sys/sunddi.h> 48 #include <sys/sunndi.h> 49 #include <sys/spl.h> 50 #include <sys/fm/util.h> 51 #include <sys/ddi_impldefs.h> 52 #include <sys/fm/protocol.h> 53 #include <sys/fm/io/sun4upci.h> 54 #include <sys/fm/io/ddi.h> 55 #include <sys/fm/io/pci.h> 56 #include <sys/pci/pci_obj.h> 57 #include <sys/pci/pcisch.h> 58 #include <sys/pci/pcisch_asm.h> 59 #include <sys/x_call.h> /* XCALL_PIL */ 60 61 /*LINTLIBRARY*/ 62 63 extern uint8_t ldstub(uint8_t *); 64 65 #define IOMMU_CTX_BITMAP_SIZE (1 << (12 - 3)) 66 static void iommu_ctx_free(iommu_t *); 67 static int iommu_tlb_scrub(iommu_t *, int); 68 static uint32_t pci_identity_init(pci_t *); 69 70 static void pci_cb_clear_error(cb_t *, cb_errstate_t *); 71 static void pci_clear_error(pci_t *, pbm_errstate_t *); 72 static uint32_t pci_identity_init(pci_t *pci_p); 73 static int pci_intr_setup(pci_t *pci_p); 74 static void iommu_ereport_post(dev_info_t *, uint64_t, pbm_errstate_t *); 75 static void cb_ereport_post(dev_info_t *, uint64_t, cb_errstate_t *); 76 static void pcix_ereport_post(dev_info_t *, uint64_t, pbm_errstate_t *); 77 static void pci_format_ecc_addr(dev_info_t *dip, uint64_t *afar, 78 ecc_region_t region); 79 static void pci_pbm_errstate_get(pci_t *pci_p, pbm_errstate_t *pbm_err_p); 80 static void tm_vmem_free(ddi_dma_impl_t *mp, iommu_t *iommu_p, 81 dvma_addr_t dvma_pg, int npages); 82 83 static int pcix_ma_behind_bridge(pbm_errstate_t *pbm_err_p); 84 85 static pci_ksinfo_t *pci_name_kstat; 86 static pci_ksinfo_t *saf_name_kstat; 87 88 extern void pcix_set_cmd_reg(dev_info_t *child, uint16_t value); 89 90 /* called by pci_attach() DDI_ATTACH to initialize pci objects */ 91 int 92 pci_obj_setup(pci_t *pci_p) 93 { 94 pci_common_t *cmn_p; 95 uint32_t chip_id = pci_identity_init(pci_p); 96 uint32_t cmn_id = PCI_CMN_ID(ID_CHIP_TYPE(chip_id), pci_p->pci_id); 97 int ret; 98 99 /* Perform allocations first to avoid delicate unwinding. */ 100 if (pci_alloc_tsb(pci_p) != DDI_SUCCESS) 101 return (DDI_FAILURE); 102 103 mutex_enter(&pci_global_mutex); 104 cmn_p = get_pci_common_soft_state(cmn_id); 105 if (cmn_p == NULL) { 106 if (alloc_pci_common_soft_state(cmn_id) != DDI_SUCCESS) { 107 mutex_exit(&pci_global_mutex); 108 pci_free_tsb(pci_p); 109 return (DDI_FAILURE); 110 } 111 cmn_p = get_pci_common_soft_state(cmn_id); 112 cmn_p->pci_common_id = cmn_id; 113 cmn_p->pci_common_tsb_cookie = IOMMU_TSB_COOKIE_NONE; 114 } 115 116 ASSERT((pci_p->pci_side == 0) || (pci_p->pci_side == 1)); 117 if (cmn_p->pci_p[pci_p->pci_side]) { 118 /* second side attach */ 119 pci_p->pci_side = PCI_OTHER_SIDE(pci_p->pci_side); 120 ASSERT(cmn_p->pci_p[pci_p->pci_side] == NULL); 121 } 122 123 cmn_p->pci_p[pci_p->pci_side] = pci_p; 124 pci_p->pci_common_p = cmn_p; 125 126 if (cmn_p->pci_common_refcnt == 0) 127 cmn_p->pci_chip_id = chip_id; 128 129 ib_create(pci_p); 130 131 /* 132 * The initialization of cb internal interrupts depends on ib 133 */ 134 if (cmn_p->pci_common_refcnt == 0) { 135 cb_create(pci_p); 136 cmn_p->pci_common_cb_p = pci_p->pci_cb_p; 137 } else 138 pci_p->pci_cb_p = cmn_p->pci_common_cb_p; 139 140 iommu_create(pci_p); 141 142 if (cmn_p->pci_common_refcnt == 0) { 143 ecc_create(pci_p); 144 cmn_p->pci_common_ecc_p = pci_p->pci_ecc_p; 145 } else 146 pci_p->pci_ecc_p = cmn_p->pci_common_ecc_p; 147 148 pbm_create(pci_p); 149 sc_create(pci_p); 150 151 pci_fm_create(pci_p); 152 153 if ((ret = pci_intr_setup(pci_p)) != DDI_SUCCESS) 154 goto done; 155 156 pci_kstat_create(pci_p); 157 158 cmn_p->pci_common_attachcnt++; 159 cmn_p->pci_common_refcnt++; 160 done: 161 mutex_exit(&pci_global_mutex); 162 if (ret != DDI_SUCCESS) 163 cmn_err(CE_WARN, "pci_obj_setup failed %x", ret); 164 return (ret); 165 } 166 167 /* called by pci_detach() DDI_DETACH to destroy pci objects */ 168 void 169 pci_obj_destroy(pci_t *pci_p) 170 { 171 pci_common_t *cmn_p; 172 mutex_enter(&pci_global_mutex); 173 174 cmn_p = pci_p->pci_common_p; 175 cmn_p->pci_common_refcnt--; 176 cmn_p->pci_common_attachcnt--; 177 178 pci_kstat_destroy(pci_p); 179 180 /* schizo non-shared objects */ 181 pci_fm_destroy(pci_p); 182 183 sc_destroy(pci_p); 184 pbm_destroy(pci_p); 185 iommu_destroy(pci_p); 186 ib_destroy(pci_p); 187 188 if (cmn_p->pci_common_refcnt != 0) { 189 pci_intr_teardown(pci_p); 190 cmn_p->pci_p[pci_p->pci_side] = NULL; 191 mutex_exit(&pci_global_mutex); 192 return; 193 } 194 195 /* schizo shared objects - uses cmn_p, must be destroyed before cmn */ 196 ecc_destroy(pci_p); 197 cb_destroy(pci_p); 198 199 free_pci_common_soft_state(cmn_p->pci_common_id); 200 pci_intr_teardown(pci_p); 201 mutex_exit(&pci_global_mutex); 202 } 203 204 /* called by pci_attach() DDI_RESUME to (re)initialize pci objects */ 205 void 206 pci_obj_resume(pci_t *pci_p) 207 { 208 pci_common_t *cmn_p = pci_p->pci_common_p; 209 210 mutex_enter(&pci_global_mutex); 211 212 ib_configure(pci_p->pci_ib_p); 213 iommu_configure(pci_p->pci_iommu_p); 214 215 if (cmn_p->pci_common_attachcnt == 0) 216 ecc_configure(pci_p); 217 218 ib_resume(pci_p->pci_ib_p); 219 220 pbm_configure(pci_p->pci_pbm_p); 221 sc_configure(pci_p->pci_sc_p); 222 223 if (cmn_p->pci_common_attachcnt == 0) 224 cb_resume(pci_p->pci_cb_p); 225 226 pbm_resume(pci_p->pci_pbm_p); 227 228 cmn_p->pci_common_attachcnt++; 229 mutex_exit(&pci_global_mutex); 230 } 231 232 /* called by pci_detach() DDI_SUSPEND to suspend pci objects */ 233 void 234 pci_obj_suspend(pci_t *pci_p) 235 { 236 mutex_enter(&pci_global_mutex); 237 238 pbm_suspend(pci_p->pci_pbm_p); 239 ib_suspend(pci_p->pci_ib_p); 240 241 if (!--pci_p->pci_common_p->pci_common_attachcnt) 242 cb_suspend(pci_p->pci_cb_p); 243 244 mutex_exit(&pci_global_mutex); 245 } 246 247 /* 248 * add an additional 0x35 or 0x36 ino interrupt on platforms don't have them 249 * This routine has multiple places that assumes interrupt takes one cell 250 * each and cell size is same as integer size. 251 */ 252 static int 253 pci_intr_setup(pci_t *pci_p) 254 { 255 dev_info_t *dip = pci_p->pci_dip; 256 pbm_t *pbm_p = pci_p->pci_pbm_p; 257 cb_t *cb_p = pci_p->pci_cb_p; 258 uint32_t *intr_buf, *new_intr_buf; 259 int intr_len, intr_cnt, ret; 260 261 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 262 "interrupts", (caddr_t)&intr_buf, &intr_len) != DDI_SUCCESS) 263 cmn_err(CE_PANIC, "%s%d: no interrupts property\n", 264 ddi_driver_name(dip), ddi_get_instance(dip)); 265 266 intr_cnt = BYTES_TO_1275_CELLS(intr_len); 267 if (intr_cnt < CBNINTR_CDMA) /* CBNINTR_CDMA is 0 based */ 268 cmn_err(CE_PANIC, "%s%d: <%d interrupts", ddi_driver_name(dip), 269 ddi_get_instance(dip), CBNINTR_CDMA); 270 271 if (intr_cnt == CBNINTR_CDMA) 272 intr_cnt++; 273 274 new_intr_buf = kmem_alloc(CELLS_1275_TO_BYTES(intr_cnt), KM_SLEEP); 275 bcopy(intr_buf, new_intr_buf, intr_len); 276 kmem_free(intr_buf, intr_len); 277 278 new_intr_buf[CBNINTR_CDMA] = PBM_CDMA_INO_BASE + pci_p->pci_side; 279 pci_p->pci_inos = new_intr_buf; 280 pci_p->pci_inos_len = CELLS_1275_TO_BYTES(intr_cnt); 281 282 if (ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "interrupts", 283 (int *)new_intr_buf, intr_cnt)) 284 cmn_err(CE_PANIC, "%s%d: cannot update interrupts property\n", 285 ddi_driver_name(dip), ddi_get_instance(dip)); 286 287 if (pci_p->pci_common_p->pci_common_refcnt == 0) { 288 cb_p->cb_no_of_inos = intr_cnt; 289 if (ret = cb_register_intr(pci_p)) 290 goto teardown; 291 if (ret = ecc_register_intr(pci_p)) 292 goto teardown; 293 294 intr_dist_add(cb_intr_dist, cb_p); 295 cb_enable_intr(pci_p); 296 ecc_enable_intr(pci_p); 297 } 298 299 if (CHIP_TYPE(pci_p) != PCI_CHIP_SCHIZO) 300 pbm_p->pbm_sync_ino = pci_p->pci_inos[CBNINTR_PBM]; 301 if (ret = pbm_register_intr(pbm_p)) { 302 if (pci_p->pci_common_p->pci_common_refcnt == 0) 303 intr_dist_rem(cb_intr_dist, cb_p); 304 goto teardown; 305 } 306 intr_dist_add(pbm_intr_dist, pbm_p); 307 ib_intr_enable(pci_p, pci_p->pci_inos[CBNINTR_PBM]); 308 ib_intr_enable(pci_p, pci_p->pci_inos[CBNINTR_CDMA]); 309 310 intr_dist_add_weighted(ib_intr_dist_all, pci_p->pci_ib_p); 311 return (DDI_SUCCESS); 312 teardown: 313 pci_intr_teardown(pci_p); 314 return (ret); 315 } 316 317 uint64_t 318 pci_sc_configure(pci_t *pci_p) 319 { 320 int instance; 321 dev_info_t *dip = pci_p->pci_dip; 322 323 instance = ddi_get_instance(dip); 324 if ((pci_xmits_sc_max_prf & (1 << instance)) && 325 (CHIP_TYPE(pci_p) == PCI_CHIP_XMITS)) 326 return (XMITS_SC_MAX_PRF); 327 else 328 return (0); 329 } 330 331 static void 332 pci_schizo_cdma_sync(pbm_t *pbm_p) 333 { 334 pci_t *pci_p = pbm_p->pbm_pci_p; 335 hrtime_t start_time; 336 volatile uint64_t *clr_p = ib_clear_intr_reg_addr(pci_p->pci_ib_p, 337 pci_p->pci_inos[CBNINTR_CDMA]); 338 uint32_t fail_cnt = pci_cdma_intr_count; 339 340 mutex_enter(&pbm_p->pbm_sync_mutex); 341 #ifdef PBM_CDMA_DEBUG 342 pbm_p->pbm_cdma_req_cnt++; 343 #endif /* PBM_CDMA_DEBUG */ 344 pbm_p->pbm_cdma_flag = PBM_CDMA_PEND; 345 IB_INO_INTR_TRIG(clr_p); 346 wait: 347 start_time = gethrtime(); 348 while (pbm_p->pbm_cdma_flag != PBM_CDMA_DONE) { 349 if (gethrtime() - start_time <= pci_cdma_intr_timeout) 350 continue; 351 if (--fail_cnt > 0) 352 goto wait; 353 if (pbm_p->pbm_cdma_flag == PBM_CDMA_DONE) 354 break; 355 cmn_err(CE_PANIC, "%s (%s): consistent dma sync timeout", 356 pbm_p->pbm_nameinst_str, pbm_p->pbm_nameaddr_str); 357 } 358 #ifdef PBM_CDMA_DEBUG 359 if (pbm_p->pbm_cdma_flag != PBM_CDMA_DONE) 360 pbm_p->pbm_cdma_to_cnt++; 361 else { 362 start_time = gethrtime() - start_time; 363 pbm_p->pbm_cdma_success_cnt++; 364 pbm_p->pbm_cdma_latency_sum += start_time; 365 if (start_time > pbm_p->pbm_cdma_latency_max) 366 pbm_p->pbm_cdma_latency_max = start_time; 367 } 368 #endif /* PBM_CDMA_DEBUG */ 369 mutex_exit(&pbm_p->pbm_sync_mutex); 370 } 371 372 #if !defined(lint) 373 #include <sys/cpuvar.h> 374 #endif 375 376 #define SYNC_HW_BUSY(pa, mask) (lddphysio(pa) & (mask)) 377 378 /* 379 * Consistent DMA Sync/Flush 380 * 381 * XMITS and Tomatillo use multi-threaded sync/flush register. 382 * Called from interrupt wrapper: the associated ino is used to index 383 * the distinctive register bit. 384 * Called from pci_dma_sync(): the bit belongs to PBM is shared 385 * for all calls from pci_dma_sync(). Xmits requires serialization 386 * while Tomatillo does not. 387 */ 388 void 389 pci_pbm_dma_sync(pbm_t *pbm_p, ib_ino_t ino) 390 { 391 pci_t *pci_p = pbm_p->pbm_pci_p; 392 hrtime_t start_time; 393 uint64_t ino_mask, sync_reg_pa; 394 volatile uint64_t flag_val; 395 uint32_t locked, chip_type = CHIP_TYPE(pci_p); 396 int i; 397 398 if (chip_type == PCI_CHIP_SCHIZO) { 399 pci_schizo_cdma_sync(pbm_p); 400 return; 401 } 402 403 sync_reg_pa = pbm_p->pbm_sync_reg_pa; 404 405 locked = 0; 406 if (((chip_type == PCI_CHIP_XMITS) && (ino == pbm_p->pbm_sync_ino)) || 407 pci_sync_lock) { 408 locked = 1; 409 mutex_enter(&pbm_p->pbm_sync_mutex); 410 } 411 ino_mask = 1ull << ino; 412 stdphysio(sync_reg_pa, ino_mask); 413 414 for (i = 0; i < 5; i++) { 415 if ((flag_val = SYNC_HW_BUSY(sync_reg_pa, ino_mask)) == 0) 416 goto done; 417 } 418 419 start_time = gethrtime(); 420 for (; (flag_val = SYNC_HW_BUSY(sync_reg_pa, ino_mask)) != 0; i++) { 421 if (gethrtime() - start_time > pci_sync_buf_timeout) 422 break; 423 } 424 425 if (flag_val && SYNC_HW_BUSY(sync_reg_pa, ino_mask) && !panicstr) 426 cmn_err(CE_PANIC, "%s: pbm dma sync %lx,%lx timeout!", 427 pbm_p->pbm_nameaddr_str, sync_reg_pa, flag_val); 428 done: 429 /* optional: stdphysio(sync_reg_pa - 8, ino_mask); */ 430 if (locked) 431 mutex_exit(&pbm_p->pbm_sync_mutex); 432 433 if (tomatillo_store_store_wrka) { 434 #if !defined(lint) 435 kpreempt_disable(); 436 #endif 437 tomatillo_store_store_order(); 438 #if !defined(lint) 439 kpreempt_enable(); 440 #endif 441 } 442 443 } 444 445 /*ARGSUSED*/ 446 void 447 pci_fix_ranges(pci_ranges_t *rng_p, int rng_entries) 448 { 449 } 450 451 /* 452 * map_pci_registers 453 * 454 * This function is called from the attach routine to map the registers 455 * accessed by this driver. 456 * 457 * used by: pci_attach() 458 * 459 * return value: DDI_FAILURE on failure 460 */ 461 int 462 map_pci_registers(pci_t *pci_p, dev_info_t *dip) 463 { 464 ddi_device_acc_attr_t attr; 465 int len; 466 467 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 468 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 469 470 attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC; 471 472 /* 473 * Register set 0 is PCI CSR Base 474 */ 475 if (ddi_regs_map_setup(dip, 0, &pci_p->pci_address[0], 0, 0, 476 &attr, &pci_p->pci_ac[0]) != DDI_SUCCESS) { 477 len = 0; 478 goto fail; 479 } 480 /* 481 * Register set 1 is Schizo CSR Base 482 */ 483 if (ddi_regs_map_setup(dip, 1, &pci_p->pci_address[1], 0, 0, 484 &attr, &pci_p->pci_ac[1]) != DDI_SUCCESS) { 485 len = 1; 486 goto fail; 487 } 488 489 /* 490 * The third register set contains the bridge's configuration 491 * header. This header is at the very beginning of the bridge's 492 * configuration space. This space has litte-endian byte order. 493 */ 494 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 495 if (ddi_regs_map_setup(dip, 2, &pci_p->pci_address[2], 0, 496 PCI_CONF_HDR_SIZE, &attr, &pci_p->pci_ac[2]) != DDI_SUCCESS) { 497 len = 2; 498 goto fail; 499 } 500 501 if (ddi_getproplen(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 502 "reg", &len) || (len / sizeof (pci_nexus_regspec_t) < 4)) 503 goto done; 504 505 /* 506 * The optional fourth register bank points to the 507 * interrupt concentrator registers. 508 */ 509 attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC; 510 if (ddi_regs_map_setup(dip, 3, &pci_p->pci_address[3], 0, 511 0, &attr, &pci_p->pci_ac[3]) != DDI_SUCCESS) { 512 len = 3; 513 goto fail; 514 } 515 516 done: 517 DEBUG4(DBG_ATTACH, dip, "address (%p,%p,%p,%p)\n", 518 pci_p->pci_address[0], pci_p->pci_address[1], 519 pci_p->pci_address[2], pci_p->pci_address[3]); 520 521 return (DDI_SUCCESS); 522 523 524 fail: 525 cmn_err(CE_WARN, "%s%d: unable to map reg entry %d\n", 526 ddi_driver_name(dip), ddi_get_instance(dip), len); 527 for (; len--; ddi_regs_map_free(&pci_p->pci_ac[len])) 528 ; 529 return (DDI_FAILURE); 530 } 531 532 /* 533 * unmap_pci_registers: 534 * 535 * This routine unmap the registers mapped by map_pci_registers. 536 * 537 * used by: pci_detach() 538 * 539 * return value: none 540 */ 541 void 542 unmap_pci_registers(pci_t *pci_p) 543 { 544 int i; 545 546 for (i = 0; i < 4; i++) { 547 if (pci_p->pci_ac[i]) 548 ddi_regs_map_free(&pci_p->pci_ac[i]); 549 } 550 } 551 552 uint64_t 553 ib_get_map_reg(ib_mondo_t mondo, uint32_t cpu_id) 554 { 555 uint32_t agent_id; 556 uint32_t node_id; 557 558 /* ensure that cpu_id is only 10 bits. */ 559 ASSERT((cpu_id & ~0x3ff) == 0); 560 561 agent_id = cpu_id & 0x1f; 562 node_id = (cpu_id >> 5) & 0x1f; 563 564 return ((mondo) | (agent_id << COMMON_INTR_MAP_REG_TID_SHIFT) | 565 (node_id << SCHIZO_INTR_MAP_REG_NID_SHIFT) | 566 COMMON_INTR_MAP_REG_VALID); 567 } 568 569 uint32_t 570 ib_map_reg_get_cpu(volatile uint64_t reg) 571 { 572 return (((reg & COMMON_INTR_MAP_REG_TID) >> 573 COMMON_INTR_MAP_REG_TID_SHIFT) | 574 ((reg & SCHIZO_INTR_MAP_REG_NID) >> 575 (SCHIZO_INTR_MAP_REG_NID_SHIFT-5))); 576 } 577 578 uint64_t * 579 ib_intr_map_reg_addr(ib_t *ib_p, ib_ino_t ino) 580 { 581 /* 582 * Schizo maps all interrupts in one contiguous area. 583 * (PCI_CSRBase + 0x00.1000 + INO * 8). 584 */ 585 return ((uint64_t *)(ib_p->ib_intr_map_regs) + (ino & 0x3f)); 586 } 587 588 uint64_t * 589 ib_clear_intr_reg_addr(ib_t *ib_p, ib_ino_t ino) /* XXX - needs work */ 590 { 591 /* 592 * Schizo maps clear intr. registers in contiguous area. 593 * (PCI_CSRBase + 0x00.1400 + INO * 8). 594 */ 595 return ((uint64_t *)(ib_p->ib_slot_clear_intr_regs) + (ino & 0x3f)); 596 } 597 598 /* 599 * schizo does not have mapping register per slot, so no sharing 600 * is done. 601 */ 602 /*ARGSUSED*/ 603 void 604 ib_ino_map_reg_share(ib_t *ib_p, ib_ino_t ino, ib_ino_info_t *ino_p) 605 { 606 } 607 608 /* 609 * return true if there are interrupts using this mapping register 610 */ 611 /*ARGSUSED*/ 612 int 613 ib_ino_map_reg_unshare(ib_t *ib_p, ib_ino_t ino, ib_ino_info_t *ino_p) 614 { 615 return (ino_p->ino_ipil_size); 616 } 617 618 void 619 pci_pbm_intr_dist(pbm_t *pbm_p) 620 { 621 pci_t *pci_p = pbm_p->pbm_pci_p; 622 ib_t *ib_p = pci_p->pci_ib_p; 623 ib_ino_t ino = IB_MONDO_TO_INO(pci_p->pci_inos[CBNINTR_CDMA]); 624 625 mutex_enter(&pbm_p->pbm_sync_mutex); 626 ib_intr_dist_nintr(ib_p, ino, ib_intr_map_reg_addr(ib_p, ino)); 627 mutex_exit(&pbm_p->pbm_sync_mutex); 628 } 629 630 uint32_t 631 pci_xlate_intr(dev_info_t *dip, dev_info_t *rdip, ib_t *ib_p, uint32_t intr) 632 { 633 return (IB_INO_TO_MONDO(ib_p, intr)); 634 } 635 636 637 /* 638 * Return the cpuid to to be used for an ino. We have no special cpu 639 * assignment constraints for this nexus, so just call intr_dist_cpuid(). 640 */ 641 /* ARGSUSED */ 642 uint32_t 643 pci_intr_dist_cpuid(ib_t *ib_p, ib_ino_info_t *ino_p) 644 { 645 return (intr_dist_cpuid()); 646 } 647 648 void 649 pci_cb_teardown(pci_t *pci_p) 650 { 651 cb_t *cb_p = pci_p->pci_cb_p; 652 uint32_t mondo; 653 654 if (!pci_buserr_interrupt) 655 return; 656 657 mondo = ((pci_p->pci_cb_p->cb_ign << PCI_INO_BITS) | 658 pci_p->pci_inos[CBNINTR_BUS_ERROR]); 659 mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo); 660 661 cb_disable_nintr(cb_p, CBNINTR_BUS_ERROR, IB_INTR_WAIT); 662 VERIFY(rem_ivintr(mondo, pci_pil[CBNINTR_BUS_ERROR]) == 0); 663 } 664 665 int 666 cb_register_intr(pci_t *pci_p) 667 { 668 uint32_t mondo; 669 670 if (!pci_buserr_interrupt) 671 return (DDI_SUCCESS); 672 673 mondo = ((pci_p->pci_cb_p->cb_ign << PCI_INO_BITS) | 674 pci_p->pci_inos[CBNINTR_BUS_ERROR]); 675 mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo); 676 677 VERIFY(add_ivintr(mondo, pci_pil[CBNINTR_BUS_ERROR], 678 (intrfunc)cb_buserr_intr, (caddr_t)pci_p->pci_cb_p, 679 NULL, NULL) == 0); 680 681 return (PCI_ATTACH_RETCODE(PCI_CB_OBJ, PCI_OBJ_INTR_ADD, DDI_SUCCESS)); 682 } 683 684 void 685 cb_enable_intr(pci_t *pci_p) 686 { 687 if (pci_buserr_interrupt) 688 cb_enable_nintr(pci_p, CBNINTR_BUS_ERROR); 689 } 690 691 uint64_t 692 cb_ino_to_map_pa(cb_t *cb_p, ib_ino_t ino) 693 { 694 return (cb_p->cb_map_pa + (ino << 3)); 695 } 696 697 uint64_t 698 cb_ino_to_clr_pa(cb_t *cb_p, ib_ino_t ino) 699 { 700 return (cb_p->cb_clr_pa + (ino << 3)); 701 } 702 703 /* 704 * Useful on psycho only. 705 */ 706 int 707 cb_remove_xintr(pci_t *pci_p, dev_info_t *dip, dev_info_t *rdip, ib_ino_t ino, 708 ib_mondo_t mondo) 709 { 710 return (DDI_FAILURE); 711 } 712 713 void 714 pbm_configure(pbm_t *pbm_p) 715 { 716 pci_t *pci_p = pbm_p->pbm_pci_p; 717 dev_info_t *dip = pbm_p->pbm_pci_p->pci_dip; 718 int instance = ddi_get_instance(dip); 719 uint64_t l; 720 uint64_t mask = 1ll << instance; 721 ushort_t s = 0; 722 723 l = *pbm_p->pbm_ctrl_reg; /* save control register state */ 724 DEBUG1(DBG_ATTACH, dip, "pbm_configure: ctrl reg=%llx\n", l); 725 726 /* 727 * See if any SERR# signals are asserted. We'll clear them later. 728 */ 729 if (l & COMMON_PCI_CTRL_SERR) 730 cmn_err(CE_WARN, "%s%d: SERR asserted on pci bus\n", 731 ddi_driver_name(dip), instance); 732 733 /* 734 * Determine if PCI bus is running at 33 or 66 mhz. 735 */ 736 if (l & COMMON_PCI_CTRL_SPEED) 737 pbm_p->pbm_speed = PBM_SPEED_66MHZ; 738 else 739 pbm_p->pbm_speed = PBM_SPEED_33MHZ; 740 DEBUG1(DBG_ATTACH, dip, "pbm_configure: %d mhz\n", 741 pbm_p->pbm_speed == PBM_SPEED_66MHZ ? 66 : 33); 742 743 if (pci_set_dto_value & mask) { 744 l &= ~(3ull << SCHIZO_PCI_CTRL_PTO_SHIFT); 745 l |= pci_dto_value << SCHIZO_PCI_CTRL_PTO_SHIFT; 746 } else if (PCI_CHIP_ID(pci_p) >= TOMATILLO_VER_21) { 747 l |= (3ull << SCHIZO_PCI_CTRL_PTO_SHIFT); 748 } 749 750 /* 751 * Enable error interrupts. 752 */ 753 if (pci_error_intr_enable & mask) 754 l |= SCHIZO_PCI_CTRL_ERR_INT_EN; 755 else 756 l &= ~SCHIZO_PCI_CTRL_ERR_INT_EN; 757 758 /* 759 * Enable pci streaming byte errors and error interrupts. 760 */ 761 if (pci_sbh_error_intr_enable & mask) 762 l |= SCHIZO_PCI_CTRL_SBH_INT_EN; 763 else 764 l &= ~SCHIZO_PCI_CTRL_SBH_INT_EN; 765 766 /* 767 * Enable pci discard timeout error interrupt. 768 */ 769 if (pci_mmu_error_intr_enable & mask) 770 l |= SCHIZO_PCI_CTRL_MMU_INT_EN; 771 else 772 l &= ~SCHIZO_PCI_CTRL_MMU_INT_EN; 773 774 /* 775 * Enable PCI-X error interrupts. 776 */ 777 if (CHIP_TYPE(pci_p) == PCI_CHIP_XMITS) { 778 779 if (xmits_error_intr_enable & mask) 780 l |= XMITS_PCI_CTRL_X_ERRINT_EN; 781 else 782 l &= ~XMITS_PCI_CTRL_X_ERRINT_EN; 783 /* 784 * Panic if older XMITS hardware is found. 785 */ 786 if (*pbm_p->pbm_ctrl_reg & XMITS_PCI_CTRL_X_MODE) 787 if (PCI_CHIP_ID(pci_p) <= XMITS_VER_10) 788 cmn_err(CE_PANIC, "%s (%s): PCIX mode " 789 "unsupported on XMITS version %d\n", 790 pbm_p->pbm_nameinst_str, 791 pbm_p->pbm_nameaddr_str, CHIP_VER(pci_p)); 792 793 if (xmits_perr_recov_int_enable) { 794 if (PCI_CHIP_ID(pci_p) >= XMITS_VER_30) { 795 uint64_t pcix_err; 796 /* 797 * Enable interrupt on PERR 798 */ 799 pcix_err = *pbm_p->pbm_pcix_err_stat_reg; 800 pcix_err |= XMITS_PCIX_STAT_PERR_RECOV_INT_EN; 801 pcix_err &= ~XMITS_PCIX_STAT_SERR_ON_PERR; 802 *pbm_p->pbm_pcix_err_stat_reg = pcix_err; 803 } 804 } 805 806 /* 807 * Enable parity error detection on internal memories 808 */ 809 *pbm_p->pbm_pci_ped_ctrl = 0x3fff; 810 } 811 812 /* 813 * Enable/disable bus parking. 814 */ 815 if ((pci_bus_parking_enable & mask) && 816 !ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 817 "no-bus-parking")) 818 l |= SCHIZO_PCI_CTRL_ARB_PARK; 819 else 820 l &= ~SCHIZO_PCI_CTRL_ARB_PARK; 821 822 /* 823 * Enable arbitration. 824 */ 825 l |= PCI_CHIP_ID(pci_p) == XMITS_VER_10 ? XMITS10_PCI_CTRL_ARB_EN_MASK : 826 SCHIZO_PCI_CTRL_ARB_EN_MASK; 827 828 /* 829 * Make sure SERR is clear 830 */ 831 l |= COMMON_PCI_CTRL_SERR; 832 833 834 /* 835 * Enable DTO interrupt, if desired. 836 */ 837 838 if (PCI_CHIP_ID(pci_p) <= TOMATILLO_VER_20 || (pci_dto_intr_enable & 839 mask)) 840 l |= (TOMATILLO_PCI_CTRL_DTO_INT_EN); 841 else 842 l &= ~(TOMATILLO_PCI_CTRL_DTO_INT_EN); 843 844 l |= TOMATILLO_PCI_CTRL_PEN_RD_MLTPL | 845 TOMATILLO_PCI_CTRL_PEN_RD_ONE | 846 TOMATILLO_PCI_CTRL_PEN_RD_LINE; 847 848 /* 849 * Now finally write the control register with the appropriate value. 850 */ 851 DEBUG1(DBG_ATTACH, dip, "pbm_configure: ctrl reg=%llx\n", l); 852 *pbm_p->pbm_ctrl_reg = l; 853 854 /* 855 * Enable IO Prefetch on Tomatillo 856 */ 857 if (CHIP_TYPE(pci_p) == PCI_CHIP_TOMATILLO) { 858 volatile uint64_t *ioc_csr_p = pbm_p->pbm_ctrl_reg + 859 ((TOMATILLO_IOC_CSR_OFF - 860 SCHIZO_PCI_CTRL_REG_OFFSET) >> 3); 861 *ioc_csr_p = TOMATILLO_WRT_PEN | 862 (1 << TOMATILLO_POFFSET_SHIFT) | 863 TOMATILLO_C_PEN_RD_MLTPL | 864 TOMATILLO_C_PEN_RD_ONE | 865 TOMATILLO_C_PEN_RD_LINE; 866 } 867 868 /* 869 * Allow DMA write parity errors to generate an interrupt. 870 * This is implemented on Schizo 2.5 and greater and XMITS 3.0 871 * and greater. Setting this on earlier versions of XMITS 3.0 872 * has no affect. 873 */ 874 if (((CHIP_TYPE(pci_p) == PCI_CHIP_SCHIZO) && 875 PCI_CHIP_ID(pci_p) >= SCHIZO_VER_25) || 876 (CHIP_TYPE(pci_p) == PCI_CHIP_XMITS)) { 877 volatile uint64_t *pbm_icd = pbm_p->pbm_ctrl_reg + 878 ((SCHIZO_PERF_PCI_ICD_OFFSET - 879 SCHIZO_PCI_CTRL_REG_OFFSET) >> 3); 880 881 *pbm_icd |= SCHIZO_PERF_PCI_ICD_DMAW_PARITY_INT_ENABLE; 882 } 883 884 /* 885 * Clear any PBM errors. 886 */ 887 l = (SCHIZO_PCI_AFSR_E_MASK << SCHIZO_PCI_AFSR_PE_SHIFT) | 888 (SCHIZO_PCI_AFSR_E_MASK << SCHIZO_PCI_AFSR_SE_SHIFT); 889 *pbm_p->pbm_async_flt_status_reg = l; 890 891 /* 892 * Allow the diag register to be set based upon variable that 893 * can be configured via /etc/system. 894 */ 895 l = *pbm_p->pbm_diag_reg; 896 DEBUG1(DBG_ATTACH, dip, "pbm_configure: PCI diag reg=%llx\n", l); 897 898 /* 899 * Enable/disable retry limit. 900 */ 901 if (pci_retry_disable & mask) 902 l |= COMMON_PCI_DIAG_DIS_RETRY; 903 else 904 l &= ~COMMON_PCI_DIAG_DIS_RETRY; 905 906 /* 907 * Enable/disable DMA write/interrupt synchronization. 908 */ 909 if (pci_intsync_disable & mask) 910 l |= COMMON_PCI_DIAG_DIS_INTSYNC; 911 else 912 l &= ~COMMON_PCI_DIAG_DIS_INTSYNC; 913 914 /* 915 * Enable/disable retry arbitration priority. 916 */ 917 if (pci_enable_retry_arb & mask) 918 l &= ~SCHIZO_PCI_DIAG_DIS_RTRY_ARB; 919 else 920 l |= SCHIZO_PCI_DIAG_DIS_RTRY_ARB; 921 922 DEBUG1(DBG_ATTACH, dip, "pbm_configure: PCI diag reg=%llx\n", l); 923 *pbm_p->pbm_diag_reg = l; 924 925 /* 926 * Enable SERR# and parity reporting via command register. 927 */ 928 s = pci_perr_enable & mask ? PCI_COMM_PARITY_DETECT : 0; 929 s |= pci_serr_enable & mask ? PCI_COMM_SERR_ENABLE : 0; 930 931 DEBUG1(DBG_ATTACH, dip, "pbm_configure: conf command reg=%x\n", s); 932 pbm_p->pbm_config_header->ch_command_reg = s; 933 934 /* 935 * Clear error bits in configuration status register. 936 */ 937 s = PCI_STAT_PERROR | PCI_STAT_S_PERROR | 938 PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB | 939 PCI_STAT_S_TARG_AB | PCI_STAT_S_PERROR; 940 DEBUG1(DBG_ATTACH, dip, "pbm_configure: conf status reg=%x\n", s); 941 pbm_p->pbm_config_header->ch_status_reg = s; 942 943 /* 944 * The current versions of the obp are suppose to set the latency 945 * timer register but do not. Bug 1234181 is open against this 946 * problem. Until this bug is fixed we check to see if the obp 947 * has attempted to set the latency timer register by checking 948 * for the existence of a "latency-timer" property. 949 */ 950 if (pci_set_latency_timer_register) { 951 DEBUG1(DBG_ATTACH, dip, 952 "pbm_configure: set schizo latency timer to %x\n", 953 pci_latency_timer); 954 pbm_p->pbm_config_header->ch_latency_timer_reg = 955 pci_latency_timer; 956 } 957 958 (void) ndi_prop_update_int(DDI_DEV_T_ANY, dip, "latency-timer", 959 (int)pbm_p->pbm_config_header->ch_latency_timer_reg); 960 961 /* 962 * Adjust xmits_upper_retry_counter if set in /etc/system 963 * 964 * NOTE: current implementation resets UPPR_RTRY counter for 965 * _all_ XMITS' PBMs and does not support tuning per PBM. 966 */ 967 if (CHIP_TYPE(pci_p) == PCI_CHIP_XMITS) { 968 uint_t xurc = xmits_upper_retry_counter & 969 XMITS_UPPER_RETRY_MASK; 970 971 if (xurc) { 972 *pbm_p->pbm_upper_retry_counter_reg = (uint64_t)xurc; 973 DEBUG1(DBG_ATTACH, dip, "pbm_configure: Setting XMITS" 974 " uppr_rtry counter = 0x%lx\n", 975 *pbm_p->pbm_upper_retry_counter_reg); 976 } 977 } 978 } 979 980 uint_t 981 pbm_disable_pci_errors(pbm_t *pbm_p) 982 { 983 pci_t *pci_p = pbm_p->pbm_pci_p; 984 ib_t *ib_p = pci_p->pci_ib_p; 985 986 /* 987 * Disable error and streaming byte hole interrupts via the 988 * PBM control register. 989 */ 990 *pbm_p->pbm_ctrl_reg &= 991 ~(SCHIZO_PCI_CTRL_ERR_INT_EN | SCHIZO_PCI_CTRL_SBH_INT_EN | 992 SCHIZO_PCI_CTRL_MMU_INT_EN); 993 994 /* 995 * Disable error interrupts via the interrupt mapping register. 996 */ 997 ib_intr_disable(ib_p, pci_p->pci_inos[CBNINTR_PBM], IB_INTR_NOWAIT); 998 return (BF_NONE); 999 } 1000 1001 /* 1002 * Layout of the dvma context bucket bitmap entry: 1003 * 1004 * 63 - 56 55 - 0 1005 * 8-bit lock 56-bit, each represent one context 1006 * DCB_LOCK_BITS DCB_BMAP_BITS 1007 */ 1008 #define DCB_LOCK_BITS 8 1009 #define DCB_BMAP_BITS (64 - DCB_LOCK_BITS) 1010 1011 dvma_context_t 1012 pci_iommu_get_dvma_context(iommu_t *iommu_p, dvma_addr_t dvma_pg_index) 1013 { 1014 dvma_context_t ctx; 1015 int i = (dvma_pg_index >> 6) & 0x1f; /* 5 bit index within bucket */ 1016 uint64_t ctx_mask, test = 1ull << i; 1017 uint32_t bucket_no = dvma_pg_index & 0x3f; 1018 uint64_t *bucket_ptr = iommu_p->iommu_ctx_bitmap + bucket_no; 1019 1020 uint32_t spl = ddi_enter_critical(); /* block interrupts */ 1021 if (ldstub((uint8_t *)bucket_ptr)) { /* try lock */ 1022 ddi_exit_critical(spl); /* unblock interrupt */ 1023 pci_iommu_ctx_lock_failure++; 1024 return (0); 1025 } 1026 1027 /* clear lock bits */ 1028 ctx_mask = (*bucket_ptr << DCB_LOCK_BITS) >> DCB_LOCK_BITS; 1029 ASSERT(*bucket_ptr >> DCB_BMAP_BITS == 0xff); 1030 ASSERT(ctx_mask >> DCB_BMAP_BITS == 0); 1031 1032 if (ctx_mask & test) /* quick check i bit */ 1033 for (i = 0, test = 1ull; test & ctx_mask; test <<= 1, i++) 1034 ; 1035 if (i < DCB_BMAP_BITS) 1036 ctx_mask |= test; 1037 *bucket_ptr = ctx_mask; /* unlock */ 1038 ddi_exit_critical(spl); /* unblock interrupts */ 1039 1040 ctx = i < DCB_BMAP_BITS ? (bucket_no << 6) | i : 0; 1041 DEBUG3(DBG_DMA_MAP, iommu_p->iommu_pci_p->pci_dip, 1042 "get_dvma_context: ctx_mask=0x%x.%x ctx=0x%x\n", 1043 (uint32_t)(ctx_mask >> 32), (uint32_t)ctx_mask, ctx); 1044 return (ctx); 1045 } 1046 1047 void 1048 pci_iommu_free_dvma_context(iommu_t *iommu_p, dvma_context_t ctx) 1049 { 1050 uint64_t ctx_mask; 1051 uint32_t spl, bucket_no = ctx >> 6; 1052 int bit_no = ctx & 0x3f; 1053 uint64_t *bucket_ptr = iommu_p->iommu_ctx_bitmap + bucket_no; 1054 1055 DEBUG1(DBG_DMA_MAP, iommu_p->iommu_pci_p->pci_dip, 1056 "free_dvma_context: ctx=0x%x\n", ctx); 1057 1058 spl = ddi_enter_critical(); /* block interrupts */ 1059 while (ldstub((uint8_t *)bucket_ptr)) /* spin lock */ 1060 ; 1061 ctx_mask = (*bucket_ptr << DCB_LOCK_BITS) >> DCB_LOCK_BITS; 1062 /* clear lock bits */ 1063 ASSERT(ctx_mask & (1ull << bit_no)); 1064 *bucket_ptr = ctx_mask ^ (1ull << bit_no); /* clear & unlock */ 1065 ddi_exit_critical(spl); /* unblock interrupt */ 1066 } 1067 1068 int 1069 pci_sc_ctx_inv(dev_info_t *dip, sc_t *sc_p, ddi_dma_impl_t *mp) 1070 { 1071 dvma_context_t ctx = MP2CTX(mp); 1072 volatile uint64_t *reg_addr = sc_p->sc_ctx_match_reg + ctx; 1073 uint64_t matchreg; 1074 1075 if (!*reg_addr) { 1076 DEBUG1(DBG_SC, dip, "ctx=%x no match\n", ctx); 1077 return (DDI_SUCCESS); 1078 } 1079 1080 *sc_p->sc_ctx_invl_reg = ctx; /* 1st flush write */ 1081 matchreg = *reg_addr; /* re-fetch after 1st flush */ 1082 if (!matchreg) 1083 return (DDI_SUCCESS); 1084 1085 matchreg = (matchreg << SC_ENT_SHIFT) >> SC_ENT_SHIFT; /* low 16-bit */ 1086 do { 1087 if (matchreg & 1) 1088 *sc_p->sc_ctx_invl_reg = ctx; 1089 matchreg >>= 1; 1090 } while (matchreg); 1091 1092 if (pci_ctx_no_compat || !*reg_addr) /* compat: active ctx flush */ 1093 return (DDI_SUCCESS); 1094 1095 pci_ctx_unsuccess_count++; 1096 if (pci_ctx_flush_warn) 1097 cmn_err(pci_ctx_flush_warn, "%s%d: ctx flush unsuccessful\n", 1098 NAMEINST(dip)); 1099 return (DDI_FAILURE); 1100 } 1101 1102 void 1103 pci_cb_setup(pci_t *pci_p) 1104 { 1105 dev_info_t *dip = pci_p->pci_dip; 1106 cb_t *cb_p = pci_p->pci_cb_p; 1107 uint64_t pa; 1108 uint32_t chip_id = PCI_CHIP_ID(pci_p); 1109 DEBUG1(DBG_ATTACH, dip, "cb_create: chip id %d\n", chip_id); 1110 1111 if (CHIP_TYPE(pci_p) == PCI_CHIP_TOMATILLO) { 1112 if ((!tm_mtlb_gc_manual) && 1113 (PCI_CHIP_ID(pci_p) <= TOMATILLO_VER_24)) 1114 tm_mtlb_gc = 1; 1115 1116 if (PCI_CHIP_ID(pci_p) <= TOMATILLO_VER_23) { 1117 /* Workaround for the Tomatillo ASIC Erratum #72 */ 1118 ignore_invalid_vecintr = 1; 1119 tomatillo_store_store_wrka = 1; 1120 tomatillo_disallow_bypass = 1; 1121 if (pci_spurintr_msgs == PCI_SPURINTR_MSG_DEFAULT) 1122 pci_spurintr_msgs = 0; 1123 } 1124 } 1125 1126 if (chip_id == TOMATILLO_VER_20 || chip_id == TOMATILLO_VER_21) 1127 cmn_err(CE_WARN, "Unsupported Tomatillo rev (%x)", chip_id); 1128 1129 if (chip_id < SCHIZO_VER_23) 1130 pci_ctx_no_active_flush = 1; 1131 1132 cb_p->cb_node_id = PCI_ID_TO_NODEID(pci_p->pci_id); 1133 cb_p->cb_ign = PCI_ID_TO_IGN(pci_p->pci_id); 1134 1135 /* 1136 * schizo control status reg bank is on the 2nd "reg" property entry 1137 * interrupt mapping/clear/state regs are on the 1st "reg" entry. 1138 * 1139 * ALL internal interrupts except pbm interrupts are shared by both 1140 * sides, 1st-side-attached is used as *the* owner. 1141 */ 1142 pa = (uint64_t)hat_getpfnum(kas.a_hat, pci_p->pci_address[1]); 1143 cb_p->cb_base_pa = pa << MMU_PAGESHIFT; 1144 1145 pa = pci_p->pci_address[3] ? 1146 (uint64_t)hat_getpfnum(kas.a_hat, pci_p->pci_address[3]) : 0; 1147 cb_p->cb_icbase_pa = (pa == PFN_INVALID) ? 0 : pa << MMU_PAGESHIFT; 1148 1149 pa = (uint64_t)hat_getpfnum(kas.a_hat, pci_p->pci_address[0]) 1150 << MMU_PAGESHIFT; 1151 cb_p->cb_map_pa = pa + SCHIZO_IB_INTR_MAP_REG_OFFSET; 1152 cb_p->cb_clr_pa = pa + SCHIZO_IB_CLEAR_INTR_REG_OFFSET; 1153 cb_p->cb_obsta_pa = pa + COMMON_IB_OBIO_INTR_STATE_DIAG_REG; 1154 } 1155 1156 void 1157 pci_ecc_setup(ecc_t *ecc_p) 1158 { 1159 ecc_p->ecc_ue.ecc_errpndg_mask = SCHIZO_ECC_UE_AFSR_ERRPNDG; 1160 ecc_p->ecc_ue.ecc_offset_mask = SCHIZO_ECC_UE_AFSR_QW_OFFSET; 1161 ecc_p->ecc_ue.ecc_offset_shift = SCHIZO_ECC_UE_AFSR_QW_OFFSET_SHIFT; 1162 ecc_p->ecc_ue.ecc_size_log2 = 4; 1163 1164 ecc_p->ecc_ce.ecc_errpndg_mask = SCHIZO_ECC_CE_AFSR_ERRPNDG; 1165 ecc_p->ecc_ce.ecc_offset_mask = SCHIZO_ECC_CE_AFSR_QW_OFFSET; 1166 ecc_p->ecc_ce.ecc_offset_shift = SCHIZO_ECC_CE_AFSR_QW_OFFSET_SHIFT; 1167 ecc_p->ecc_ce.ecc_size_log2 = 4; 1168 } 1169 1170 ushort_t 1171 pci_ecc_get_synd(uint64_t afsr) 1172 { 1173 return ((ushort_t)((afsr & SCHIZO_ECC_CE_AFSR_SYND) >> 1174 SCHIZO_ECC_CE_AFSR_SYND_SHIFT)); 1175 } 1176 1177 /* 1178 * overwrite dvma end address (only on virtual-dma systems) 1179 * initialize tsb size 1180 * reset context bits 1181 * return: IOMMU CSR bank base address (VA) 1182 */ 1183 1184 uintptr_t 1185 pci_iommu_setup(iommu_t *iommu_p) 1186 { 1187 pci_dvma_range_prop_t *dvma_prop; 1188 int dvma_prop_len; 1189 1190 uintptr_t a; 1191 pci_t *pci_p = iommu_p->iommu_pci_p; 1192 dev_info_t *dip = pci_p->pci_dip; 1193 uint_t tsb_size = iommu_tsb_cookie_to_size(pci_p->pci_tsb_cookie); 1194 uint_t tsb_size_prop; 1195 1196 /* 1197 * Initializations for Tomatillo's micro TLB bug. errata #82 1198 */ 1199 if (tm_mtlb_gc) { 1200 iommu_p->iommu_mtlb_nreq = 0; 1201 iommu_p->iommu_mtlb_npgs = 0; 1202 iommu_p->iommu_mtlb_maxpgs = tm_mtlb_maxpgs; 1203 iommu_p->iommu_mtlb_req_p = (dvma_unbind_req_t *) 1204 kmem_zalloc(sizeof (dvma_unbind_req_t) * 1205 (tm_mtlb_maxpgs + 1), KM_SLEEP); 1206 mutex_init(&iommu_p->iommu_mtlb_lock, NULL, MUTEX_DRIVER, NULL); 1207 } 1208 1209 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1210 "virtual-dma", (caddr_t)&dvma_prop, &dvma_prop_len) != 1211 DDI_PROP_SUCCESS) 1212 goto tsb_done; 1213 1214 if (dvma_prop_len != sizeof (pci_dvma_range_prop_t)) { 1215 cmn_err(CE_WARN, "%s%d: invalid virtual-dma property", 1216 ddi_driver_name(dip), ddi_get_instance(dip)); 1217 goto tsb_end; 1218 } 1219 iommu_p->iommu_dvma_end = dvma_prop->dvma_base + 1220 (dvma_prop->dvma_len - 1); 1221 tsb_size_prop = IOMMU_BTOP(dvma_prop->dvma_len) * sizeof (uint64_t); 1222 tsb_size = MIN(tsb_size_prop, tsb_size); 1223 tsb_end: 1224 kmem_free(dvma_prop, dvma_prop_len); 1225 tsb_done: 1226 iommu_p->iommu_tsb_size = iommu_tsb_size_encode(tsb_size); 1227 iommu_p->iommu_ctx_bitmap = 1228 kmem_zalloc(IOMMU_CTX_BITMAP_SIZE, KM_SLEEP); 1229 *iommu_p->iommu_ctx_bitmap = 1ull; /* reserve context 0 */ 1230 1231 /* 1232 * Determine the virtual address of the register block 1233 * containing the iommu control registers and determine 1234 * the virtual address of schizo specific iommu registers. 1235 */ 1236 a = (uintptr_t)pci_p->pci_address[0]; 1237 iommu_p->iommu_flush_ctx_reg = 1238 (uint64_t *)(a + SCHIZO_IOMMU_FLUSH_CTX_REG_OFFSET); 1239 if (CHIP_TYPE(pci_p) == PCI_CHIP_TOMATILLO) 1240 iommu_p->iommu_tfar_reg = 1241 (uint64_t *)(a + TOMATILLO_IOMMU_ERR_TFAR_OFFSET); 1242 return (a); /* PCICSRBase */ 1243 } 1244 1245 void 1246 pci_iommu_teardown(iommu_t *iommu_p) 1247 { 1248 if (pci_use_contexts) 1249 iommu_ctx_free(iommu_p); 1250 if (iommu_p->iommu_mtlb_req_p) { 1251 kmem_free(iommu_p->iommu_mtlb_req_p, 1252 sizeof (dvma_unbind_req_t) * (tm_mtlb_maxpgs + 1)); 1253 mutex_destroy(&iommu_p->iommu_mtlb_lock); 1254 iommu_p->iommu_mtlb_req_p = NULL; 1255 iommu_p->iommu_mtlb_nreq = 0; 1256 iommu_p->iommu_mtlb_npgs = iommu_p->iommu_mtlb_maxpgs = 0; 1257 } 1258 } 1259 1260 uintptr_t 1261 get_pbm_reg_base(pci_t *pci_p) 1262 { 1263 return ((uintptr_t) 1264 (pci_p->pci_address[0] + SCHIZO_PCI_CTRL_REG_OFFSET)); 1265 } 1266 1267 /* ARGSUSED */ 1268 static boolean_t 1269 pci_pbm_panic_callb(void *arg, int code) 1270 { 1271 pbm_t *pbm_p = (pbm_t *)arg; 1272 volatile uint64_t *ctrl_reg_p; 1273 1274 if (pbm_p->pbm_quiesce_count > 0) { 1275 ctrl_reg_p = pbm_p->pbm_ctrl_reg; 1276 *ctrl_reg_p = pbm_p->pbm_saved_ctrl_reg; 1277 } 1278 1279 return (B_TRUE); 1280 } 1281 1282 static boolean_t 1283 pci_pbm_debug_callb(void *arg, int code) 1284 { 1285 pbm_t *pbm_p = (pbm_t *)arg; 1286 volatile uint64_t *ctrl_reg_p; 1287 uint64_t ctrl_reg; 1288 1289 if (pbm_p->pbm_quiesce_count > 0) { 1290 ctrl_reg_p = pbm_p->pbm_ctrl_reg; 1291 if (code == 0) { 1292 *ctrl_reg_p = pbm_p->pbm_saved_ctrl_reg; 1293 } else { 1294 ctrl_reg = pbm_p->pbm_saved_ctrl_reg; 1295 ctrl_reg &= ~(SCHIZO_PCI_CTRL_ARB_EN_MASK | 1296 SCHIZO_PCI_CTRL_ARB_PARK); 1297 *ctrl_reg_p = ctrl_reg; 1298 } 1299 } 1300 1301 return (B_TRUE); 1302 } 1303 1304 void 1305 pci_pbm_setup(pbm_t *pbm_p) 1306 { 1307 pci_t *pci_p = pbm_p->pbm_pci_p; 1308 caddr_t a = pci_p->pci_address[0]; /* PBM block base VA */ 1309 uint64_t pa = va_to_pa(a); 1310 extern int segkmem_reloc; 1311 1312 mutex_init(&pbm_p->pbm_sync_mutex, NULL, MUTEX_DRIVER, 1313 (void *)ipltospl(XCALL_PIL)); 1314 1315 pbm_p->pbm_config_header = (config_header_t *)pci_p->pci_address[2]; 1316 pbm_p->pbm_ctrl_reg = (uint64_t *)(a + SCHIZO_PCI_CTRL_REG_OFFSET); 1317 pbm_p->pbm_diag_reg = (uint64_t *)(a + SCHIZO_PCI_DIAG_REG_OFFSET); 1318 pbm_p->pbm_async_flt_status_reg = 1319 (uint64_t *)(a + SCHIZO_PCI_ASYNC_FLT_STATUS_REG_OFFSET); 1320 pbm_p->pbm_async_flt_addr_reg = 1321 (uint64_t *)(a + SCHIZO_PCI_ASYNC_FLT_ADDR_REG_OFFSET); 1322 pbm_p->pbm_estar_reg = (uint64_t *)(a + SCHIZO_PCI_ESTAR_REG_OFFSET); 1323 pbm_p->pbm_pcix_err_stat_reg = (uint64_t *)(a + 1324 XMITS_PCI_X_ERROR_STATUS_REG_OFFSET); 1325 pbm_p->pbm_pci_ped_ctrl = (uint64_t *)(a + 1326 XMITS_PARITY_DETECT_REG_OFFSET); 1327 1328 /* 1329 * Create a property to indicate that this node supports DVMA 1330 * page relocation. 1331 */ 1332 if (CHIP_TYPE(pci_p) != PCI_CHIP_TOMATILLO && segkmem_reloc != 0) { 1333 pci_dvma_remap_enabled = 1; 1334 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, 1335 pci_p->pci_dip, "dvma-remap-supported"); 1336 } 1337 1338 /* 1339 * Register a panic callback so we can unquiesce this bus 1340 * if it has been placed in the quiesced state. 1341 */ 1342 pbm_p->pbm_panic_cb_id = callb_add(pci_pbm_panic_callb, 1343 (void *)pbm_p, CB_CL_PANIC, "pci_panic"); 1344 pbm_p->pbm_debug_cb_id = callb_add(pci_pbm_panic_callb, 1345 (void *)pbm_p, CB_CL_ENTER_DEBUGGER, "pci_debug_enter"); 1346 1347 if (CHIP_TYPE(pci_p) != PCI_CHIP_SCHIZO) 1348 goto non_schizo; 1349 1350 if (PCI_CHIP_ID(pci_p) >= SCHIZO_VER_23) { 1351 1352 pbm_p->pbm_sync_reg_pa = pa + SCHIZO_PBM_DMA_SYNC_REG_OFFSET; 1353 1354 /* 1355 * This is a software workaround to fix schizo hardware bug. 1356 * Create a boolean property and its existence means consistent 1357 * dma sync should not be done while in prom. The usb polled 1358 * code (OHCI,EHCI) will check for this property and will not 1359 * do dma sync if this property exist. 1360 */ 1361 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, 1362 pci_p->pci_dip, "no-prom-cdma-sync"); 1363 } 1364 return; 1365 non_schizo: 1366 if (CHIP_TYPE(pci_p) == PCI_CHIP_TOMATILLO) { 1367 pci_dvma_sync_before_unmap = 1; 1368 pa = pci_p->pci_cb_p->cb_icbase_pa; 1369 } 1370 if (CHIP_TYPE(pci_p) == PCI_CHIP_XMITS) 1371 pbm_p->pbm_upper_retry_counter_reg = 1372 (uint64_t *)(a + XMITS_UPPER_RETRY_COUNTER_REG_OFFSET); 1373 1374 pbm_p->pbm_sync_reg_pa = pa + PBM_DMA_SYNC_PEND_REG_OFFSET; 1375 } 1376 1377 void 1378 pci_pbm_teardown(pbm_t *pbm_p) 1379 { 1380 (void) callb_delete(pbm_p->pbm_panic_cb_id); 1381 (void) callb_delete(pbm_p->pbm_debug_cb_id); 1382 } 1383 1384 uintptr_t 1385 pci_ib_setup(ib_t *ib_p) 1386 { 1387 /* 1388 * Determine virtual addresses of bridge specific registers, 1389 */ 1390 pci_t *pci_p = ib_p->ib_pci_p; 1391 uintptr_t a = (uintptr_t)pci_p->pci_address[0]; 1392 1393 ib_p->ib_ign = PCI_ID_TO_IGN(pci_p->pci_id); 1394 ib_p->ib_max_ino = SCHIZO_MAX_INO; 1395 ib_p->ib_slot_intr_map_regs = a + SCHIZO_IB_SLOT_INTR_MAP_REG_OFFSET; 1396 ib_p->ib_intr_map_regs = a + SCHIZO_IB_INTR_MAP_REG_OFFSET; 1397 ib_p->ib_slot_clear_intr_regs = a + SCHIZO_IB_CLEAR_INTR_REG_OFFSET; 1398 return (a); 1399 } 1400 1401 void 1402 pci_sc_setup(sc_t *sc_p) 1403 { 1404 pci_t *pci_p = sc_p->sc_pci_p; 1405 uintptr_t a; 1406 1407 /* 1408 * Determine the virtual addresses of the stream cache 1409 * control/status and flush registers. 1410 */ 1411 a = (uintptr_t)pci_p->pci_address[0]; /* PCICSRBase */ 1412 sc_p->sc_ctrl_reg = (uint64_t *)(a + SCHIZO_SC_CTRL_REG_OFFSET); 1413 sc_p->sc_invl_reg = (uint64_t *)(a + SCHIZO_SC_INVL_REG_OFFSET); 1414 sc_p->sc_sync_reg = (uint64_t *)(a + SCHIZO_SC_SYNC_REG_OFFSET); 1415 sc_p->sc_ctx_invl_reg = (uint64_t *)(a + SCHIZO_SC_CTX_INVL_REG_OFFSET); 1416 sc_p->sc_ctx_match_reg = 1417 (uint64_t *)(a + SCHIZO_SC_CTX_MATCH_REG_OFFSET); 1418 1419 /* 1420 * Determine the virtual addresses of the streaming cache 1421 * diagnostic access registers. 1422 */ 1423 sc_p->sc_data_diag_acc = (uint64_t *)(a + SCHIZO_SC_DATA_DIAG_OFFSET); 1424 sc_p->sc_tag_diag_acc = (uint64_t *)(a + SCHIZO_SC_TAG_DIAG_OFFSET); 1425 sc_p->sc_ltag_diag_acc = (uint64_t *)(a + SCHIZO_SC_LTAG_DIAG_OFFSET); 1426 } 1427 1428 /*ARGSUSED*/ 1429 int 1430 pci_get_numproxy(dev_info_t *dip) 1431 { 1432 /* 1433 * Schizo does not support interrupt proxies. 1434 */ 1435 return (0); 1436 } 1437 1438 /* 1439 * pcisch error handling 101: 1440 * 1441 * The various functions below are responsible for error handling. Given 1442 * a particular error, they must gather the appropriate state, report all 1443 * errors with correct payload, and attempt recovery where ever possible. 1444 * 1445 * Recovery in the context of this driver is being able notify a leaf device 1446 * of the failed transaction. This leaf device may either be the master or 1447 * target for this transaction and may have already received an error 1448 * notification via a PCI interrupt. Notification is done via DMA and access 1449 * handles. If we capture an address for the transaction then we can map it 1450 * to a handle(if the leaf device is fma-compliant) and fault the handle as 1451 * well as call the device driver registered callback. 1452 * 1453 * The hardware can either interrupt or trap upon detection of an error, in 1454 * some rare cases it also causes a fatal reset. 1455 * 1456 * cb_buserr_intr() is responsible for handling control block 1457 * errors(errors which stem from the host bus side of the bridge). Since 1458 * we support multiple chips and host bus standards, cb_buserr_intr will 1459 * call a bus specific error handler to report and handle the detected 1460 * error. Since this error can either affect or orginate from either of the 1461 * two PCI busses which are connected to the bridge, we need to call 1462 * pci_pbm_err_handler() for each bus as well to report their errors. We 1463 * also need to gather possible errors which have been detected by their 1464 * compliant children(via ndi_fm_handler_dispatch()). 1465 * 1466 * pbm_error_intr() and ecc_intr() are responsible for PCI Block Module 1467 * errors(generic PCI + bridge specific) and ECC errors, respectively. They 1468 * are common between pcisch and pcipsy and therefore exist in pci_pbm.c and 1469 * pci_ecc.c. To support error handling certain chip specific handlers 1470 * must exist and they are defined below. 1471 * 1472 * cpu_deferred_error() and cpu_async_error(), handle the traps that may 1473 * have originated from IO space. They call into the registered IO callbacks 1474 * to report and handle errors that may have caused the trap. 1475 * 1476 * pci_pbm_err_handler() is called by pbm_error_intr() or pci_err_callback() 1477 * (generic fma callback for pcipsy/pcisch, pci_fm.c). pci_err_callback() is 1478 * called when the CPU has trapped because of a possible IO error(TO/BERR/UE). 1479 * It will call pci_pbm_err_handler() to report and handle all PCI/PBM/IOMMU 1480 * related errors which are detected by the chip. 1481 * 1482 * pci_pbm_err_handler() calls a generic interface pbm_afsr_report()(pci_pbm.c) 1483 * to report the pbm specific errors and attempt to map the failed address 1484 * (if captured) to a device instance. pbm_afsr_report() calls a chip specific 1485 * interface to interpret the afsr bits pci_pbm_classify()(pcisch.c/pcipsy.c). 1486 * pci_pbm_err_handler() also calls iommu_err_handler() to handle IOMMU related 1487 * errors. 1488 * 1489 * iommu_err_handler() can recover from most errors, as long as the requesting 1490 * device is notified and the iommu can be flushed. If an IOMMU error occurs 1491 * due to a UE then it will be passed on to the ecc_err_handler() for 1492 * subsequent handling. 1493 * 1494 * ecc_err_handler()(pci_ecc.c) also calls a chip specific interface to 1495 * interpret the afsr, pci_ecc_classify(). ecc_err_handler() also calls 1496 * pci_pbm_err_handler() to report any pbm errors detected. 1497 * 1498 * To make sure that the trap code and the interrupt code are not going 1499 * to step on each others toes we have a per chip pci_fm_mutex. This also 1500 * makes it necessary for us to be caution while we are at a high PIL, so 1501 * that we do not cause a subsequent trap that causes us to hang. 1502 * 1503 * The attempt to commonize code was meant to keep in line with the current 1504 * pci driver implementation and it was not meant to confuse. If you are 1505 * confused then don't worry, I was too. 1506 * 1507 */ 1508 static void 1509 pci_cb_errstate_get(cb_t *cb_p, cb_errstate_t *cb_err_p) 1510 { 1511 uint64_t pa = cb_p->cb_base_pa; 1512 int i; 1513 1514 bzero(cb_err_p, sizeof (cb_errstate_t)); 1515 1516 ASSERT(MUTEX_HELD(&cb_p->cb_pci_cmn_p->pci_fm_mutex)); 1517 1518 cb_err_p->cb_bridge_type = PCI_BRIDGE_TYPE(cb_p->cb_pci_cmn_p); 1519 1520 cb_err_p->cb_csr = lddphysio(pa + SCHIZO_CB_CSR_OFFSET); 1521 cb_err_p->cb_err = lddphysio(pa + SCHIZO_CB_ERRCTRL_OFFSET); 1522 cb_err_p->cb_intr = lddphysio(pa + SCHIZO_CB_INTCTRL_OFFSET); 1523 cb_err_p->cb_elog = lddphysio(pa + SCHIZO_CB_ERRLOG_OFFSET); 1524 cb_err_p->cb_ecc = lddphysio(pa + SCHIZO_CB_ECCCTRL_OFFSET); 1525 cb_err_p->cb_ue_afsr = lddphysio(pa + SCHIZO_CB_UEAFSR_OFFSET); 1526 cb_err_p->cb_ue_afar = lddphysio(pa + SCHIZO_CB_UEAFAR_OFFSET); 1527 cb_err_p->cb_ce_afsr = lddphysio(pa + SCHIZO_CB_CEAFSR_OFFSET); 1528 cb_err_p->cb_ce_afar = lddphysio(pa + SCHIZO_CB_CEAFAR_OFFSET); 1529 1530 if ((CB_CHIP_TYPE((cb_t *)cb_p)) == PCI_CHIP_XMITS) { 1531 cb_err_p->cb_first_elog = lddphysio(pa + 1532 XMITS_CB_FIRST_ERROR_LOG); 1533 cb_err_p->cb_first_eaddr = lddphysio(pa + 1534 XMITS_CB_FIRST_ERROR_ADDR); 1535 cb_err_p->cb_leaf_status = lddphysio(pa + 1536 XMITS_CB_FIRST_ERROR_ADDR); 1537 } 1538 1539 /* Gather PBM state information for both sides of this chip */ 1540 for (i = 0; i < 2; i++) { 1541 if (cb_p->cb_pci_cmn_p->pci_p[i] == NULL) 1542 continue; 1543 pci_pbm_errstate_get(((cb_t *)cb_p)->cb_pci_cmn_p-> 1544 pci_p[i], &cb_err_p->cb_pbm[i]); 1545 } 1546 } 1547 1548 static void 1549 pci_cb_clear_error(cb_t *cb_p, cb_errstate_t *cb_err_p) 1550 { 1551 uint64_t pa = ((cb_t *)cb_p)->cb_base_pa; 1552 1553 stdphysio(pa + SCHIZO_CB_ERRLOG_OFFSET, cb_err_p->cb_elog); 1554 } 1555 1556 static cb_fm_err_t safari_err_tbl[] = { 1557 SAFARI_BAD_CMD, SCHIZO_CB_ELOG_BAD_CMD, CB_FATAL, 1558 SAFARI_SSM_DIS, SCHIZO_CB_ELOG_SSM_DIS, CB_FATAL, 1559 SAFARI_BAD_CMD_PCIA, SCHIZO_CB_ELOG_BAD_CMD_PCIA, CB_FATAL, 1560 SAFARI_BAD_CMD_PCIB, SCHIZO_CB_ELOG_BAD_CMD_PCIB, CB_FATAL, 1561 SAFARI_PAR_ERR_INT_PCIB, XMITS_CB_ELOG_PAR_ERR_INT_PCIB, CB_FATAL, 1562 SAFARI_PAR_ERR_INT_PCIA, XMITS_CB_ELOG_PAR_ERR_INT_PCIA, CB_FATAL, 1563 SAFARI_PAR_ERR_INT_SAF, XMITS_CB_ELOG_PAR_ERR_INT_SAF, CB_FATAL, 1564 SAFARI_PLL_ERR_PCIB, XMITS_CB_ELOG_PLL_ERR_PCIB, CB_FATAL, 1565 SAFARI_PLL_ERR_PCIA, XMITS_CB_ELOG_PLL_ERR_PCIA, CB_FATAL, 1566 SAFARI_PLL_ERR_SAF, XMITS_CB_ELOG_PLL_ERR_SAF, CB_FATAL, 1567 SAFARI_SAF_CIQ_TO, SCHIZO_CB_ELOG_SAF_CIQ_TO, CB_FATAL, 1568 SAFARI_SAF_LPQ_TO, SCHIZO_CB_ELOG_SAF_LPQ_TO, CB_FATAL, 1569 SAFARI_SAF_SFPQ_TO, SCHIZO_CB_ELOG_SAF_SFPQ_TO, CB_FATAL, 1570 SAFARI_APERR, SCHIZO_CB_ELOG_ADDR_PAR_ERR, CB_FATAL, 1571 SAFARI_UNMAP_ERR, SCHIZO_CB_ELOG_UNMAP_ERR, CB_FATAL, 1572 SAFARI_BUS_ERR, SCHIZO_CB_ELOG_BUS_ERR, CB_FATAL, 1573 SAFARI_TO_ERR, SCHIZO_CB_ELOG_TO_ERR, CB_FATAL, 1574 SAFARI_DSTAT_ERR, SCHIZO_CB_ELOG_DSTAT_ERR, CB_FATAL, 1575 SAFARI_SAF_UFPQ_TO, SCHIZO_CB_ELOG_SAF_UFPQ_TO, CB_FATAL, 1576 SAFARI_CPU0_PAR_SINGLE, SCHIZO_CB_ELOG_CPU0_PAR_SINGLE, CB_FATAL, 1577 SAFARI_CPU0_PAR_BIDI, SCHIZO_CB_ELOG_CPU0_PAR_BIDI, CB_FATAL, 1578 SAFARI_CPU1_PAR_SINGLE, SCHIZO_CB_ELOG_CPU1_PAR_SINGLE, CB_FATAL, 1579 SAFARI_CPU1_PAR_BIDI, SCHIZO_CB_ELOG_CPU1_PAR_BIDI, CB_FATAL, 1580 NULL, NULL, NULL, 1581 }; 1582 1583 /* 1584 * Function used to handle and log Safari bus errors. 1585 */ 1586 static int 1587 safari_err_handler(dev_info_t *dip, uint64_t fme_ena, 1588 cb_errstate_t *cb_err_p) 1589 { 1590 int i; 1591 int fatal = 0; 1592 pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 1593 pci_common_t *cmn_p = pci_p->pci_common_p; 1594 1595 ASSERT(MUTEX_HELD(&cmn_p->pci_fm_mutex)); 1596 1597 for (i = 0; safari_err_tbl[i].cb_err_class != NULL; i++) { 1598 if (cb_err_p->cb_elog & safari_err_tbl[i].cb_reg_bit) { 1599 cb_err_p->cb_err_class = safari_err_tbl[i].cb_err_class; 1600 cb_ereport_post(dip, fme_ena, cb_err_p); 1601 fatal += safari_err_tbl[i].cb_fatal; 1602 } 1603 } 1604 1605 if (fatal) 1606 return (DDI_FM_FATAL); 1607 return (DDI_FM_OK); 1608 1609 } 1610 1611 /* 1612 * Check pbm va log register for captured errant address, and fail handle 1613 * if in per device cache. 1614 * Called from jbus_err_handler. 1615 */ 1616 static int 1617 jbus_check_va_log(cb_t *cb_p, uint64_t fme_ena, 1618 cb_errstate_t *cb_err_p) 1619 { 1620 int i; 1621 int ret = DDI_FM_FATAL; 1622 pci_common_t *cmn_p = cb_p->cb_pci_cmn_p; 1623 1624 ASSERT(MUTEX_HELD(&cmn_p->pci_fm_mutex)); 1625 /* 1626 * Check VA log register for address associated with error, 1627 * if no address is registered then return failure 1628 */ 1629 for (i = 0; i < 2; i++) { 1630 1631 if (cb_p->cb_pci_cmn_p->pci_p[i] == NULL) 1632 continue; 1633 /* 1634 * Look up and fault handle associated with 1635 * logged DMA address 1636 */ 1637 if (cb_err_p->cb_pbm[i].pbm_va_log) { 1638 void *addr = (void *)&cb_err_p->cb_pbm[i].pbm_va_log; 1639 ret = ndi_fmc_error(cb_p->cb_pci_cmn_p->pci_p[i]-> 1640 pci_dip, NULL, DMA_HANDLE, fme_ena, 1641 (void *)addr); 1642 if (ret == DDI_FM_NONFATAL) 1643 break; 1644 } 1645 } 1646 return (ret); 1647 } 1648 1649 static cb_fm_err_t jbus_err_tbl[] = { 1650 JBUS_APERR, SCHIZO_CB_ELOG_ADDR_PAR_ERR, CB_FATAL, 1651 JBUS_PWR_DATA_PERR, TOMATILLO_CB_ELOG_WR_DATA_PAR_ERR, CB_FATAL, 1652 JBUS_DRD_DATA_PERR, TOMATILLO_CB_ELOG_RD_DATA_PAR_ERR, CB_NONFATAL, 1653 JBUS_CTL_PERR, TOMATILLO_CB_ELOG_CTL_PAR_ERR, CB_FATAL, 1654 JBUS_ILL_BYTE_EN, TOMATILLO_CB_ELOG_ILL_BYTE_EN, CB_FATAL, 1655 JBUS_ILL_COH_IN, TOMATILLO_CB_ELOG_ILL_COH_IN, CB_FATAL, 1656 JBUS_SNOOP_ERR_RD, TOMATILLO_CB_ELOG_SNOOP_ERR_RD, CB_FATAL, 1657 JBUS_SNOOP_ERR_RDS, TOMATILLO_CB_ELOG_SNOOP_ERR_RDS, CB_FATAL, 1658 JBUS_SNOOP_ERR_RDSA, TOMATILLO_CB_ELOG_SNOOP_ERR_RDSA, CB_FATAL, 1659 JBUS_SNOOP_ERR_OWN, TOMATILLO_CB_ELOG_SNOOP_ERR_OWN, CB_FATAL, 1660 JBUS_SNOOP_ERR_RDO, TOMATILLO_CB_ELOG_SNOOP_ERR_RDO, CB_FATAL, 1661 JBUS_SNOOP_ERR_PCI, TOMATILLO_CB_ELOG_SNOOP_ERR_PCI, CB_FATAL, 1662 JBUS_SNOOP_ERR_GR, TOMATILLO_CB_ELOG_SNOOP_ERR_GR, CB_FATAL, 1663 JBUS_SNOOP_ERR, TOMATILLO_CB_ELOG_SNOOP_ERR, CB_FATAL, 1664 JBUS_BAD_CMD, SCHIZO_CB_ELOG_BAD_CMD, CB_FATAL, 1665 JBUS_UNMAP_ERR, SCHIZO_CB_ELOG_UNMAP_ERR, CB_NONFATAL, 1666 JBUS_TO_EXP_ERR, TOMATILLO_CB_ELOG_TO_EXP_ERR, CB_NONFATAL, 1667 JBUS_TO_ERR, SCHIZO_CB_ELOG_TO_ERR, CB_NONFATAL, 1668 JBUS_BUS_ERR, SCHIZO_CB_ELOG_BUS_ERR, CB_NONFATAL, 1669 NULL, NULL, NULL, 1670 }; 1671 1672 /* 1673 * Function used to handle and log Jbus errors. 1674 */ 1675 static int 1676 jbus_err_handler(dev_info_t *dip, uint64_t fme_ena, 1677 cb_errstate_t *cb_err_p) 1678 { 1679 int fatal = 0; 1680 int nonfatal = 0; 1681 int i; 1682 pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 1683 cb_t *cb_p = pci_p->pci_cb_p; 1684 1685 ASSERT(MUTEX_HELD(&pci_p->pci_common_p->pci_fm_mutex)); 1686 1687 for (i = 0; jbus_err_tbl[i].cb_err_class != NULL; i++) { 1688 if (!(cb_err_p->cb_elog & jbus_err_tbl[i].cb_reg_bit)) 1689 continue; 1690 cb_err_p->cb_err_class = jbus_err_tbl[i].cb_err_class; 1691 if (jbus_err_tbl[i].cb_fatal) { 1692 fatal += jbus_err_tbl[i].cb_fatal; 1693 continue; 1694 } 1695 if (jbus_check_va_log(cb_p, fme_ena, cb_err_p) 1696 != DDI_FM_NONFATAL) { 1697 fatal++; 1698 } 1699 cb_ereport_post(dip, fme_ena, cb_err_p); 1700 } 1701 1702 return (fatal ? DDI_FM_FATAL : (nonfatal ? DDI_FM_NONFATAL : 1703 DDI_FM_OK)); 1704 } 1705 1706 /* 1707 * Control Block error interrupt handler. 1708 */ 1709 uint_t 1710 cb_buserr_intr(caddr_t a) 1711 { 1712 cb_t *cb_p = (cb_t *)a; 1713 pci_common_t *cmn_p = cb_p->cb_pci_cmn_p; 1714 pci_t *pci_p = cmn_p->pci_p[0]; 1715 cb_errstate_t cb_err; 1716 ddi_fm_error_t derr; 1717 int ret = DDI_FM_FATAL; 1718 int i; 1719 1720 if (pci_p == NULL) 1721 pci_p = cmn_p->pci_p[1]; 1722 1723 bzero(&derr, sizeof (ddi_fm_error_t)); 1724 derr.fme_version = DDI_FME_VERSION; 1725 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 1726 1727 mutex_enter(&cmn_p->pci_fm_mutex); 1728 1729 pci_cb_errstate_get(cb_p, &cb_err); 1730 1731 if (CB_CHIP_TYPE(cb_p) == PCI_CHIP_TOMATILLO) 1732 ret = jbus_err_handler(pci_p->pci_dip, derr.fme_ena, &cb_err); 1733 else if ((CB_CHIP_TYPE(cb_p) == PCI_CHIP_SCHIZO) || 1734 (CB_CHIP_TYPE(cb_p) == PCI_CHIP_XMITS)) 1735 ret = safari_err_handler(pci_p->pci_dip, derr.fme_ena, &cb_err); 1736 1737 /* 1738 * Check for related errors in PBM and IOMMU. The IOMMU could cause 1739 * a timeout on the jbus due to an IOMMU miss, so we need to check and 1740 * log the IOMMU error registers. 1741 */ 1742 for (i = 0; i < 2; i++) { 1743 if (cmn_p->pci_p[i] == NULL) 1744 continue; 1745 if (pci_pbm_err_handler(cmn_p->pci_p[i]->pci_dip, &derr, 1746 (void *)cmn_p->pci_p[i], PCI_CB_CALL) == DDI_FM_FATAL) 1747 ret = DDI_FM_FATAL; 1748 } 1749 1750 /* Cleanup and reset error bits */ 1751 (void) pci_cb_clear_error(cb_p, &cb_err); 1752 mutex_exit(&cmn_p->pci_fm_mutex); 1753 1754 if (ret == DDI_FM_FATAL) { 1755 fm_panic("Fatal System Bus Error has occurred\n"); 1756 } 1757 1758 return (DDI_INTR_CLAIMED); 1759 } 1760 1761 static ecc_fm_err_t ecc_err_tbl[] = { 1762 PCI_ECC_PIO_UE, COMMON_ECC_AFSR_E_PIO, CBNINTR_UE, 1763 PBM_PRIMARY, SCHIZO_ECC_AFAR_PIOW_UPA64S, SCH_REG_UPA, 1764 ACC_HANDLE, 1765 1766 PCI_ECC_PIO_UE, COMMON_ECC_AFSR_E_PIO, CBNINTR_UE, 1767 PBM_PRIMARY, SCHIZO_ECC_AFAR_PIOW_PCIA_REG, SCH_REG_PCIA_REG, 1768 ACC_HANDLE, 1769 1770 PCI_ECC_PIO_UE, COMMON_ECC_AFSR_E_PIO, CBNINTR_UE, 1771 PBM_PRIMARY, SCHIZO_ECC_AFAR_PIOW_PCIA_MEM, SCH_REG_PCIA_MEM, 1772 ACC_HANDLE, 1773 1774 PCI_ECC_PIO_UE, COMMON_ECC_AFSR_E_PIO, CBNINTR_UE, 1775 PBM_PRIMARY, SCHIZO_ECC_AFAR_PIOW_PCIA_CFGIO, SCH_REG_PCIA_CFGIO, 1776 ACC_HANDLE, 1777 1778 PCI_ECC_PIO_UE, COMMON_ECC_AFSR_E_PIO, CBNINTR_UE, 1779 PBM_PRIMARY, SCHIZO_ECC_AFAR_PIOW_PCIB_REG, SCH_REG_PCIB_REG, 1780 ACC_HANDLE, 1781 1782 PCI_ECC_PIO_UE, COMMON_ECC_AFSR_E_PIO, CBNINTR_UE, 1783 PBM_PRIMARY, SCHIZO_ECC_AFAR_PIOW_PCIB_MEM, SCH_REG_PCIB_MEM, 1784 ACC_HANDLE, 1785 1786 PCI_ECC_PIO_UE, COMMON_ECC_AFSR_E_PIO, CBNINTR_UE, 1787 PBM_PRIMARY, SCHIZO_ECC_AFAR_PIOW_PCIB_CFGIO, SCH_REG_PCIB_CFGIO, 1788 ACC_HANDLE, 1789 1790 PCI_ECC_PIO_UE, COMMON_ECC_AFSR_E_PIO, CBNINTR_UE, 1791 PBM_PRIMARY, SCHIZO_ECC_AFAR_PIOW_SAFARI_REGS, SCH_REG_SAFARI_REGS, 1792 ACC_HANDLE, 1793 1794 PCI_ECC_SEC_PIO_UE, COMMON_ECC_AFSR_E_PIO, CBNINTR_UE, 1795 PBM_SECONDARY, NULL, NULL, ACC_HANDLE, 1796 1797 PCI_ECC_PIO_CE, COMMON_ECC_AFSR_E_PIO, CBNINTR_CE, 1798 PBM_PRIMARY, NULL, NULL, ACC_HANDLE, 1799 1800 PCI_ECC_SEC_PIO_CE, COMMON_ECC_AFSR_E_PIO, CBNINTR_CE, 1801 PBM_SECONDARY, NULL, NULL, ACC_HANDLE, 1802 1803 PCI_ECC_DRD_UE, COMMON_ECC_AFSR_E_DRD, CBNINTR_UE, 1804 PBM_PRIMARY, NULL, NULL, DMA_HANDLE, 1805 1806 PCI_ECC_SEC_DRD_UE, COMMON_ECC_AFSR_E_DRD, CBNINTR_UE, 1807 PBM_SECONDARY, NULL, NULL, DMA_HANDLE, 1808 1809 PCI_ECC_DRD_CE, COMMON_ECC_AFSR_E_DRD, CBNINTR_CE, 1810 PBM_PRIMARY, NULL, NULL, DMA_HANDLE, 1811 1812 PCI_ECC_SEC_DRD_CE, COMMON_ECC_AFSR_E_DRD, CBNINTR_CE, 1813 PBM_SECONDARY, NULL, NULL, DMA_HANDLE, 1814 1815 PCI_ECC_DWR_UE, COMMON_ECC_AFSR_E_DWR, CBNINTR_UE, 1816 PBM_PRIMARY, NULL, NULL, DMA_HANDLE, 1817 1818 PCI_ECC_SEC_DWR_UE, COMMON_ECC_AFSR_E_DWR, CBNINTR_UE, 1819 PBM_SECONDARY, NULL, NULL, DMA_HANDLE, 1820 1821 PCI_ECC_DWR_CE, COMMON_ECC_AFSR_E_DWR, CBNINTR_CE, 1822 PBM_PRIMARY, NULL, NULL, DMA_HANDLE, 1823 1824 PCI_ECC_SEC_DWR_CE, COMMON_ECC_AFSR_E_DWR, CBNINTR_CE, 1825 PBM_SECONDARY, NULL, NULL, DMA_HANDLE, 1826 1827 NULL, NULL, NULL, NULL, NULL, NULL, 1828 }; 1829 1830 /* 1831 * pci_ecc_classify, called by ecc_handler to classify ecc errors 1832 * and determine if we should panic or not. 1833 */ 1834 void 1835 pci_ecc_classify(uint64_t err, ecc_errstate_t *ecc_err_p) 1836 { 1837 struct async_flt *ecc_p = &ecc_err_p->ecc_aflt; 1838 uint64_t region, afar = ecc_p->flt_addr; 1839 int i, j, ret = 0; 1840 int flag, fatal = 0; 1841 pci_common_t *cmn_p = ecc_err_p->ecc_ii_p.ecc_p->ecc_pci_cmn_p; 1842 pci_t *pci_p = cmn_p->pci_p[0]; 1843 1844 ASSERT(MUTEX_HELD(&cmn_p->pci_fm_mutex)); 1845 1846 ecc_err_p->ecc_bridge_type = PCI_BRIDGE_TYPE(cmn_p); 1847 1848 if (pci_p == NULL) 1849 pci_p = cmn_p->pci_p[1]; 1850 1851 ecc_err_p->ecc_ctrl = lddphysio(ecc_err_p->ecc_ii_p.ecc_p->ecc_csr_pa); 1852 ecc_err_p->ecc_err_addr = afar; 1853 region = afar & SCHIZO_ECC_AFAR_PIOW_MASK; 1854 1855 for (i = 0; ecc_err_tbl[i].ecc_err_class != NULL; i++) { 1856 if (!(err & ecc_err_tbl[i].ecc_reg_bit) || 1857 (ecc_err_p->ecc_ii_p.ecc_type != 1858 ecc_err_tbl[i].ecc_type) || 1859 (ecc_err_p->ecc_pri != ecc_err_tbl[i].ecc_pri)) 1860 continue; 1861 1862 ecc_p->flt_erpt_class = ecc_err_tbl[i].ecc_err_class; 1863 flag = ecc_err_tbl[i].ecc_flag; 1864 1865 if (!ecc_err_tbl[i].ecc_pri || 1866 (ecc_err_tbl[i].ecc_type == CBNINTR_CE)) { 1867 fatal += (ecc_err_tbl[i].ecc_type == CBNINTR_UE) ? 1868 1 : 0; 1869 break; 1870 } 1871 1872 if (flag == ACC_HANDLE && 1873 (region & ecc_err_tbl[i].ecc_region_bits)) { 1874 ecc_err_p->ecc_region = ecc_err_tbl[i].ecc_region; 1875 pci_format_ecc_addr(pci_p->pci_dip, 1876 &ecc_err_p->ecc_err_addr, 1877 ecc_err_p->ecc_region); 1878 } 1879 1880 /* 1881 * Lookup and fault errant handle 1882 */ 1883 for (j = 0; j < 2; ++j) { 1884 ret = DDI_FM_UNKNOWN; 1885 if (cmn_p->pci_p[j] == NULL) 1886 continue; 1887 ret = ndi_fmc_error(cmn_p->pci_p[j]->pci_dip, NULL, 1888 flag, ecc_err_p->ecc_ena, 1889 (void *)&ecc_err_p->ecc_err_addr); 1890 if (ret == DDI_FM_NONFATAL) { 1891 fatal = 0; 1892 break; 1893 } else 1894 fatal++; 1895 } 1896 break; 1897 } 1898 1899 if (fatal) 1900 ecc_p->flt_panic = 1; 1901 else if (flag != ACC_HANDLE) 1902 ecc_err_p->ecc_pg_ret = 1; 1903 } 1904 1905 /* 1906 * Tables to define PCI-X Split Completion errors 1907 */ 1908 1909 pcix_err_msg_rec_t pcix_completer_errs[] = { 1910 {PCIX_CPLT_OUT_OF_RANGE, "pcix", "oor" }, 1911 }; 1912 1913 pcix_err_tbl_t pcix_split_errs_tbl[] = { 1914 {PCIX_CLASS_CPLT, 1915 sizeof (pcix_completer_errs)/sizeof (pcix_err_msg_rec_t), 1916 pcix_completer_errs }, 1917 }; 1918 1919 /* 1920 * Tables for the PCI-X error status messages 1921 */ 1922 pcix_err_msg_rec_t pcix_stat_errs[] = { 1923 {XMITS_PCIX_STAT_SC_DSCRD, "pcix", "discard" }, 1924 {XMITS_PCIX_STAT_SC_TTO, "xmits.pbmx", "tato" }, 1925 {XMITS_PCIX_STAT_SMMU, "xmits.pbmx", "stmmu" }, 1926 {XMITS_PCIX_STAT_SDSTAT, "xmits.pbmx", "stdst" }, 1927 {XMITS_PCIX_STAT_CMMU, "xmits.pbmx", "cnmmu" }, 1928 {XMITS_PCIX_STAT_CDSTAT, "xmits.pbmx", "cndst" } 1929 }; 1930 1931 pcix_err_tbl_t pcix_stat_errs_tbl = 1932 {PCIX_NO_CLASS, 1933 sizeof (pcix_stat_errs)/sizeof (pcix_err_msg_rec_t), 1934 pcix_stat_errs }; 1935 1936 1937 /* 1938 * walk thru a table of error messages, printing as appropriate 1939 * 1940 * t - the table of messages to parse 1941 * err - the error to match against 1942 * multi - flag, sometimes multiple error bits may be set/desired 1943 */ 1944 static int 1945 pcix_lookup_err_msgs(dev_info_t *dip, uint64_t ena, pcix_err_tbl_t t, 1946 pbm_errstate_t *pbm_err_p) 1947 { 1948 uint32_t err_bits = pbm_err_p->pbm_err & XMITS_PCIX_MSG_INDEX_MASK; 1949 int nerr = 0; 1950 int j; 1951 char buf[FM_MAX_CLASS]; 1952 1953 for (j = 0; j < t.err_rec_num; j++) { 1954 uint32_t msg_key = t.err_msg_tbl[j].msg_key; 1955 if (pbm_err_p->pbm_multi ? !(err_bits & msg_key) : err_bits 1956 != msg_key) 1957 continue; 1958 1959 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s%s", 1960 t.err_msg_tbl[j].msg_class, 1961 pbm_err_p->pbm_pri ? "" : PCIX_SECONDARY, 1962 t.err_msg_tbl[j].msg_str); 1963 1964 pbm_err_p->pbm_err_class = buf; 1965 pcix_ereport_post(dip, ena, pbm_err_p); 1966 nerr++; 1967 } 1968 return (nerr ? DDI_FM_FATAL : DDI_FM_OK); 1969 } 1970 1971 /* 1972 * Decodes primary(bit 27-24) or secondary(bit 15-12) PCI-X split 1973 * completion error message class and index in PBM AFSR. 1974 */ 1975 static void 1976 pcix_log_split_err(dev_info_t *dip, uint64_t ena, pbm_errstate_t *pbm_err_p) 1977 { 1978 uint32_t class = pbm_err_p->pbm_err & XMITS_PCIX_MSG_CLASS_MASK; 1979 uint32_t num_classes = sizeof (pcix_split_errs_tbl) / 1980 sizeof (struct pcix_err_tbl); 1981 int i; 1982 1983 for (i = 0; i < num_classes; i++) { 1984 if (class == pcix_split_errs_tbl[i].err_class) { 1985 pbm_err_p->pbm_multi = PCIX_SINGLE_ERR; 1986 (void) pcix_lookup_err_msgs(dip, ena, 1987 pcix_split_errs_tbl[i], pbm_err_p); 1988 break; 1989 } 1990 } 1991 } 1992 1993 /* 1994 * Report PBM PCI-X Error Status Register if in PCI-X mode 1995 * 1996 * Once a PCI-X fault tree is constructed, the code below may need to 1997 * change. 1998 */ 1999 static int 2000 pcix_log_pbm(pci_t *pci_p, uint64_t ena, pbm_errstate_t *pbm_err_p) 2001 { 2002 int fatal = 0; 2003 int nonfatal = 0; 2004 uint32_t e; 2005 2006 ASSERT(MUTEX_HELD(&pci_p->pci_common_p->pci_fm_mutex)); 2007 2008 DEBUG3(DBG_ERR_INTR, pci_p->pci_dip, "pcix_log_pbm: chip_type=%d " 2009 "ctr_stat=%lx afsr = 0x%lx", CHIP_TYPE(pci_p), 2010 pbm_err_p->pbm_ctl_stat, pbm_err_p->pbm_afsr); 2011 2012 if (!(CHIP_TYPE(pci_p) == PCI_CHIP_XMITS) || 2013 !(pbm_err_p->pbm_ctl_stat & XMITS_PCI_CTRL_X_MODE)) 2014 return (DDI_FM_OK); 2015 2016 if (pbm_err_p->pbm_afsr & XMITS_PCI_X_AFSR_P_SC_ERR) { 2017 pbm_err_p->pbm_err = PBM_AFSR_TO_PRISPLIT(pbm_err_p->pbm_afsr); 2018 pbm_err_p->pbm_pri = PBM_PRIMARY; 2019 pcix_log_split_err(pci_p->pci_dip, ena, pbm_err_p); 2020 nonfatal++; 2021 } 2022 if (pbm_err_p->pbm_afsr & XMITS_PCI_X_AFSR_S_SC_ERR) { 2023 pbm_err_p->pbm_err = PBM_AFSR_TO_PRISPLIT(pbm_err_p->pbm_afsr); 2024 pbm_err_p->pbm_pri = PBM_PRIMARY; 2025 pcix_log_split_err(pci_p->pci_dip, ena, pbm_err_p); 2026 nonfatal++; 2027 } 2028 2029 e = PBM_PCIX_TO_PRIERR(pbm_err_p->pbm_pcix_stat); 2030 if (e) { 2031 pbm_err_p->pbm_pri = PBM_PRIMARY; 2032 pbm_err_p->pbm_err = e; 2033 pbm_err_p->pbm_multi = PCIX_MULTI_ERR; 2034 if (pcix_lookup_err_msgs(pci_p->pci_dip, ena, 2035 pcix_stat_errs_tbl, pbm_err_p) == DDI_FM_FATAL) 2036 fatal++; 2037 else 2038 nonfatal++; 2039 } 2040 2041 e = PBM_PCIX_TO_SECERR(pbm_err_p->pbm_pcix_stat); 2042 if (e) { 2043 pbm_err_p->pbm_pri = PBM_SECONDARY; 2044 pbm_err_p->pbm_err = e; 2045 pbm_err_p->pbm_multi = PCIX_MULTI_ERR; 2046 if (pcix_lookup_err_msgs(pci_p->pci_dip, ena, 2047 pcix_stat_errs_tbl, pbm_err_p) == DDI_FM_FATAL) 2048 fatal++; 2049 else 2050 nonfatal++; 2051 } 2052 2053 if (!fatal && !nonfatal) 2054 return (DDI_FM_OK); 2055 else if (fatal) 2056 return (DDI_FM_FATAL); 2057 return (DDI_FM_NONFATAL); 2058 } 2059 2060 static pbm_fm_err_t pbm_err_tbl[] = { 2061 PCI_MA, SCHIZO_PCI_AFSR_E_MA, PBM_PRIMARY, 2062 FM_LOG_PCI, PCI_TARG_MA, 2063 2064 PCI_SEC_MA, SCHIZO_PCI_AFSR_E_MA, PBM_SECONDARY, 2065 FM_LOG_PBM, NULL, 2066 2067 PCI_REC_TA, SCHIZO_PCI_AFSR_E_TA, PBM_PRIMARY, 2068 FM_LOG_PCI, PCI_TARG_REC_TA, 2069 2070 PCI_SEC_REC_TA, SCHIZO_PCI_AFSR_E_TA, PBM_SECONDARY, 2071 FM_LOG_PBM, NULL, 2072 2073 PCI_PBM_RETRY, SCHIZO_PCI_AFSR_E_RTRY, PBM_PRIMARY, 2074 FM_LOG_PBM, PCI_PBM_TARG_RETRY, 2075 2076 PCI_SEC_PBM_RETRY, SCHIZO_PCI_AFSR_E_RTRY, PBM_SECONDARY, 2077 FM_LOG_PBM, NULL, 2078 2079 PCI_MDPE, SCHIZO_PCI_AFSR_E_PERR, PBM_PRIMARY, 2080 FM_LOG_PCI, PCI_TARG_MDPE, 2081 2082 PCI_SEC_MDPE, SCHIZO_PCI_AFSR_E_PERR, PBM_SECONDARY, 2083 FM_LOG_PBM, NULL, 2084 2085 PCI_PBM_TTO, SCHIZO_PCI_AFSR_E_TTO, PBM_PRIMARY, 2086 FM_LOG_PBM, PCI_PBM_TARG_TTO, 2087 2088 PCI_SEC_PBM_TTO, SCHIZO_PCI_AFSR_E_TTO, PBM_SECONDARY, 2089 FM_LOG_PBM, NULL, 2090 2091 PCI_SCH_BUS_UNUSABLE_ERR, SCHIZO_PCI_AFSR_E_UNUSABLE, PBM_PRIMARY, 2092 FM_LOG_PBM, NULL, 2093 2094 PCI_SEC_SCH_BUS_UNUSABLE_ERR, SCHIZO_PCI_AFSR_E_UNUSABLE, PBM_SECONDARY, 2095 FM_LOG_PBM, NULL, 2096 2097 NULL, NULL, NULL, 2098 NULL, NULL, 2099 }; 2100 2101 2102 /* 2103 * pci_pbm_classify, called by pbm_afsr_report to classify piow afsr. 2104 */ 2105 int 2106 pci_pbm_classify(pbm_errstate_t *pbm_err_p) 2107 { 2108 uint32_t err; 2109 int nerr = 0; 2110 int i; 2111 2112 err = pbm_err_p->pbm_pri ? PBM_AFSR_TO_PRIERR(pbm_err_p->pbm_afsr): 2113 PBM_AFSR_TO_SECERR(pbm_err_p->pbm_afsr); 2114 2115 for (i = 0; pbm_err_tbl[i].pbm_err_class != NULL; i++) { 2116 if ((err & pbm_err_tbl[i].pbm_reg_bit) && 2117 (pbm_err_p->pbm_pri == pbm_err_tbl[i].pbm_pri)) { 2118 if (pbm_err_tbl[i].pbm_flag == FM_LOG_PCI) 2119 pbm_err_p->pbm_pci.pci_err_class = 2120 pbm_err_tbl[i].pbm_err_class; 2121 else 2122 pbm_err_p->pbm_err_class = 2123 pbm_err_tbl[i].pbm_err_class; 2124 2125 pbm_err_p->pbm_terr_class = 2126 pbm_err_tbl[i].pbm_terr_class; 2127 pbm_err_p->pbm_log = pbm_err_tbl[i].pbm_flag; 2128 nerr++; 2129 break; 2130 } 2131 } 2132 2133 return (nerr); 2134 } 2135 2136 /* 2137 * Function used to handle and log IOMMU errors. Called by pci_pbm_err_handler, 2138 * with pci_fm_mutex held. 2139 */ 2140 static int 2141 iommu_err_handler(dev_info_t *dip, uint64_t ena, pbm_errstate_t *pbm_err_p) 2142 { 2143 pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 2144 iommu_t *iommu_p = pci_p->pci_iommu_p; 2145 ecc_t *ecc_p = pci_p->pci_ecc_p; 2146 uint64_t stat; 2147 ushort_t ta_signalled; 2148 int err = 0; 2149 int fatal = 0; 2150 int nonfatal = 0; 2151 int ret; 2152 2153 ASSERT(MUTEX_HELD(&ecc_p->ecc_pci_cmn_p->pci_fm_mutex)); 2154 if (!((stat = *iommu_p->iommu_ctrl_reg) & TOMATILLO_IOMMU_ERR)) { 2155 pbm_err_p->pbm_err_class = PCI_SCH_MMU_ERR; 2156 iommu_ereport_post(dip, ena, pbm_err_p); 2157 return (DDI_FM_NONFATAL); 2158 } 2159 2160 /* 2161 * Need to make sure a Target Abort was signalled to the device if 2162 * we have any hope of recovering. Tomatillo does not send a TA for 2163 * DMA Writes that result in a Translation Error, thus fooling the 2164 * device into believing everything is as it expects. Ignorance 2165 * is bliss, but knowledge is power. 2166 */ 2167 ta_signalled = pbm_err_p->pbm_pci.pci_cfg_stat & 2168 PCI_STAT_S_TARG_AB; 2169 2170 if (stat & TOMATILLO_IOMMU_ERR_ILLTSBTBW) { 2171 pbm_err_p->pbm_err_class = PCI_TOM_MMU_BAD_TSBTBW; 2172 err = 1; 2173 iommu_ereport_post(dip, ena, pbm_err_p); 2174 if (!ta_signalled) 2175 fatal++; 2176 else 2177 nonfatal++; 2178 } 2179 2180 if (stat & TOMATILLO_IOMMU_ERR_BAD_VA) { 2181 pbm_err_p->pbm_err_class = PCI_TOM_MMU_BAD_VA; 2182 err = 1; 2183 iommu_ereport_post(dip, ena, pbm_err_p); 2184 if (!ta_signalled) 2185 fatal++; 2186 else 2187 nonfatal++; 2188 } 2189 2190 if (!err) { 2191 stat = ((stat & TOMATILLO_IOMMU_ERRSTS) >> 2192 TOMATILLO_IOMMU_ERRSTS_SHIFT); 2193 switch (stat) { 2194 case TOMATILLO_IOMMU_PROTECTION_ERR: 2195 pbm_err_p->pbm_err_class = PCI_TOM_MMU_PROT_ERR; 2196 iommu_ereport_post(dip, ena, pbm_err_p); 2197 fatal++; 2198 break; 2199 case TOMATILLO_IOMMU_INVALID_ERR: 2200 pbm_err_p->pbm_err_class = PCI_TOM_MMU_INVAL_ERR; 2201 /* 2202 * Fault the address in iommu_tfar 2203 * register to inform target driver of error 2204 */ 2205 ret = ndi_fmc_error(pci_p->pci_dip, NULL, DMA_HANDLE, 2206 ena, (void *)&pbm_err_p->pbm_iommu.iommu_tfar); 2207 2208 if (ret != DDI_FM_NONFATAL) 2209 if (ta_signalled) 2210 nonfatal++; 2211 else 2212 fatal++; 2213 else 2214 nonfatal++; 2215 2216 iommu_ereport_post(dip, ena, pbm_err_p); 2217 break; 2218 case TOMATILLO_IOMMU_TIMEOUT_ERR: 2219 pbm_err_p->pbm_err_class = PCI_TOM_MMU_TO_ERR; 2220 fatal++; 2221 iommu_ereport_post(dip, ena, pbm_err_p); 2222 break; 2223 case TOMATILLO_IOMMU_ECC_ERR: 2224 pbm_err_p->pbm_err_class = PCI_TOM_MMU_UE; 2225 iommu_ereport_post(dip, ena, pbm_err_p); 2226 break; 2227 } 2228 } 2229 2230 if (fatal) 2231 return (DDI_FM_FATAL); 2232 else if (nonfatal) 2233 return (DDI_FM_NONFATAL); 2234 2235 return (DDI_FM_OK); 2236 } 2237 2238 int 2239 pci_check_error(pci_t *pci_p) 2240 { 2241 pbm_t *pbm_p = pci_p->pci_pbm_p; 2242 uint16_t pci_cfg_stat; 2243 uint64_t pbm_ctl_stat, pbm_afsr, pbm_pcix_stat; 2244 caddr_t a = pci_p->pci_address[0]; 2245 uint64_t *pbm_pcix_stat_reg; 2246 2247 ASSERT(MUTEX_HELD(&pci_p->pci_common_p->pci_fm_mutex)); 2248 2249 pci_cfg_stat = pbm_p->pbm_config_header->ch_status_reg; 2250 pbm_ctl_stat = *pbm_p->pbm_ctrl_reg; 2251 pbm_afsr = *pbm_p->pbm_async_flt_status_reg; 2252 2253 if ((pci_cfg_stat & (PCI_STAT_S_PERROR | PCI_STAT_S_TARG_AB | 2254 PCI_STAT_R_TARG_AB | PCI_STAT_R_MAST_AB | 2255 PCI_STAT_S_SYSERR | PCI_STAT_PERROR)) || 2256 (pbm_ctl_stat & (SCHIZO_PCI_CTRL_BUS_UNUSABLE | 2257 TOMATILLO_PCI_CTRL_PCI_DTO_ERR | 2258 SCHIZO_PCI_CTRL_PCI_TTO_ERR | 2259 SCHIZO_PCI_CTRL_PCI_RTRY_ERR | 2260 SCHIZO_PCI_CTRL_PCI_MMU_ERR | 2261 COMMON_PCI_CTRL_SBH_ERR | 2262 COMMON_PCI_CTRL_SERR)) || 2263 (PBM_AFSR_TO_PRIERR(pbm_afsr))) 2264 return (1); 2265 2266 if ((CHIP_TYPE(pci_p) == PCI_CHIP_XMITS) && 2267 (pbm_ctl_stat & XMITS_PCI_CTRL_X_MODE)) { 2268 2269 pbm_pcix_stat_reg = (uint64_t *)(a + 2270 XMITS_PCI_X_ERROR_STATUS_REG_OFFSET); 2271 2272 pbm_pcix_stat = *pbm_pcix_stat_reg; 2273 2274 if (PBM_PCIX_TO_PRIERR(pbm_pcix_stat)) 2275 return (1); 2276 2277 if (pbm_pcix_stat & XMITS_PCIX_STAT_PERR_RECOV_INT) 2278 return (1); 2279 } 2280 2281 return (0); 2282 2283 } 2284 2285 static pbm_fm_err_t pci_pbm_err_tbl[] = { 2286 PCI_PBM_RETRY, SCHIZO_PCI_CTRL_PCI_RTRY_ERR, 2287 NULL, PBM_NONFATAL, PCI_PBM_TARG_RETRY, 2288 2289 PCI_PBM_TTO, SCHIZO_PCI_CTRL_PCI_TTO_ERR, 2290 NULL, PBM_NONFATAL, PCI_PBM_TARG_TTO, 2291 2292 PCI_SCH_BUS_UNUSABLE_ERR, SCHIZO_PCI_CTRL_BUS_UNUSABLE, 2293 NULL, PBM_NONFATAL, NULL, 2294 2295 NULL, NULL, 2296 NULL, NULL, NULL 2297 }; 2298 2299 /* 2300 * Function used to log all PCI/PBM/IOMMU errors found in the system. 2301 * It is called by the pbm_error_intr as well as the pci_err_callback(trap 2302 * callback). To protect access we hold the pci_fm_mutex when calling 2303 * this function. 2304 */ 2305 int 2306 pci_pbm_err_handler(dev_info_t *dip, ddi_fm_error_t *derr, 2307 const void *impl_data, int caller) 2308 { 2309 int fatal = 0; 2310 int nonfatal = 0; 2311 int unknown = 0; 2312 uint32_t prierr, secerr; 2313 pbm_errstate_t pbm_err; 2314 char buf[FM_MAX_CLASS]; 2315 pci_t *pci_p = (pci_t *)impl_data; 2316 pbm_t *pbm_p = pci_p->pci_pbm_p; 2317 int i, ret = 0; 2318 2319 ASSERT(MUTEX_HELD(&pci_p->pci_common_p->pci_fm_mutex)); 2320 pci_pbm_errstate_get(pci_p, &pbm_err); 2321 2322 derr->fme_ena = derr->fme_ena ? derr->fme_ena : 2323 fm_ena_generate(0, FM_ENA_FMT1); 2324 2325 prierr = PBM_AFSR_TO_PRIERR(pbm_err.pbm_afsr); 2326 secerr = PBM_AFSR_TO_SECERR(pbm_err.pbm_afsr); 2327 2328 if (derr->fme_flag == DDI_FM_ERR_EXPECTED) { 2329 if (caller == PCI_TRAP_CALL) { 2330 /* 2331 * For ddi_caut_get treat all events as nonfatal. 2332 * The trampoline will set err_ena = 0, err_status = 2333 * NONFATAL. We only really call this function so that 2334 * pci_clear_error() and ndi_fm_handler_dispatch() will 2335 * get called. 2336 */ 2337 derr->fme_status = DDI_FM_NONFATAL; 2338 nonfatal++; 2339 goto done; 2340 } else { 2341 /* 2342 * For ddi_caut_put treat all events as nonfatal. Here 2343 * we have the handle and can call ndi_fm_acc_err_set(). 2344 */ 2345 derr->fme_status = DDI_FM_NONFATAL; 2346 ndi_fm_acc_err_set(pbm_p->pbm_excl_handle, derr); 2347 nonfatal++; 2348 goto done; 2349 } 2350 } else if (derr->fme_flag == DDI_FM_ERR_PEEK) { 2351 /* 2352 * For ddi_peek treat all events as nonfatal. We only 2353 * really call this function so that pci_clear_error() 2354 * and ndi_fm_handler_dispatch() will get called. 2355 */ 2356 nonfatal++; 2357 goto done; 2358 } else if (derr->fme_flag == DDI_FM_ERR_POKE) { 2359 /* 2360 * For ddi_poke we can treat as nonfatal if the 2361 * following conditions are met : 2362 * 1. Make sure only primary error is MA/TA 2363 * 2. Make sure no secondary error bits set 2364 * 3. check pci config header stat reg to see MA/TA is 2365 * logged. We cannot verify only MA/TA is recorded 2366 * since it gets much more complicated when a 2367 * PCI-to-PCI bridge is present. 2368 */ 2369 if ((prierr == SCHIZO_PCI_AFSR_E_MA) && !secerr && 2370 (pbm_err.pbm_pci.pci_cfg_stat & PCI_STAT_R_MAST_AB)) { 2371 nonfatal++; 2372 goto done; 2373 } else if ((*pbm_p->pbm_ctrl_reg & XMITS_PCI_CTRL_X_MODE) && 2374 pcix_ma_behind_bridge(&pbm_err)) { 2375 /* 2376 * MAs behind a PCI-X bridge get sent back to 2377 * the host as a Split Completion Error Message. 2378 * We handle this the same as the above check. 2379 */ 2380 nonfatal++; 2381 goto done; 2382 } 2383 if ((prierr == SCHIZO_PCI_AFSR_E_TA) && !secerr && 2384 (pbm_err.pbm_pci.pci_cfg_stat & PCI_STAT_R_TARG_AB)) { 2385 nonfatal++; 2386 goto done; 2387 } 2388 } 2389 2390 DEBUG2(DBG_ERR_INTR, dip, "pci_pbm_err_handler: prierr=0x%x " 2391 "secerr=0x%x", prierr, secerr); 2392 2393 if (prierr || secerr) { 2394 ret = pbm_afsr_report(dip, derr->fme_ena, &pbm_err); 2395 if (ret == DDI_FM_FATAL) 2396 fatal++; 2397 else 2398 nonfatal++; 2399 } 2400 if ((ret = pcix_log_pbm(pci_p, derr->fme_ena, &pbm_err)) 2401 == DDI_FM_FATAL) 2402 fatal++; 2403 else if (ret == DDI_FM_NONFATAL) 2404 nonfatal++; 2405 2406 if ((ret = pci_cfg_report(dip, derr, &pbm_err.pbm_pci, caller, prierr)) 2407 == DDI_FM_FATAL) 2408 fatal++; 2409 else if (ret == DDI_FM_NONFATAL) 2410 nonfatal++; 2411 2412 for (i = 0; pci_pbm_err_tbl[i].pbm_err_class != NULL; i++) { 2413 if ((pbm_err.pbm_ctl_stat & pci_pbm_err_tbl[i].pbm_reg_bit) && 2414 !prierr) { 2415 pbm_err.pbm_err_class = 2416 pci_pbm_err_tbl[i].pbm_err_class; 2417 pbm_ereport_post(dip, derr->fme_ena, &pbm_err); 2418 if (pci_pbm_err_tbl[i].pbm_flag) 2419 fatal++; 2420 else 2421 nonfatal++; 2422 if (caller == PCI_TRAP_CALL && 2423 pci_pbm_err_tbl[i].pbm_terr_class) 2424 pci_target_enqueue(derr->fme_ena, 2425 pci_pbm_err_tbl[i].pbm_terr_class, 2426 pbm_err.pbm_bridge_type, 2427 (uint64_t)derr->fme_bus_specific); 2428 } 2429 } 2430 2431 if ((pbm_err.pbm_ctl_stat & COMMON_PCI_CTRL_SBH_ERR) && 2432 (CHIP_TYPE(pci_p) != PCI_CHIP_TOMATILLO)) { 2433 pbm_err.pbm_err_class = PCI_SCH_SBH; 2434 pbm_ereport_post(dip, derr->fme_ena, &pbm_err); 2435 if (pci_panic_on_sbh_errors) 2436 fatal++; 2437 else 2438 nonfatal++; 2439 } 2440 2441 /* 2442 * PBM Received System Error - During any transaction, or 2443 * at any point on the bus, some device may detect a critical 2444 * error and signal a system error to the system. 2445 */ 2446 if (pbm_err.pbm_ctl_stat & COMMON_PCI_CTRL_SERR) { 2447 /* 2448 * may be expected (master abort from pci-pci bridge during 2449 * poke will generate SERR) 2450 */ 2451 if (derr->fme_flag != DDI_FM_ERR_POKE) { 2452 DEBUG1(DBG_ERR_INTR, dip, "pci_pbm_err_handler: " 2453 "ereport_post: %s", buf); 2454 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", 2455 PCI_ERROR_SUBCLASS, PCI_REC_SERR); 2456 ddi_fm_ereport_post(dip, buf, derr->fme_ena, 2457 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 2458 PCI_CONFIG_STATUS, DATA_TYPE_UINT16, 2459 pbm_err.pbm_pci.pci_cfg_stat, PCI_CONFIG_COMMAND, 2460 DATA_TYPE_UINT16, pbm_err.pbm_pci.pci_cfg_comm, 2461 PCI_PA, DATA_TYPE_UINT64, (uint64_t)0, NULL); 2462 } 2463 unknown++; 2464 } 2465 2466 /* 2467 * PCI Retry Timeout - Device fails to retry deferred 2468 * transaction within timeout. Only Tomatillo 2469 */ 2470 if (pbm_err.pbm_ctl_stat & TOMATILLO_PCI_CTRL_PCI_DTO_ERR) { 2471 if (pci_dto_fault_warn == CE_PANIC) 2472 fatal++; 2473 else 2474 nonfatal++; 2475 2476 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", 2477 PCI_ERROR_SUBCLASS, PCI_DTO); 2478 ddi_fm_ereport_post(dip, buf, derr->fme_ena, DDI_NOSLEEP, 2479 FM_VERSION, DATA_TYPE_UINT8, 0, 2480 PCI_CONFIG_STATUS, DATA_TYPE_UINT16, 2481 pbm_err.pbm_pci.pci_cfg_stat, 2482 PCI_CONFIG_COMMAND, DATA_TYPE_UINT16, 2483 pbm_err.pbm_pci.pci_cfg_comm, 2484 PCI_PA, DATA_TYPE_UINT64, (uint64_t)0, NULL); 2485 } 2486 2487 /* 2488 * PBM Detected Data Parity Error - DPE detected during a DMA Write 2489 * or PIO Read. Later case is taken care of by cpu_deferred_error 2490 * and sent here to be logged. 2491 */ 2492 if ((pbm_err.pbm_pci.pci_cfg_stat & PCI_STAT_PERROR) && 2493 !(pbm_err.pbm_pci.pci_cfg_stat & PCI_STAT_S_SYSERR)) { 2494 /* 2495 * If we have an address then fault 2496 * it, if not probe for errant device 2497 */ 2498 ret = DDI_FM_FATAL; 2499 if (caller != PCI_TRAP_CALL) { 2500 if (pbm_err.pbm_va_log) { 2501 ret = ndi_fmc_error(dip, NULL, DMA_HANDLE, 2502 derr->fme_ena, (void *)&pbm_err.pbm_va_log); 2503 } 2504 if (ret == DDI_FM_NONFATAL) 2505 nonfatal++; 2506 else 2507 fatal++; 2508 } else 2509 nonfatal++; 2510 2511 } 2512 2513 /* PBM Detected IOMMU Error */ 2514 if (pbm_err.pbm_ctl_stat & SCHIZO_PCI_CTRL_PCI_MMU_ERR) { 2515 if (iommu_err_handler(dip, derr->fme_ena, &pbm_err) 2516 == DDI_FM_FATAL) 2517 fatal++; 2518 else 2519 nonfatal++; 2520 } 2521 2522 done: 2523 ret = ndi_fm_handler_dispatch(dip, NULL, derr); 2524 if (ret == DDI_FM_FATAL) { 2525 fatal++; 2526 } else if (ret == DDI_FM_NONFATAL) { 2527 nonfatal++; 2528 } else if (ret == DDI_FM_UNKNOWN) { 2529 unknown++; 2530 } 2531 2532 /* 2533 * RSERR not claimed as nonfatal by a child is considered fatal 2534 */ 2535 if (unknown && !fatal && !nonfatal) 2536 fatal++; 2537 2538 /* Cleanup and reset error bits */ 2539 pci_clear_error(pci_p, &pbm_err); 2540 2541 return (fatal ? DDI_FM_FATAL : (nonfatal ? DDI_FM_NONFATAL : 2542 (unknown ? DDI_FM_UNKNOWN : DDI_FM_OK))); 2543 } 2544 2545 /* 2546 * Function returns TRUE if a Primary error is Split Completion Error 2547 * that indicates a Master Abort occured behind a PCI-X bridge. 2548 * This function should only be called for busses running in PCI-X mode. 2549 */ 2550 static int 2551 pcix_ma_behind_bridge(pbm_errstate_t *pbm_err_p) 2552 { 2553 uint64_t msg; 2554 2555 if (pbm_err_p->pbm_afsr & XMITS_PCI_X_AFSR_S_SC_ERR) 2556 return (0); 2557 2558 if (pbm_err_p->pbm_afsr & XMITS_PCI_X_AFSR_P_SC_ERR) { 2559 msg = (pbm_err_p->pbm_afsr >> XMITS_PCI_X_P_MSG_SHIFT) & 2560 XMITS_PCIX_MSG_MASK; 2561 if (msg & PCIX_CLASS_BRIDGE) 2562 if (msg & PCIX_BRIDGE_MASTER_ABORT) { 2563 return (1); 2564 } 2565 } 2566 2567 return (0); 2568 } 2569 2570 /* 2571 * Function used to gather PBM/PCI/IOMMU error state for the 2572 * pci_pbm_err_handler and the cb_buserr_intr. This function must be 2573 * called while pci_fm_mutex is held. 2574 */ 2575 static void 2576 pci_pbm_errstate_get(pci_t *pci_p, pbm_errstate_t *pbm_err_p) 2577 { 2578 pbm_t *pbm_p = pci_p->pci_pbm_p; 2579 iommu_t *iommu_p = pci_p->pci_iommu_p; 2580 caddr_t a = pci_p->pci_address[0]; 2581 uint64_t *pbm_pcix_stat_reg; 2582 2583 ASSERT(MUTEX_HELD(&pci_p->pci_common_p->pci_fm_mutex)); 2584 bzero(pbm_err_p, sizeof (pbm_errstate_t)); 2585 2586 /* 2587 * Capture all pbm error state for later logging 2588 */ 2589 pbm_err_p->pbm_bridge_type = PCI_BRIDGE_TYPE(pci_p->pci_common_p); 2590 2591 pbm_err_p->pbm_pci.pci_cfg_stat = 2592 pbm_p->pbm_config_header->ch_status_reg; 2593 pbm_err_p->pbm_ctl_stat = *pbm_p->pbm_ctrl_reg; 2594 pbm_err_p->pbm_afsr = *pbm_p->pbm_async_flt_status_reg; 2595 pbm_err_p->pbm_afar = *pbm_p->pbm_async_flt_addr_reg; 2596 pbm_err_p->pbm_iommu.iommu_stat = *iommu_p->iommu_ctrl_reg; 2597 pbm_err_p->pbm_pci.pci_cfg_comm = 2598 pbm_p->pbm_config_header->ch_command_reg; 2599 pbm_err_p->pbm_pci.pci_pa = *pbm_p->pbm_async_flt_addr_reg; 2600 2601 /* 2602 * Record errant slot for Xmits and Schizo 2603 * Not stored in Tomatillo 2604 */ 2605 if (CHIP_TYPE(pci_p) == PCI_CHIP_XMITS || 2606 CHIP_TYPE(pci_p) == PCI_CHIP_SCHIZO) { 2607 pbm_err_p->pbm_err_sl = (pbm_err_p->pbm_ctl_stat & 2608 SCHIZO_PCI_CTRL_ERR_SLOT) >> 2609 SCHIZO_PCI_CTRL_ERR_SLOT_SHIFT; 2610 2611 /* 2612 * The bit 51 on XMITS rev1.0 is same as 2613 * SCHIZO_PCI_CTRL_ERR_SLOT_LOCK on schizo2.3. But 2614 * this bit needs to be cleared to be able to latch 2615 * the slot info on next fault. 2616 * But in XMITS Rev2.0, this bit indicates a DMA Write 2617 * Parity error. 2618 */ 2619 if (pbm_err_p->pbm_ctl_stat & XMITS_PCI_CTRL_DMA_WR_PERR) { 2620 if ((PCI_CHIP_ID(pci_p) == XMITS_VER_10) || 2621 (PCI_CHIP_ID(pci_p) <= SCHIZO_VER_23)) { 2622 /* 2623 * top 32 bits are W1C and we just want to 2624 * clear SLOT_LOCK. Leave bottom 32 bits 2625 * unchanged 2626 */ 2627 *pbm_p->pbm_ctrl_reg = 2628 pbm_err_p->pbm_ctl_stat & 2629 (SCHIZO_PCI_CTRL_ERR_SLOT_LOCK | 2630 0xffffffff); 2631 pbm_err_p->pbm_ctl_stat = *pbm_p->pbm_ctrl_reg; 2632 } 2633 } 2634 } 2635 2636 /* 2637 * Tomatillo specific registers 2638 */ 2639 if (CHIP_TYPE(pci_p) == PCI_CHIP_TOMATILLO) { 2640 pbm_err_p->pbm_va_log = (uint64_t)va_to_pa( 2641 (void *)(uintptr_t)*(a + TOMATILLO_TGT_ERR_VALOG_OFFSET)); 2642 pbm_err_p->pbm_iommu.iommu_tfar = *iommu_p->iommu_tfar_reg; 2643 } 2644 2645 /* 2646 * Xmits PCI-X register 2647 */ 2648 if ((CHIP_TYPE(pci_p) == PCI_CHIP_XMITS) && 2649 (pbm_err_p->pbm_ctl_stat & XMITS_PCI_CTRL_X_MODE)) { 2650 2651 pbm_pcix_stat_reg = (uint64_t *)(a + 2652 XMITS_PCI_X_ERROR_STATUS_REG_OFFSET); 2653 2654 pbm_err_p->pbm_pcix_stat = *pbm_pcix_stat_reg; 2655 pbm_err_p->pbm_pcix_pfar = pbm_err_p->pbm_pcix_stat & 2656 XMITS_PCI_X_STATUS_PFAR_MASK; 2657 } 2658 } 2659 2660 /* 2661 * Function used to clear PBM/PCI/IOMMU error state after error handling 2662 * is complete. Only clearing error bits which have been logged. Called by 2663 * pci_pbm_err_handler and pci_bus_exit. 2664 */ 2665 static void 2666 pci_clear_error(pci_t *pci_p, pbm_errstate_t *pbm_err_p) 2667 { 2668 pbm_t *pbm_p = pci_p->pci_pbm_p; 2669 iommu_t *iommu_p = pci_p->pci_iommu_p; 2670 2671 ASSERT(MUTEX_HELD(&pbm_p->pbm_pci_p->pci_common_p->pci_fm_mutex)); 2672 2673 if (*pbm_p->pbm_ctrl_reg & SCHIZO_PCI_CTRL_PCI_MMU_ERR) { 2674 iommu_tlb_scrub(pci_p->pci_iommu_p, 1); 2675 } 2676 pbm_p->pbm_config_header->ch_status_reg = 2677 pbm_err_p->pbm_pci.pci_cfg_stat; 2678 *pbm_p->pbm_ctrl_reg = pbm_err_p->pbm_ctl_stat; 2679 *pbm_p->pbm_async_flt_status_reg = pbm_err_p->pbm_afsr; 2680 *iommu_p->iommu_ctrl_reg = pbm_err_p->pbm_iommu.iommu_stat; 2681 } 2682 2683 void 2684 pbm_clear_error(pbm_t *pbm_p) 2685 { 2686 uint64_t pbm_afsr, pbm_ctl_stat; 2687 2688 /* 2689 * for poke() support - called from POKE_FLUSH. Spin waiting 2690 * for MA, TA or SERR to be cleared by a pbm_error_intr(). 2691 * We have to wait for SERR too in case the device is beyond 2692 * a pci-pci bridge. 2693 */ 2694 pbm_ctl_stat = *pbm_p->pbm_ctrl_reg; 2695 pbm_afsr = *pbm_p->pbm_async_flt_status_reg; 2696 while (((pbm_afsr >> SCHIZO_PCI_AFSR_PE_SHIFT) & 2697 (SCHIZO_PCI_AFSR_E_MA | SCHIZO_PCI_AFSR_E_TA)) || 2698 (pbm_ctl_stat & COMMON_PCI_CTRL_SERR)) { 2699 pbm_ctl_stat = *pbm_p->pbm_ctrl_reg; 2700 pbm_afsr = *pbm_p->pbm_async_flt_status_reg; 2701 } 2702 } 2703 2704 /* 2705 * Function used to convert the 32 bit captured PCI error address 2706 * to the full Safari or Jbus address. This is so we can look this address 2707 * up in our handle caches. 2708 */ 2709 void 2710 pci_format_addr(dev_info_t *dip, uint64_t *afar, uint64_t afsr) 2711 { 2712 pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 2713 pci_ranges_t *io_range, *mem_range; 2714 uint64_t err_pa = 0; 2715 2716 if (afsr & SCHIZO_PCI_AFSR_CONF_SPACE) { 2717 err_pa |= pci_p->pci_ranges->parent_high; 2718 err_pa = err_pa << 32; 2719 err_pa |= pci_p->pci_ranges->parent_low; 2720 } else if (afsr & SCHIZO_PCI_AFSR_IO_SPACE) { 2721 io_range = pci_p->pci_ranges + 1; 2722 err_pa |= io_range->parent_high; 2723 err_pa = err_pa << 32; 2724 err_pa |= io_range->parent_low; 2725 } else if (afsr & SCHIZO_PCI_AFSR_MEM_SPACE) { 2726 mem_range = pci_p->pci_ranges + 2; 2727 err_pa |= mem_range->parent_high; 2728 err_pa = err_pa << 32; 2729 err_pa |= mem_range->parent_low; 2730 } 2731 *afar |= err_pa; 2732 } 2733 2734 static ecc_format_t ecc_format_tbl[] = { 2735 SCH_REG_UPA, NULL, NULL, 2736 SCH_REG_PCIA_REG, SCHIZO_PCI_AFSR_CONF_SPACE, PCI_SIDEA, 2737 SCH_REG_PCIA_MEM, SCHIZO_PCI_AFSR_MEM_SPACE, PCI_SIDEA, 2738 SCH_REG_PCIA_CFGIO, SCHIZO_PCI_AFSR_IO_SPACE, PCI_SIDEA, 2739 SCH_REG_PCIB_REG, SCHIZO_PCI_AFSR_CONF_SPACE, PCI_SIDEB, 2740 SCH_REG_PCIB_MEM, SCHIZO_PCI_AFSR_MEM_SPACE, PCI_SIDEB, 2741 SCH_REG_PCIB_CFGIO, SCHIZO_PCI_AFSR_IO_SPACE, PCI_SIDEB, 2742 SCH_REG_SAFARI_REGS, NULL, NULL, 2743 NULL, NULL, NULL, 2744 }; 2745 2746 /* 2747 * Function used to convert the 32 bit PIO address captured for a 2748 * Safari Bus UE(during PIO Rd/Wr) to a full Safari Bus Address. 2749 */ 2750 static void 2751 pci_format_ecc_addr(dev_info_t *dip, uint64_t *afar, ecc_region_t region) 2752 { 2753 pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 2754 pci_common_t *cmn_p = pci_p->pci_common_p; 2755 cb_t *cb_p = pci_p->pci_cb_p; 2756 int i, pci_side = 0; 2757 int swap = 0; 2758 uint64_t pa = cb_p->cb_base_pa; 2759 uint64_t flag, schizo_base, pci_csr_base; 2760 2761 if (pci_p == NULL) 2762 return; 2763 2764 pci_csr_base = va_to_pa(pci_p->pci_address[0]); 2765 2766 /* 2767 * Using the csr_base address to determine which side 2768 * we are on. 2769 */ 2770 if (pci_csr_base & PCI_SIDE_ADDR_MASK) 2771 pci_side = 1; 2772 else 2773 pci_side = 0; 2774 2775 schizo_base = pa - PBM_CTRL_OFFSET; 2776 2777 for (i = 0; ecc_format_tbl[i].ecc_region != NULL; i++) { 2778 if (region == ecc_format_tbl[i].ecc_region) { 2779 flag = ecc_format_tbl[i].ecc_space; 2780 if (ecc_format_tbl[i].ecc_side != pci_side) 2781 swap = 1; 2782 if (region == SCH_REG_SAFARI_REGS) 2783 *afar |= schizo_base; 2784 break; 2785 } 2786 } 2787 2788 if (swap) { 2789 pci_p = cmn_p->pci_p[PCI_OTHER_SIDE(pci_p->pci_side)]; 2790 2791 if (pci_p == NULL) 2792 return; 2793 } 2794 pci_format_addr(pci_p->pci_dip, afar, flag); 2795 } 2796 2797 /* 2798 * Function used to post control block specific ereports. 2799 */ 2800 static void 2801 cb_ereport_post(dev_info_t *dip, uint64_t ena, cb_errstate_t *cb_err) 2802 { 2803 pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 2804 char buf[FM_MAX_CLASS], dev_path[MAXPATHLEN], *ptr; 2805 struct i_ddi_fmhdl *fmhdl = DEVI(dip)->devi_fmhdl; 2806 nvlist_t *ereport, *detector; 2807 errorq_elem_t *eqep; 2808 nv_alloc_t *nva; 2809 2810 DEBUG1(DBG_ATTACH, dip, "cb_ereport_post: elog 0x%lx", 2811 cb_err->cb_elog); 2812 2813 /* 2814 * We do not use ddi_fm_ereport_post because we need to set a 2815 * special detector here. Since we do not have a device path for 2816 * the bridge chip we use what we think it should be to aid in 2817 * diagnosis. 2818 */ 2819 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s.%s", DDI_IO_CLASS, 2820 cb_err->cb_bridge_type, cb_err->cb_err_class); 2821 2822 ena = ena ? ena : fm_ena_generate(0, FM_ENA_FMT1); 2823 2824 eqep = errorq_reserve(fmhdl->fh_errorq); 2825 if (eqep == NULL) 2826 return; 2827 2828 ereport = errorq_elem_nvl(fmhdl->fh_errorq, eqep); 2829 nva = errorq_elem_nva(fmhdl->fh_errorq, eqep); 2830 detector = fm_nvlist_create(nva); 2831 2832 ASSERT(ereport); 2833 ASSERT(nva); 2834 ASSERT(detector); 2835 2836 ddi_pathname(dip, dev_path); 2837 ptr = strrchr(dev_path, (int)','); 2838 2839 if (ptr) 2840 *ptr = '\0'; 2841 2842 fm_fmri_dev_set(detector, FM_DEV_SCHEME_VERSION, NULL, dev_path, NULL); 2843 2844 DEBUG1(DBG_ERR_INTR, dip, "cb_ereport_post: ereport_set: %s", buf); 2845 2846 if (CHIP_TYPE(pci_p) == PCI_CHIP_SCHIZO || 2847 CHIP_TYPE(pci_p) == PCI_CHIP_XMITS) { 2848 fm_ereport_set(ereport, FM_EREPORT_VERSION, buf, ena, detector, 2849 SAFARI_CSR, DATA_TYPE_UINT64, cb_err->cb_csr, 2850 SAFARI_ERR, DATA_TYPE_UINT64, cb_err->cb_err, 2851 SAFARI_INTR, DATA_TYPE_UINT64, cb_err->cb_intr, 2852 SAFARI_ELOG, DATA_TYPE_UINT64, cb_err->cb_elog, 2853 SAFARI_PCR, DATA_TYPE_UINT64, cb_err->cb_pcr, 2854 NULL); 2855 } else if (CHIP_TYPE(pci_p) == PCI_CHIP_TOMATILLO) { 2856 fm_ereport_set(ereport, FM_EREPORT_VERSION, buf, ena, detector, 2857 JBUS_CSR, DATA_TYPE_UINT64, cb_err->cb_csr, 2858 JBUS_ERR, DATA_TYPE_UINT64, cb_err->cb_err, 2859 JBUS_INTR, DATA_TYPE_UINT64, cb_err->cb_intr, 2860 JBUS_ELOG, DATA_TYPE_UINT64, cb_err->cb_elog, 2861 JBUS_PCR, DATA_TYPE_UINT64, cb_err->cb_pcr, 2862 NULL); 2863 } 2864 errorq_commit(fmhdl->fh_errorq, eqep, ERRORQ_ASYNC); 2865 } 2866 2867 /* 2868 * Function used to post IOMMU specific ereports. 2869 */ 2870 static void 2871 iommu_ereport_post(dev_info_t *dip, uint64_t ena, pbm_errstate_t *pbm_err) 2872 { 2873 char buf[FM_MAX_CLASS]; 2874 2875 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", 2876 pbm_err->pbm_bridge_type, pbm_err->pbm_err_class); 2877 2878 ena = ena ? ena : fm_ena_generate(0, FM_ENA_FMT1); 2879 2880 DEBUG1(DBG_ERR_INTR, dip, "iommu_ereport_post: ereport_set: %s", buf); 2881 2882 ddi_fm_ereport_post(dip, buf, ena, DDI_NOSLEEP, 2883 FM_VERSION, DATA_TYPE_UINT8, 0, 2884 PCI_CONFIG_STATUS, DATA_TYPE_UINT16, pbm_err->pbm_pci.pci_cfg_stat, 2885 PCI_CONFIG_COMMAND, DATA_TYPE_UINT16, pbm_err->pbm_pci.pci_cfg_comm, 2886 PCI_PBM_CSR, DATA_TYPE_UINT64, pbm_err->pbm_ctl_stat, 2887 PCI_PBM_IOMMU_CTRL, DATA_TYPE_UINT64, pbm_err->pbm_iommu.iommu_stat, 2888 PCI_PBM_IOMMU_TFAR, DATA_TYPE_UINT64, pbm_err->pbm_iommu.iommu_tfar, 2889 PCI_PBM_SLOT, DATA_TYPE_UINT64, pbm_err->pbm_err_sl, 2890 PCI_PBM_VALOG, DATA_TYPE_UINT64, pbm_err->pbm_va_log, 2891 NULL); 2892 } 2893 2894 /* 2895 * Function used to post PCI-X generic ereports. 2896 * This function needs to be fixed once the Fault Boundary Analysis 2897 * for PCI-X is conducted. The payload should be made more generic. 2898 */ 2899 static void 2900 pcix_ereport_post(dev_info_t *dip, uint64_t ena, pbm_errstate_t *pbm_err) 2901 { 2902 char buf[FM_MAX_CLASS]; 2903 2904 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", 2905 pbm_err->pbm_bridge_type, pbm_err->pbm_err_class); 2906 2907 ena = ena ? ena : fm_ena_generate(0, FM_ENA_FMT1); 2908 2909 DEBUG1(DBG_ERR_INTR, dip, "pcix_ereport_post: ereport_post: %s", buf); 2910 2911 ddi_fm_ereport_post(dip, buf, ena, DDI_NOSLEEP, 2912 FM_VERSION, DATA_TYPE_UINT8, 0, 2913 PCI_CONFIG_STATUS, DATA_TYPE_UINT16, pbm_err->pbm_pci.pci_cfg_stat, 2914 PCI_CONFIG_COMMAND, DATA_TYPE_UINT16, pbm_err->pbm_pci.pci_cfg_comm, 2915 PCI_PBM_CSR, DATA_TYPE_UINT64, pbm_err->pbm_ctl_stat, 2916 PCI_PBM_AFSR, DATA_TYPE_UINT64, pbm_err->pbm_afsr, 2917 PCI_PBM_AFAR, DATA_TYPE_UINT64, pbm_err->pbm_afar, 2918 PCI_PBM_SLOT, DATA_TYPE_UINT64, pbm_err->pbm_err_sl, 2919 PCIX_STAT, DATA_TYPE_UINT64, pbm_err->pbm_pcix_stat, 2920 PCIX_PFAR, DATA_TYPE_UINT32, pbm_err->pbm_pcix_pfar, 2921 NULL); 2922 } 2923 2924 static void 2925 iommu_ctx_free(iommu_t *iommu_p) 2926 { 2927 kmem_free(iommu_p->iommu_ctx_bitmap, IOMMU_CTX_BITMAP_SIZE); 2928 } 2929 2930 /* 2931 * iommu_tlb_scrub(): 2932 * Exam TLB entries through TLB diagnostic registers and look for errors. 2933 * scrub = 1 : cleanup all error bits in tlb, called in FAULT_RESET case 2934 * scrub = 0 : log all error conditions to console, FAULT_LOG case 2935 * In both cases, it returns number of errors found in tlb entries. 2936 */ 2937 static int 2938 iommu_tlb_scrub(iommu_t *iommu_p, int scrub) 2939 { 2940 int i, nerr = 0; 2941 dev_info_t *dip = iommu_p->iommu_pci_p->pci_dip; 2942 char *neg = "not "; 2943 2944 uint64_t base = (uint64_t)iommu_p->iommu_ctrl_reg - 2945 COMMON_IOMMU_CTRL_REG_OFFSET; 2946 2947 volatile uint64_t *tlb_tag = (volatile uint64_t *) 2948 (base + COMMON_IOMMU_TLB_TAG_DIAG_ACC_OFFSET); 2949 volatile uint64_t *tlb_data = (volatile uint64_t *) 2950 (base + COMMON_IOMMU_TLB_DATA_DIAG_ACC_OFFSET); 2951 for (i = 0; i < IOMMU_TLB_ENTRIES; i++) { 2952 uint64_t tag = tlb_tag[i]; 2953 uint64_t data = tlb_data[i]; 2954 uint32_t errstat; 2955 iopfn_t pfn; 2956 2957 if (!(tag & TLBTAG_ERR_BIT)) 2958 continue; 2959 2960 pfn = (iopfn_t)(data & TLBDATA_MEMPA_BITS); 2961 errstat = (uint32_t) 2962 ((tag & TLBTAG_ERRSTAT_BITS) >> TLBTAG_ERRSTAT_SHIFT); 2963 if (errstat == TLBTAG_ERRSTAT_INVALID) { 2964 if (scrub) 2965 tlb_tag[i] = tlb_data[i] = 0ull; 2966 } else 2967 nerr++; 2968 2969 if (scrub) 2970 continue; 2971 2972 cmn_err(CE_CONT, "%s%d: Error %x on IOMMU TLB entry %x:\n" 2973 "\tContext=%lx %sWritable %sStreamable\n" 2974 "\tPCI Page Size=%sk Address in page %lx\n", 2975 ddi_driver_name(dip), ddi_get_instance(dip), errstat, i, 2976 (tag & TLBTAG_CONTEXT_BITS) >> TLBTAG_CONTEXT_SHIFT, 2977 (tag & TLBTAG_WRITABLE_BIT) ? "" : neg, 2978 (tag & TLBTAG_STREAM_BIT) ? "" : neg, 2979 (tag & TLBTAG_PGSIZE_BIT) ? "64" : "8", 2980 (tag & TLBTAG_PCIVPN_BITS) << 13); 2981 cmn_err(CE_CONT, "Memory: %sValid %sCacheable Page Frame=%lx\n", 2982 (data & TLBDATA_VALID_BIT) ? "" : neg, 2983 (data & TLBDATA_CACHE_BIT) ? "" : neg, pfn); 2984 } 2985 return (nerr); 2986 } 2987 2988 /* 2989 * pci_iommu_disp: calculates the displacement needed in tomatillo's 2990 * iommu control register and modifies the control value template 2991 * from caller. It also clears any error status bit that are new 2992 * in tomatillo. 2993 * return value: an 8-bit mask to enable corresponding 512 MB segments 2994 * suitable for tomatillo's target address register. 2995 * 0x00: no programming is needed, use existing value from prom 2996 * 0x60: use segment 5 and 6 to form a 1GB dvma range 2997 */ 2998 static uint64_t 2999 pci_iommu_disp(iommu_t *iommu_p, uint64_t *ctl_p) 3000 { 3001 uint64_t ctl_old; 3002 if (CHIP_TYPE(iommu_p->iommu_pci_p) != PCI_CHIP_TOMATILLO) 3003 return (0); 3004 3005 ctl_old = *iommu_p->iommu_ctrl_reg; 3006 /* iommu ctrl reg error bits are W1C */ 3007 if (ctl_old >> TOMATIILO_IOMMU_ERR_REG_SHIFT) { 3008 cmn_err(CE_WARN, "Tomatillo iommu err: %lx", ctl_old); 3009 *ctl_p |= (ctl_old >> TOMATIILO_IOMMU_ERR_REG_SHIFT) 3010 << TOMATIILO_IOMMU_ERR_REG_SHIFT; 3011 } 3012 3013 if (iommu_p->iommu_tsb_size != TOMATILLO_IOMMU_TSB_MAX) 3014 return (0); 3015 3016 /* Tomatillo 2.0 and later, and 1GB DVMA range */ 3017 *ctl_p |= 1 << TOMATILLO_IOMMU_SEG_DISP_SHIFT; 3018 return (3 << (iommu_p->iommu_dvma_base >> (32 - 3))); 3019 } 3020 3021 void 3022 pci_iommu_config(iommu_t *iommu_p, uint64_t iommu_ctl, uint64_t cfgpa) 3023 { 3024 uintptr_t pbm_regbase = get_pbm_reg_base(iommu_p->iommu_pci_p); 3025 volatile uint64_t *pbm_csr_p = (volatile uint64_t *)pbm_regbase; 3026 volatile uint64_t *tgt_space_p = (volatile uint64_t *)(pbm_regbase | 3027 (TOMATILLO_TGT_ADDR_SPACE_OFFSET - SCHIZO_PCI_CTRL_REG_OFFSET)); 3028 volatile uint64_t pbm_ctl = *pbm_csr_p; 3029 3030 volatile uint64_t *iommu_ctl_p = iommu_p->iommu_ctrl_reg; 3031 volatile uint64_t tsb_bar_val = iommu_p->iommu_tsb_paddr; 3032 volatile uint64_t *tsb_bar_p = iommu_p->iommu_tsb_base_addr_reg; 3033 uint64_t mask = pci_iommu_disp(iommu_p, &iommu_ctl); 3034 3035 DEBUG2(DBG_ATTACH, iommu_p->iommu_pci_p->pci_dip, 3036 "\npci_iommu_config: pbm_csr_p=%llx pbm_ctl=%llx", 3037 pbm_csr_p, pbm_ctl); 3038 DEBUG2(DBG_ATTACH|DBG_CONT, iommu_p->iommu_pci_p->pci_dip, 3039 "\n\tiommu_ctl_p=%llx iommu_ctl=%llx", 3040 iommu_ctl_p, iommu_ctl); 3041 DEBUG4(DBG_ATTACH|DBG_CONT, iommu_p->iommu_pci_p->pci_dip, 3042 "\n\tcfgpa=%llx tgt_space_p=%llx mask=%x tsb=%llx\n", 3043 cfgpa, tgt_space_p, mask, tsb_bar_val); 3044 3045 if (!cfgpa) 3046 goto reprog; 3047 3048 /* disable PBM arbiters - turn off bits 0-7 */ 3049 *pbm_csr_p = (pbm_ctl >> 8) << 8; 3050 3051 /* 3052 * For non-XMITS, flush any previous writes. This is only 3053 * necessary for host bridges that may have a USB keywboard 3054 * attached. XMITS does not. 3055 */ 3056 if (!(CHIP_TYPE(iommu_p->iommu_pci_p) == PCI_CHIP_XMITS)) 3057 (void) ldphysio(cfgpa); 3058 3059 reprog: 3060 if (mask) 3061 *tgt_space_p = mask; 3062 3063 *tsb_bar_p = tsb_bar_val; 3064 *iommu_ctl_p = iommu_ctl; 3065 3066 *pbm_csr_p = pbm_ctl; /* re-enable bus arbitration */ 3067 pbm_ctl = *pbm_csr_p; /* flush all prev writes */ 3068 } 3069 3070 3071 int 3072 pci_get_portid(dev_info_t *dip) 3073 { 3074 return (ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 3075 "portid", -1)); 3076 } 3077 3078 /* 3079 * Schizo Safari Performance Events. 3080 */ 3081 pci_kev_mask_t 3082 schizo_saf_events[] = { 3083 {"saf_bus_cycles", 0x1}, {"saf_pause_asserted_cycles", 0x2}, 3084 {"saf_frn_coherent_cmds", 0x3}, {"saf_frn_coherent_hits", 0x4}, 3085 {"saf_my_coherent_cmds", 0x5}, {"saf_my_coherent_hits", 0x6}, 3086 {"saf_frn_io_cmds", 0x7}, {"saf_frn_io_hits", 0x8}, 3087 {"merge_buffer", 0x9}, {"interrupts", 0xa}, 3088 {"csr_pios", 0xc}, {"upa_pios", 0xd}, 3089 {"pcia_pios", 0xe}, {"pcib_pios", 0xf}, 3090 {"saf_pause_seen_cycles", 0x11}, {"dvma_reads", 0x12}, 3091 {"dvma_writes", 0x13}, {"saf_orq_full_cycles", 0x14}, 3092 {"saf_data_in_cycles", 0x15}, {"saf_data_out_cycles", 0x16}, 3093 {"clear_pic", 0x1f} 3094 }; 3095 3096 3097 /* 3098 * Schizo PCI Performance Events. 3099 */ 3100 pci_kev_mask_t 3101 schizo_pci_events[] = { 3102 {"dvma_stream_rd", 0x0}, {"dvma_stream_wr", 0x1}, 3103 {"dvma_const_rd", 0x2}, {"dvma_const_wr", 0x3}, 3104 {"dvma_stream_buf_mis", 0x4}, {"dvma_cycles", 0x5}, 3105 {"dvma_wd_xfr", 0x6}, {"pio_cycles", 0x7}, 3106 {"dvma_tlb_misses", 0x10}, {"interrupts", 0x11}, 3107 {"saf_inter_nack", 0x12}, {"pio_reads", 0x13}, 3108 {"pio_writes", 0x14}, {"dvma_rd_buf_timeout", 0x15}, 3109 {"dvma_rd_rtry_stc", 0x16}, {"dvma_wr_rtry_stc", 0x17}, 3110 {"dvma_rd_rtry_nonstc", 0x18}, {"dvma_wr_rtry_nonstc", 0x19}, 3111 {"E*_slow_transitions", 0x1a}, {"E*_slow_cycles_per_64", 0x1b}, 3112 {"clear_pic", 0x1f} 3113 }; 3114 3115 3116 /* 3117 * Create the picN kstats for the pci 3118 * and safari events. 3119 */ 3120 void 3121 pci_kstat_init() 3122 { 3123 pci_name_kstat = (pci_ksinfo_t *)kmem_alloc(sizeof (pci_ksinfo_t), 3124 KM_NOSLEEP); 3125 3126 if (pci_name_kstat == NULL) { 3127 cmn_err(CE_WARN, "pcisch : no space for kstat\n"); 3128 } else { 3129 pci_name_kstat->pic_no_evs = 3130 sizeof (schizo_pci_events) / sizeof (pci_kev_mask_t); 3131 pci_name_kstat->pic_shift[0] = SCHIZO_SHIFT_PIC0; 3132 pci_name_kstat->pic_shift[1] = SCHIZO_SHIFT_PIC1; 3133 pci_create_name_kstat("pcis", 3134 pci_name_kstat, schizo_pci_events); 3135 } 3136 3137 saf_name_kstat = (pci_ksinfo_t *)kmem_alloc(sizeof (pci_ksinfo_t), 3138 KM_NOSLEEP); 3139 if (saf_name_kstat == NULL) { 3140 cmn_err(CE_WARN, "pcisch : no space for kstat\n"); 3141 } else { 3142 saf_name_kstat->pic_no_evs = 3143 sizeof (schizo_saf_events) / sizeof (pci_kev_mask_t); 3144 saf_name_kstat->pic_shift[0] = SCHIZO_SHIFT_PIC0; 3145 saf_name_kstat->pic_shift[1] = SCHIZO_SHIFT_PIC1; 3146 pci_create_name_kstat("saf", saf_name_kstat, schizo_saf_events); 3147 } 3148 } 3149 3150 void 3151 pci_kstat_fini() 3152 { 3153 if (pci_name_kstat != NULL) { 3154 pci_delete_name_kstat(pci_name_kstat); 3155 kmem_free(pci_name_kstat, sizeof (pci_ksinfo_t)); 3156 pci_name_kstat = NULL; 3157 } 3158 3159 if (saf_name_kstat != NULL) { 3160 pci_delete_name_kstat(saf_name_kstat); 3161 kmem_free(saf_name_kstat, sizeof (pci_ksinfo_t)); 3162 saf_name_kstat = NULL; 3163 } 3164 } 3165 3166 /* 3167 * Create 'counters' kstat for pci events. 3168 */ 3169 void 3170 pci_add_pci_kstat(pci_t *pci_p) 3171 { 3172 pci_cntr_addr_t *cntr_addr_p = &pci_p->pci_ks_addr; 3173 uintptr_t regbase = (uintptr_t)pci_p->pci_address[0]; 3174 3175 cntr_addr_p->pcr_addr = (uint64_t *) 3176 (regbase + SCHIZO_PERF_PCI_PCR_OFFSET); 3177 cntr_addr_p->pic_addr = (uint64_t *) 3178 (regbase + SCHIZO_PERF_PCI_PIC_OFFSET); 3179 3180 pci_p->pci_ksp = pci_create_cntr_kstat(pci_p, "pcis", 3181 NUM_OF_PICS, pci_cntr_kstat_update, cntr_addr_p); 3182 3183 if (pci_p->pci_ksp == NULL) { 3184 cmn_err(CE_WARN, "pcisch : cannot create counter kstat"); 3185 } 3186 } 3187 3188 void 3189 pci_rem_pci_kstat(pci_t *pci_p) 3190 { 3191 if (pci_p->pci_ksp != NULL) 3192 kstat_delete(pci_p->pci_ksp); 3193 pci_p->pci_ksp = NULL; 3194 } 3195 3196 void 3197 pci_add_upstream_kstat(pci_t *pci_p) 3198 { 3199 pci_common_t *cmn_p = pci_p->pci_common_p; 3200 pci_cntr_pa_t *cntr_pa_p = &cmn_p->pci_cmn_uks_pa; 3201 uint64_t regbase = va_to_pa(pci_p->pci_address[1]); 3202 3203 cntr_pa_p->pcr_pa = 3204 regbase + SCHIZO_PERF_SAF_PCR_OFFSET; 3205 cntr_pa_p->pic_pa = 3206 regbase + SCHIZO_PERF_SAF_PIC_OFFSET; 3207 3208 cmn_p->pci_common_uksp = pci_create_cntr_kstat(pci_p, "saf", 3209 NUM_OF_PICS, pci_cntr_kstat_pa_update, cntr_pa_p); 3210 } 3211 3212 /* 3213 * Extract the drivers binding name to identify which chip 3214 * we're binding to. Whenever a new bus bridge is created, the driver alias 3215 * entry should be added here to identify the device if needed. If a device 3216 * isn't added, the identity defaults to PCI_CHIP_UNIDENTIFIED. 3217 */ 3218 static uint32_t 3219 pci_identity_init(pci_t *pci_p) 3220 { 3221 dev_info_t *dip = pci_p->pci_dip; 3222 char *name = ddi_binding_name(dip); 3223 uint32_t ver = ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 3224 "version#", 0); 3225 3226 if (strcmp(name, "pci108e,a801") == 0) 3227 return (CHIP_ID(PCI_CHIP_TOMATILLO, ver, 0x00)); 3228 3229 if (strcmp(name, "pci108e,8001") == 0) 3230 return (CHIP_ID(PCI_CHIP_SCHIZO, ver, 0x00)); 3231 3232 if (strcmp(name, "pci108e,8002") == 0) { 3233 uint32_t mod_rev = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 3234 DDI_PROP_DONTPASS, "module-revision#", 0); 3235 return (CHIP_ID(PCI_CHIP_XMITS, ver, mod_rev)); 3236 } 3237 3238 cmn_err(CE_WARN, "%s%d: Unknown PCI Host bridge %s %x\n", 3239 ddi_driver_name(dip), ddi_get_instance(dip), name, ver); 3240 3241 return (PCI_CHIP_UNIDENTIFIED); 3242 } 3243 3244 /* 3245 * Setup a physical pointer to one leaf config space area. This 3246 * is used in several places in order to do a dummy read which 3247 * guarantees the nexus (and not a bus master) has gained control 3248 * of the bus. 3249 */ 3250 static void 3251 pci_setup_cfgpa(pci_t *pci_p) 3252 { 3253 dev_info_t *dip = pci_p->pci_dip; 3254 dev_info_t *cdip; 3255 pbm_t *pbm_p = pci_p->pci_pbm_p; 3256 uint64_t cfgpa = pci_get_cfg_pabase(pci_p); 3257 uint32_t *reg_p; 3258 int reg_len; 3259 3260 for (cdip = ddi_get_child(dip); cdip != NULL; 3261 cdip = ddi_get_next_sibling(cdip)) { 3262 if (ddi_getlongprop(DDI_DEV_T_ANY, cdip, DDI_PROP_DONTPASS, 3263 "reg", (caddr_t)®_p, ®_len) != DDI_PROP_SUCCESS) 3264 continue; 3265 cfgpa += (*reg_p) & (PCI_CONF_ADDR_MASK ^ PCI_REG_REG_M); 3266 kmem_free(reg_p, reg_len); 3267 break; 3268 } 3269 pbm_p->pbm_anychild_cfgpa = cfgpa; 3270 } 3271 3272 void 3273 pci_post_init_child(pci_t *pci_p, dev_info_t *child) 3274 { 3275 volatile uint64_t *ctrl_reg_p; 3276 pbm_t *pbm_p = pci_p->pci_pbm_p; 3277 3278 pci_setup_cfgpa(pci_p); 3279 3280 /* 3281 * This is a hack for skyhawk/casinni combination to address 3282 * hardware problems between the request and grant signals which 3283 * causes a bus hang. One workaround, which is applied here, 3284 * is to disable bus parking if the child contains the property 3285 * pci-req-removal. Note that if the bus is quiesced we must mask 3286 * off the parking bit in the saved control registers, since the 3287 * quiesce operation temporarily turns off PCI bus parking. 3288 */ 3289 if (ddi_prop_exists(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS, 3290 "pci-req-removal") == 1) { 3291 3292 if (pbm_p->pbm_quiesce_count > 0) { 3293 pbm_p->pbm_saved_ctrl_reg &= ~SCHIZO_PCI_CTRL_ARB_PARK; 3294 } else { 3295 ctrl_reg_p = pbm_p->pbm_ctrl_reg; 3296 *ctrl_reg_p &= ~SCHIZO_PCI_CTRL_ARB_PARK; 3297 } 3298 } 3299 3300 if (CHIP_TYPE(pci_p) == PCI_CHIP_XMITS) { 3301 if (*pbm_p->pbm_ctrl_reg & XMITS_PCI_CTRL_X_MODE) { 3302 int value; 3303 3304 /* 3305 * Due to a XMITS bug, we need to set the outstanding 3306 * split transactions to 1 for all PCI-X functions 3307 * behind the leaf. 3308 */ 3309 value = (xmits_max_transactions << 4) | 3310 (xmits_max_read_bytes << 2); 3311 3312 DEBUG1(DBG_INIT_CLD, child, "Turning on XMITS NCPQ " 3313 "Workaround: value = %x\n", value); 3314 3315 pcix_set_cmd_reg(child, value); 3316 3317 (void) ndi_prop_update_int(DDI_DEV_T_NONE, 3318 child, "pcix-update-cmd-reg", value); 3319 } 3320 3321 if (PCI_CHIP_ID(pci_p) >= XMITS_VER_30) { 3322 uint64_t *pbm_pcix_diag_reg = 3323 (uint64_t *)(pci_p->pci_address[0] + 3324 XMITS_PCI_X_DIAG_REG_OFFSET); 3325 uint64_t bugcntl = (*pbm_pcix_diag_reg >> 3326 XMITS_PCI_X_DIAG_BUGCNTL_SHIFT) & 3327 XMITS_PCI_X_DIAG_BUGCNTL_MASK; 3328 uint64_t tunable = (*pbm_p->pbm_ctrl_reg & 3329 XMITS_PCI_CTRL_X_MODE ? 3330 xmits_pcix_diag_bugcntl_pcix : 3331 xmits_pcix_diag_bugcntl_pci) 3332 & XMITS_PCI_X_DIAG_BUGCNTL_MASK; 3333 3334 DEBUG4(DBG_INIT_CLD, pci_p->pci_dip, "%s: XMITS " 3335 "pcix diag bugcntl=0x%lx, tunable=0x%lx, mode=%s\n", 3336 ddi_driver_name(child), bugcntl, tunable, 3337 ((*pbm_p->pbm_ctrl_reg & XMITS_PCI_CTRL_X_MODE)? 3338 "PCI-X":"PCI")); 3339 3340 DEBUG2(DBG_INIT_CLD, pci_p->pci_dip, "%s: XMITS " 3341 "pcix diag reg=0x%lx (CUR)\n", 3342 ddi_driver_name(child), *pbm_pcix_diag_reg); 3343 3344 /* 3345 * Due to a XMITS 3.x hw bug, we need to 3346 * read PBM's xmits pci ctrl status register to 3347 * determine mode (PCI or PCI-X) and then update 3348 * PBM's pcix diag register with new BUG_FIX_CNTL 3349 * bits (47:32) _if_ different from tunable's mode 3350 * based value. This update is performed only once 3351 * during the PBM's first child init. 3352 * 3353 * Per instructions from xmits hw engineering, 3354 * non-BUG_FIX_CNTL bits should not be preserved 3355 * when updating the pcix diag register. Such bits 3356 * should be written as 0s. 3357 */ 3358 3359 if (bugcntl != tunable) { 3360 *pbm_pcix_diag_reg = tunable << 3361 XMITS_PCI_X_DIAG_BUGCNTL_SHIFT; 3362 3363 DEBUG2(DBG_INIT_CLD, pci_p->pci_dip, "%s: XMITS" 3364 " pcix diag reg=0x%lx (NEW)\n", 3365 ddi_driver_name(child), *pbm_pcix_diag_reg); 3366 } 3367 } 3368 } 3369 } 3370 3371 void 3372 pci_post_uninit_child(pci_t *pci_p) 3373 { 3374 pci_setup_cfgpa(pci_p); 3375 } 3376 3377 static int 3378 pci_tom_nbintr_op(pci_t *pci_p, uint32_t inum, intrfunc f, caddr_t arg, 3379 int flag) 3380 { 3381 uint32_t ino = pci_p->pci_inos[inum]; 3382 uint32_t mondo = IB_INO_TO_NBMONDO(pci_p->pci_ib_p, ino); 3383 int ret = DDI_SUCCESS; 3384 3385 mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo); /* no op on tom */ 3386 3387 switch (flag) { 3388 case PCI_OBJ_INTR_ADD: 3389 VERIFY(add_ivintr(mondo, pci_pil[inum], f, 3390 arg, NULL, NULL) == 0); 3391 break; 3392 case PCI_OBJ_INTR_REMOVE: 3393 VERIFY(rem_ivintr(mondo, pci_pil[inum]) == 0); 3394 break; 3395 default: 3396 ret = DDI_FAILURE; 3397 break; 3398 } 3399 3400 return (ret); 3401 } 3402 3403 int 3404 pci_ecc_add_intr(pci_t *pci_p, int inum, ecc_intr_info_t *eii_p) 3405 { 3406 uint32_t mondo; 3407 int r; 3408 3409 mondo = ((pci_p->pci_cb_p->cb_ign << PCI_INO_BITS) | 3410 pci_p->pci_inos[inum]); 3411 mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo); 3412 3413 VERIFY(add_ivintr(mondo, pci_pil[inum], (intrfunc)ecc_intr, 3414 (caddr_t)eii_p, NULL, NULL) == 0); 3415 3416 if (CHIP_TYPE(pci_p) != PCI_CHIP_TOMATILLO) 3417 return (PCI_ATTACH_RETCODE(PCI_ECC_OBJ, PCI_OBJ_INTR_ADD, 3418 DDI_SUCCESS)); 3419 3420 r = pci_tom_nbintr_op(pci_p, inum, (intrfunc)ecc_intr, 3421 (caddr_t)eii_p, PCI_OBJ_INTR_ADD); 3422 return (PCI_ATTACH_RETCODE(PCI_ECC_OBJ, PCI_OBJ_INTR_ADD, r)); 3423 } 3424 3425 void 3426 pci_ecc_rem_intr(pci_t *pci_p, int inum, ecc_intr_info_t *eii_p) 3427 { 3428 uint32_t mondo; 3429 3430 mondo = ((pci_p->pci_cb_p->cb_ign << PCI_INO_BITS) | 3431 pci_p->pci_inos[inum]); 3432 mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo); 3433 3434 VERIFY(rem_ivintr(mondo, pci_pil[inum]) == 0); 3435 3436 if (CHIP_TYPE(pci_p) == PCI_CHIP_TOMATILLO) 3437 pci_tom_nbintr_op(pci_p, inum, (intrfunc)ecc_intr, 3438 (caddr_t)eii_p, PCI_OBJ_INTR_REMOVE); 3439 } 3440 3441 static uint_t 3442 pci_pbm_cdma_intr(caddr_t a) 3443 { 3444 pbm_t *pbm_p = (pbm_t *)a; 3445 pbm_p->pbm_cdma_flag = PBM_CDMA_DONE; 3446 #ifdef PBM_CDMA_DEBUG 3447 pbm_p->pbm_cdma_intr_cnt++; 3448 #endif /* PBM_CDMA_DEBUG */ 3449 return (DDI_INTR_CLAIMED); 3450 } 3451 3452 int 3453 pci_pbm_add_intr(pci_t *pci_p) 3454 { 3455 uint32_t mondo; 3456 3457 mondo = IB_INO_TO_MONDO(pci_p->pci_ib_p, pci_p->pci_inos[CBNINTR_CDMA]); 3458 mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo); 3459 3460 VERIFY(add_ivintr(mondo, pci_pil[CBNINTR_CDMA], 3461 (intrfunc)pci_pbm_cdma_intr, (caddr_t)pci_p->pci_pbm_p, 3462 NULL, NULL) == 0); 3463 3464 return (DDI_SUCCESS); 3465 } 3466 3467 void 3468 pci_pbm_rem_intr(pci_t *pci_p) 3469 { 3470 ib_t *ib_p = pci_p->pci_ib_p; 3471 uint32_t mondo; 3472 3473 mondo = IB_INO_TO_MONDO(pci_p->pci_ib_p, pci_p->pci_inos[CBNINTR_CDMA]); 3474 mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo); 3475 3476 ib_intr_disable(ib_p, pci_p->pci_inos[CBNINTR_CDMA], IB_INTR_NOWAIT); 3477 VERIFY(rem_ivintr(mondo, pci_pil[CBNINTR_CDMA]) == 0); 3478 } 3479 3480 void 3481 pci_pbm_suspend(pci_t *pci_p) 3482 { 3483 pbm_t *pbm_p = pci_p->pci_pbm_p; 3484 ib_ino_t ino = pci_p->pci_inos[CBNINTR_CDMA]; 3485 3486 /* Save CDMA interrupt state */ 3487 pbm_p->pbm_cdma_imr_save = *ib_intr_map_reg_addr(pci_p->pci_ib_p, ino); 3488 } 3489 3490 void 3491 pci_pbm_resume(pci_t *pci_p) 3492 { 3493 pbm_t *pbm_p = pci_p->pci_pbm_p; 3494 ib_ino_t ino = pci_p->pci_inos[CBNINTR_CDMA]; 3495 3496 /* Restore CDMA interrupt state */ 3497 *ib_intr_map_reg_addr(pci_p->pci_ib_p, ino) = pbm_p->pbm_cdma_imr_save; 3498 } 3499 3500 /* 3501 * pci_bus_quiesce 3502 * 3503 * This function is called as the corresponding control ops routine 3504 * to a DDI_CTLOPS_QUIESCE command. Its mission is to halt all DMA 3505 * activity on the bus by disabling arbitration/parking. 3506 */ 3507 int 3508 pci_bus_quiesce(pci_t *pci_p, dev_info_t *dip, void *result) 3509 { 3510 volatile uint64_t *ctrl_reg_p; 3511 volatile uint64_t ctrl_reg; 3512 pbm_t *pbm_p; 3513 3514 pbm_p = pci_p->pci_pbm_p; 3515 ctrl_reg_p = pbm_p->pbm_ctrl_reg; 3516 3517 if (pbm_p->pbm_quiesce_count++ == 0) { 3518 3519 DEBUG0(DBG_PWR, dip, "quiescing bus\n"); 3520 3521 ctrl_reg = *ctrl_reg_p; 3522 pbm_p->pbm_saved_ctrl_reg = ctrl_reg; 3523 ctrl_reg &= ~(SCHIZO_PCI_CTRL_ARB_EN_MASK | 3524 SCHIZO_PCI_CTRL_ARB_PARK); 3525 *ctrl_reg_p = ctrl_reg; 3526 #ifdef DEBUG 3527 ctrl_reg = *ctrl_reg_p; 3528 if ((ctrl_reg & (SCHIZO_PCI_CTRL_ARB_EN_MASK | 3529 SCHIZO_PCI_CTRL_ARB_PARK)) != 0) 3530 panic("ctrl_reg didn't quiesce: 0x%lx\n", ctrl_reg); 3531 #endif 3532 if (pbm_p->pbm_anychild_cfgpa) 3533 (void) ldphysio(pbm_p->pbm_anychild_cfgpa); 3534 } 3535 3536 return (DDI_SUCCESS); 3537 } 3538 3539 /* 3540 * pci_bus_unquiesce 3541 * 3542 * This function is called as the corresponding control ops routine 3543 * to a DDI_CTLOPS_UNQUIESCE command. Its mission is to resume paused 3544 * DMA activity on the bus by re-enabling arbitration (and maybe parking). 3545 */ 3546 int 3547 pci_bus_unquiesce(pci_t *pci_p, dev_info_t *dip, void *result) 3548 { 3549 volatile uint64_t *ctrl_reg_p; 3550 pbm_t *pbm_p; 3551 #ifdef DEBUG 3552 volatile uint64_t ctrl_reg; 3553 #endif 3554 3555 pbm_p = pci_p->pci_pbm_p; 3556 ctrl_reg_p = pbm_p->pbm_ctrl_reg; 3557 3558 ASSERT(pbm_p->pbm_quiesce_count > 0); 3559 if (--pbm_p->pbm_quiesce_count == 0) { 3560 *ctrl_reg_p = pbm_p->pbm_saved_ctrl_reg; 3561 #ifdef DEBUG 3562 ctrl_reg = *ctrl_reg_p; 3563 if ((ctrl_reg & (SCHIZO_PCI_CTRL_ARB_EN_MASK | 3564 SCHIZO_PCI_CTRL_ARB_PARK)) == 0) 3565 panic("ctrl_reg didn't unquiesce: 0x%lx\n", ctrl_reg); 3566 #endif 3567 } 3568 3569 return (DDI_SUCCESS); 3570 } 3571 3572 int 3573 pci_reloc_getkey(void) 3574 { 3575 return (0x200); 3576 } 3577 3578 static void 3579 tm_vmem_free(ddi_dma_impl_t *mp, iommu_t *iommu_p, dvma_addr_t dvma_pg, 3580 int npages) 3581 { 3582 uint32_t dur_max, dur_base; 3583 dvma_unbind_req_t *req_p, *req_max_p; 3584 dvma_unbind_req_t *req_base_p = iommu_p->iommu_mtlb_req_p; 3585 uint32_t tlb_vpn[IOMMU_TLB_ENTRIES]; 3586 caddr_t reg_base; 3587 volatile uint64_t *tag_p; 3588 int i, preserv_count = 0; 3589 3590 mutex_enter(&iommu_p->iommu_mtlb_lock); 3591 3592 iommu_p->iommu_mtlb_npgs += npages; 3593 req_max_p = req_base_p + iommu_p->iommu_mtlb_nreq++; 3594 req_max_p->dur_npg = npages; 3595 req_max_p->dur_base = dvma_pg; 3596 req_max_p->dur_flags = mp->dmai_flags & DMAI_FLAGS_VMEMCACHE; 3597 3598 3599 if (iommu_p->iommu_mtlb_npgs <= iommu_p->iommu_mtlb_maxpgs) 3600 goto done; 3601 3602 /* read TLB */ 3603 reg_base = iommu_p->iommu_pci_p->pci_address[0]; 3604 tag_p = (volatile uint64_t *) 3605 (reg_base + COMMON_IOMMU_TLB_TAG_DIAG_ACC_OFFSET); 3606 3607 for (i = 0; i < IOMMU_TLB_ENTRIES; i++) 3608 tlb_vpn[i] = tag_p[i] & SCHIZO_VPN_MASK; 3609 3610 /* for each request search the TLB for a matching address */ 3611 for (req_p = req_base_p; req_p <= req_max_p; req_p++) { 3612 dur_base = req_p->dur_base; 3613 dur_max = req_p->dur_base + req_p->dur_npg; 3614 3615 for (i = 0; i < IOMMU_TLB_ENTRIES; i++) { 3616 uint_t vpn = tlb_vpn[i]; 3617 if (vpn >= dur_base && vpn < dur_max) 3618 break; 3619 } 3620 if (i >= IOMMU_TLB_ENTRIES) { 3621 pci_vmem_do_free(iommu_p, 3622 (void *)IOMMU_PTOB(req_p->dur_base), 3623 req_p->dur_npg, req_p->dur_flags); 3624 iommu_p->iommu_mtlb_npgs -= req_p->dur_npg; 3625 continue; 3626 } 3627 /* if an empty slot exists */ 3628 if ((req_p - req_base_p) != preserv_count) 3629 *(req_base_p + preserv_count) = *req_p; 3630 preserv_count++; 3631 } 3632 3633 iommu_p->iommu_mtlb_nreq = preserv_count; 3634 done: 3635 mutex_exit(&iommu_p->iommu_mtlb_lock); 3636 } 3637 3638 void 3639 pci_vmem_free(iommu_t *iommu_p, ddi_dma_impl_t *mp, void *dvma_addr, 3640 size_t npages) 3641 { 3642 if (tm_mtlb_gc) 3643 tm_vmem_free(mp, iommu_p, 3644 (dvma_addr_t)IOMMU_BTOP((dvma_addr_t)dvma_addr), npages); 3645 else 3646 pci_vmem_do_free(iommu_p, dvma_addr, npages, 3647 (mp->dmai_flags & DMAI_FLAGS_VMEMCACHE)); 3648 } 3649 3650 /* 3651 * pci_iommu_bypass_end_configure 3652 * 3653 * Support for 42-bit bus width to SAFARI and JBUS in DVMA and 3654 * iommu bypass transfers: 3655 */ 3656 3657 dma_bypass_addr_t 3658 pci_iommu_bypass_end_configure(void) 3659 { 3660 3661 return ((dma_bypass_addr_t)SAFARI_JBUS_IOMMU_BYPASS_END); 3662 } 3663