1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * PCI nexus driver tunables 31 */ 32 33 #include <sys/types.h> 34 #include <sys/cmn_err.h> 35 #include <sys/time.h> 36 #include <sys/thread.h> 37 #include <sys/ksynch.h> 38 #include <sys/pci.h> 39 #include <sys/pci/pci_space.h> 40 41 42 /*LINTLIBRARY*/ 43 44 /* 45 * Used to disallow bypass requests for tomatillos ver <= 2.3 46 * 0 allow bypass, 1 disallow it. errata #75 47 */ 48 uint_t tomatillo_disallow_bypass = 0; 49 50 /* 51 * The three variables below enable a workround for 52 * tomatillo's micro TLB bug. errata #82 53 */ 54 uint_t tm_mtlb_maxpgs = 20; 55 uint_t tm_mtlb_gc = 0; /* for garbage collection */ 56 uint_t tm_mtlb_gc_manual = 0; /* for manual tuning */ 57 58 /* 59 * By initializing pci_interrupt_priorities_property to 1, the priority 60 * level of the interrupt handler for a PCI device can be defined via an 61 * "interrupt-priorities" property. This property is an array of integer 62 * values that have a one to one mapping the the "interrupts" property. 63 * For example, if a device's "interrupts" property was (1, 2) and its 64 * "interrupt-priorities" value was (5, 12), the handler for the first 65 * interrupt would run at cpu priority 5 and the second at priority 12. 66 * This would override the drivers standard mechanism for assigning 67 * priorities to interrupt handlers. 68 */ 69 uint_t pci_interrupt_priorities_property = 1; 70 71 /* 72 * By initializing pci_config_space_size_zero to 1, the driver will 73 * tolerate mapping requests for configuration space "reg" entries whose 74 * size is not zero. 75 */ 76 uint_t pci_config_space_size_zero = 1; 77 78 int pci_dvma_sync_before_unmap = 0; 79 int pci_sync_lock = 0; 80 81 int tomatillo_store_store_wrka = 0; 82 uint32_t pci_spurintr_duration = 60000000; /* One minute */ 83 uint64_t pci_spurintr_msgs = PCI_SPURINTR_MSG_DEFAULT; 84 85 /* 86 * The variable controls the default setting of the command register 87 * for pci devices. See init_child() for details. 88 * 89 * This flags also controls the setting of bits in the bridge control 90 * register pci to pci bridges. See init_child() for details. 91 */ 92 ushort_t pci_command_default = PCI_COMM_SERR_ENABLE | 93 PCI_COMM_WAIT_CYC_ENAB | 94 PCI_COMM_PARITY_DETECT | 95 PCI_COMM_ME | 96 PCI_COMM_MAE | 97 PCI_COMM_IO; 98 /* 99 * The following variable enables a workaround for the following obp bug: 100 * 101 * 1234181 - obp should set latency timer registers in pci 102 * configuration header 103 * 104 * Until this bug gets fixed in the obp, the following workaround should 105 * be enabled. 106 */ 107 uint_t pci_set_latency_timer_register = 1; 108 109 /* 110 * The following variable enables a workaround for an obp bug to be 111 * submitted. A bug requesting a workaround fof this problem has 112 * been filed: 113 * 114 * 1235094 - need workarounds on positron nexus drivers to set cache 115 * line size registers 116 * 117 * Until this bug gets fixed in the obp, the following workaround should 118 * be enabled. 119 */ 120 uint_t pci_set_cache_line_size_register = 1; 121 122 /* 123 * The following driver parameters are defined as variables to allow 124 * patching for debugging and tuning. Flags that can be set on a per 125 * PBM basis are bit fields where the PBM device instance number maps 126 * to the bit position. 127 */ 128 #ifdef DEBUG 129 uint64_t pci_debug_flags = 0; 130 uint_t pci_warn_pp0 = 0; 131 #endif 132 uint_t pci_disable_pass1_workarounds = 0; 133 uint_t pci_disable_pass2_workarounds = 0; 134 uint_t pci_disable_pass3_workarounds = 0; 135 uint_t pci_disable_plus_workarounds = 0; 136 uint_t pci_disable_default_workarounds = 0; 137 uint_t ecc_error_intr_enable = 1; 138 uint_t pci_sbh_error_intr_enable = (uint_t)-1; 139 uint_t pci_mmu_error_intr_enable = (uint_t)-1; 140 uint_t pci_stream_buf_enable = (uint_t)-1; 141 uint_t pci_stream_buf_exists = 1; 142 uint_t pci_rerun_disable = 0; 143 144 uint_t pci_enable_retry_arb = (uint_t)-1; 145 146 uint_t pci_bus_parking_enable = (uint_t)-1; 147 uint_t pci_error_intr_enable = (uint_t)-1; 148 uint_t pci_retry_disable = 0; 149 uint_t pci_retry_enable = 0; 150 uint_t pci_dwsync_disable = 0; 151 uint_t pci_intsync_disable = 0; 152 uint_t pci_b_arb_enable = 0xf; 153 uint_t pci_a_arb_enable = 0xf; 154 uint_t pci_ecc_afsr_retries = 100; /* XXX - what's a good value? */ 155 156 uint_t pci_intr_retry_intv = 5; /* for interrupt retry reg */ 157 uint8_t pci_latency_timer = 0x40; /* for pci latency timer reg */ 158 uint_t pci_panic_on_sbh_errors = 0; 159 uint_t pci_panic_on_fatal_errors = 1; /* should be 1 at beta */ 160 uint_t pci_thermal_intr_fatal = 1; /* thermal interrupts fatal */ 161 uint_t pci_buserr_interrupt = 1; /* safari buserr interrupt */ 162 uint_t pci_set_dto_value = 0; /* overwrite the prom settings? */ 163 uint_t pci_dto_value = 1; /* schizo consistent buf timeout PTO */ 164 uint_t pci_lock_sbuf = 0; 165 166 uint_t pci_use_contexts = 1; 167 uint_t pci_sc_use_contexts = 1; 168 uint_t pci_context_minpages = 2; 169 uint_t pci_ctx_flush_warn = CE_IGNORE; 170 uint_t pci_ctx_unsuccess_count = 0; /* unsuccessful ctx flush count */ 171 uint_t pci_ctx_no_active_flush = 0; /* cannot handle active ctx flush */ 172 uint_t pci_ctx_no_compat = 0; /* maintain compatibility */ 173 174 uint64_t pci_perr_enable = -1ull; 175 uint64_t pci_serr_enable = -1ull; 176 uint64_t pci_perr_fatal = -1ull; 177 uint64_t pci_serr_fatal = -1ull; 178 hrtime_t pci_intrpend_timeout = 5ll * NANOSEC; /* 5 seconds in nanoseconds */ 179 hrtime_t pci_sync_buf_timeout = 1ll * NANOSEC; /* 1 second in nanoseconds */ 180 hrtime_t pci_cdma_intr_timeout = 1ll * NANOSEC; /* consistent sync trigger */ 181 uint32_t pci_cdma_intr_count = 15; /* num of pci_cdma_intr_timeout cycles */ 182 183 uint32_t pci_dto_fault_warn = CE_WARN; /* set to CE_IGNORE for no messages */ 184 uint64_t pci_dto_intr_enable = 0; 185 uint64_t pci_dto_count = 0; 186 uint64_t pci_errtrig_pa = 0x0; 187 188 /* 189 * The following flag controls behavior of the ino handler routine 190 * when multiple interrupts are attached to a single ino. Typically 191 * this case would occur for the ino's assigned to the PCI bus slots 192 * with multi-function devices or bus bridges. 193 * 194 * Setting the flag to zero causes the ino handler routine to return 195 * after finding the first interrupt handler to claim the interrupt. 196 * 197 * Setting the flag to non-zero causes the ino handler routine to 198 * return after making one complete pass through the interrupt 199 * handlers. 200 */ 201 uint_t pci_check_all_handlers = 1; 202 203 /* 204 * The following value is the number of consecutive unclaimed interrupts that 205 * will be tolerated for a particular ino_p before the interrupt is deemed to 206 * be jabbering and is blocked. 207 */ 208 uint_t pci_unclaimed_intr_max = 20; 209 210 ulong_t pci_iommu_dvma_end = 0xfffffffful; 211 uint_t pci_lock_tlb = 0; 212 uint64_t pci_dvma_debug_on = 0; 213 uint64_t pci_dvma_debug_off = 0; 214 uint32_t pci_dvma_debug_rec = 512; 215 216 /* 217 * dvma address space allocation cache variables 218 */ 219 uint_t pci_dvma_page_cache_entries = 0x200; /* # of chunks (1 << bits) */ 220 uint_t pci_dvma_page_cache_clustsz = 0x8; /* # of pages per chunk */ 221 #ifdef PCI_DMA_PROF 222 uint_t pci_dvmaft_npages = 0; /* FT fail due npages */ 223 uint_t pci_dvmaft_limit = 0; /* FT fail due limits */ 224 uint_t pci_dvmaft_free = 0; /* FT free */ 225 uint_t pci_dvmaft_success = 0; /* FT success */ 226 uint_t pci_dvmaft_exhaust = 0; /* FT vmem fallback */ 227 uint_t pci_dvma_vmem_alloc = 0; /* vmem alloc */ 228 uint_t pci_dvma_vmem_xalloc = 0; /* vmem xalloc */ 229 uint_t pci_dvma_vmem_xfree = 0; /* vmem xfree */ 230 uint_t pci_dvma_vmem_free = 0; /* vmem free */ 231 #endif 232 uint_t pci_disable_fdvma = 0; 233 234 uint_t pci_iommu_ctx_lock_failure = 0; 235 236 /* 237 * This flag preserves prom iommu settings by copying prom TSB entries 238 * to corresponding kernel TSB entry locations. It should be removed 239 * after the interface properties from obp have become default. 240 */ 241 uint_t pci_preserve_iommu_tsb = 1; 242 243 /* 244 * memory callback list id callback list for kmem_alloc failure clients 245 */ 246 uintptr_t pci_kmem_clid = 0; 247 248 /* 249 * Perform a consistent-mode sync/flush during interrupt. 250 */ 251 uint_t pci_intr_dma_sync = 0; 252 253 /* 254 * This flag is used to enable max prefetch streaming cache mode 255 * feature of XMITS. 256 */ 257 uint_t pci_xmits_sc_max_prf = 0; 258 259 /* 260 * This flag is used to enable pcix error reporting in XMITS. 261 */ 262 uint64_t xmits_error_intr_enable = -1ull; 263 264 /* 265 * Enable parity error recovery for xmits 266 */ 267 uint_t xmits_perr_recov_int_enable = 0; 268 269 /* 270 * This flag controls whether or not DVMA remap support is 271 * enabled (currently, Schizo/XMITS only). 272 */ 273 int pci_dvma_remap_enabled = 0; 274 275 /* 276 * Serialize PCI relocations, since they are time critical. 277 */ 278 kthread_t *pci_reloc_thread = NULL; 279 kmutex_t pci_reloc_mutex; 280 kcondvar_t pci_reloc_cv; 281 int pci_reloc_presuspend = 0; 282 int pci_reloc_suspend = 0; 283 id_t pci_dvma_cbid; 284 id_t pci_fast_dvma_cbid; 285 int pci_dma_panic_on_leak = 0; 286 287 /* 288 * Set Outstanding Maximum Split Transactions. Legal settings are: 289 * 0 = 1 Outstanding Transacation, 1 = 2, 2 = 3, 3 = 4, 4 = 8, 5 = 12, 290 * 6 = 16, 7 = 32. 291 */ 292 uint_t xmits_max_transactions = 0; 293 294 /* 295 * Set Max Memory Read Byte Count. Legal settings are: 296 * 0 = 512 Max Memory Read Bytes, 1 = 1024, 2 = 2048, 3 = 4096. 297 */ 298 uint_t xmits_max_read_bytes = 0; 299