1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * PCI PBM implementation: 31 * initialization 32 * Bus error interrupt handler 33 */ 34 35 #include <sys/types.h> 36 #include <sys/kmem.h> 37 #include <sys/spl.h> 38 #include <sys/sysmacros.h> 39 #include <sys/sunddi.h> 40 #include <sys/fm/protocol.h> 41 #include <sys/fm/util.h> 42 #include <sys/machsystm.h> /* ldphysio() */ 43 #include <sys/async.h> 44 #include <sys/ddi_impldefs.h> 45 #include <sys/ontrap.h> 46 #include <sys/pci/pci_obj.h> 47 #include <sys/membar.h> 48 #include <sys/ivintr.h> 49 50 /*LINTLIBRARY*/ 51 52 static uint_t pbm_error_intr(caddr_t a); 53 54 /* The nexus interrupt priority values */ 55 int pci_pil[] = {14, 14, 14, 14, 14, 14}; 56 void 57 pbm_create(pci_t *pci_p) 58 { 59 pbm_t *pbm_p; 60 int i, len; 61 int nrange = pci_p->pci_ranges_length / sizeof (pci_ranges_t); 62 dev_info_t *dip = pci_p->pci_dip; 63 pci_ranges_t *rangep = pci_p->pci_ranges; 64 uint64_t base_addr, last_addr; 65 66 #ifdef lint 67 dip = dip; 68 #endif 69 70 /* 71 * Allocate a state structure for the PBM and cross-link it 72 * to its per pci node state structure. 73 */ 74 pbm_p = (pbm_t *)kmem_zalloc(sizeof (pbm_t), KM_SLEEP); 75 pci_p->pci_pbm_p = pbm_p; 76 pbm_p->pbm_pci_p = pci_p; 77 78 len = snprintf(pbm_p->pbm_nameinst_str, 79 sizeof (pbm_p->pbm_nameinst_str), 80 "%s%d", NAMEINST(dip)); 81 pbm_p->pbm_nameaddr_str = pbm_p->pbm_nameinst_str + ++len; 82 (void) snprintf(pbm_p->pbm_nameaddr_str, 83 sizeof (pbm_p->pbm_nameinst_str) - len, 84 "%s@%s", NAMEADDR(dip)); 85 86 pci_pbm_setup(pbm_p); 87 88 /* 89 * Get this pbm's mem32 and mem64 segments to determine whether 90 * a dma object originates from ths pbm. i.e. dev to dev dma 91 */ 92 /* Init all of our boundaries */ 93 base_addr = -1ull; 94 last_addr = 0ull; 95 96 for (i = 0; i < nrange; i++, rangep++) { 97 uint32_t rng_type = rangep->child_high & PCI_ADDR_MASK; 98 if (rng_type == PCI_ADDR_MEM32 || rng_type == PCI_ADDR_MEM64) { 99 uint64_t rng_addr, rng_size; 100 101 rng_addr = (uint64_t)rangep->parent_high << 32; 102 rng_addr |= (uint64_t)rangep->parent_low; 103 rng_size = (uint64_t)rangep->size_high << 32; 104 rng_size |= (uint64_t)rangep->size_low; 105 base_addr = MIN(rng_addr, base_addr); 106 last_addr = MAX(rng_addr + rng_size, last_addr); 107 } 108 } 109 pbm_p->pbm_base_pfn = mmu_btop(base_addr); 110 pbm_p->pbm_last_pfn = mmu_btop(last_addr); 111 112 DEBUG4(DBG_ATTACH, dip, 113 "pbm_create: ctrl=%x, afsr=%x, afar=%x, diag=%x\n", 114 pbm_p->pbm_ctrl_reg, pbm_p->pbm_async_flt_status_reg, 115 pbm_p->pbm_async_flt_addr_reg, pbm_p->pbm_diag_reg); 116 DEBUG1(DBG_ATTACH, dip, "pbm_create: conf=%x\n", 117 pbm_p->pbm_config_header); 118 119 /* 120 * Register a function to disable pbm error interrupts during a panic. 121 */ 122 bus_func_register(BF_TYPE_ERRDIS, 123 (busfunc_t)pbm_disable_pci_errors, pbm_p); 124 125 /* 126 * create the interrupt-priorities property if it doesn't 127 * already exist to provide a hint as to the PIL level for 128 * our interrupt. 129 */ 130 if (ddi_getproplen(DDI_DEV_T_ANY, dip, 131 DDI_PROP_DONTPASS, "interrupt-priorities", 132 &len) != DDI_PROP_SUCCESS) { 133 /* Create the interrupt-priorities property. */ 134 (void) ddi_prop_create(DDI_DEV_T_NONE, dip, 135 DDI_PROP_CANSLEEP, "interrupt-priorities", 136 (caddr_t)pci_pil, sizeof (pci_pil)); 137 } 138 139 pbm_configure(pbm_p); 140 141 /* 142 * Determine if we need to apply the Sun Fire 15k AXQ/PIO 143 * workaround. 144 */ 145 pci_axq_pio_limit(pbm_p); 146 } 147 148 int 149 pbm_register_intr(pbm_t *pbm_p) 150 { 151 pci_t *pci_p = pbm_p->pbm_pci_p; 152 uint32_t mondo; 153 int r = DDI_SUCCESS; 154 155 ib_nintr_clear(pci_p->pci_ib_p, pci_p->pci_inos[CBNINTR_PBM]); 156 157 /* 158 * Install the PCI error interrupt handler. 159 */ 160 mondo = IB_INO_TO_MONDO(pci_p->pci_ib_p, pci_p->pci_inos[CBNINTR_PBM]); 161 mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo); 162 163 VERIFY(add_ivintr(mondo, pci_pil[CBNINTR_PBM], pbm_error_intr, 164 (caddr_t)pci_p, NULL) == 0); 165 166 pbm_p->pbm_iblock_cookie = (void *)(uintptr_t)pci_pil[CBNINTR_PBM]; 167 168 /* 169 * Create the pokefault mutex at the PIL below the error interrupt. 170 */ 171 mutex_init(&pbm_p->pbm_pokefault_mutex, NULL, MUTEX_DRIVER, 172 (void *)(uintptr_t)ipltospl(spltoipl( 173 (int)(uintptr_t)pbm_p->pbm_iblock_cookie) - 1)); 174 175 if (!r) 176 r = pci_pbm_add_intr(pci_p); 177 return (PCI_ATTACH_RETCODE(PCI_PBM_OBJ, PCI_OBJ_INTR_ADD, r)); 178 } 179 180 void 181 pbm_destroy(pci_t *pci_p) 182 { 183 pbm_t *pbm_p = pci_p->pci_pbm_p; 184 ib_t *ib_p = pci_p->pci_ib_p; 185 uint32_t mondo; 186 187 DEBUG0(DBG_DETACH, pci_p->pci_dip, "pbm_destroy:\n"); 188 189 mondo = IB_INO_TO_MONDO(pci_p->pci_ib_p, pci_p->pci_inos[CBNINTR_PBM]); 190 mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo); 191 192 /* 193 * Free the pokefault mutex. 194 */ 195 mutex_destroy(&pbm_p->pbm_pokefault_mutex); 196 197 /* 198 * Remove the error interrupt and consistent dma sync handler. 199 */ 200 intr_dist_rem(pbm_intr_dist, pbm_p); 201 pci_pbm_rem_intr(pci_p); 202 ib_intr_disable(ib_p, pci_p->pci_inos[CBNINTR_PBM], IB_INTR_WAIT); 203 rem_ivintr(mondo, NULL); 204 205 /* 206 * Remove the error disable function. 207 */ 208 bus_func_unregister(BF_TYPE_ERRDIS, 209 (busfunc_t)pbm_disable_pci_errors, pbm_p); 210 211 pci_pbm_teardown(pbm_p); 212 213 /* 214 * Free the pbm state structure. 215 */ 216 kmem_free(pbm_p, sizeof (pbm_t)); 217 pci_p->pci_pbm_p = NULL; 218 } 219 220 static uint_t 221 pbm_error_intr(caddr_t a) 222 { 223 pci_t *pci_p = (pci_t *)a; 224 pbm_t *pbm_p = pci_p->pci_pbm_p; 225 ddi_fm_error_t derr; 226 int err = DDI_FM_OK; 227 on_trap_data_t *otp = pbm_p->pbm_ontrap_data; 228 229 bzero(&derr, sizeof (ddi_fm_error_t)); 230 derr.fme_version = DDI_FME_VERSION; 231 mutex_enter(&pci_p->pci_common_p->pci_fm_mutex); 232 if (pbm_p->pbm_excl_handle != NULL) { 233 /* 234 * cautious write protection, protected from all errors. 235 */ 236 ASSERT(MUTEX_HELD(&pbm_p->pbm_pokefault_mutex)); 237 ddi_fm_acc_err_get(pbm_p->pbm_excl_handle, &derr, 238 DDI_FME_VERSION); 239 ASSERT(derr.fme_flag == DDI_FM_ERR_EXPECTED); 240 derr.fme_acc_handle = pbm_p->pbm_excl_handle; 241 err = pci_pbm_err_handler(pci_p->pci_dip, &derr, (void *)pci_p, 242 PCI_INTR_CALL); 243 } else if ((otp != NULL) && (otp->ot_prot & OT_DATA_ACCESS)) { 244 /* 245 * ddi_poke protection, check nexus and children for 246 * expected errors. 247 */ 248 otp->ot_trap |= OT_DATA_ACCESS; 249 membar_sync(); 250 derr.fme_flag = DDI_FM_ERR_POKE; 251 err = pci_pbm_err_handler(pci_p->pci_dip, &derr, (void *)pci_p, 252 PCI_INTR_CALL); 253 } else if (pci_check_error(pci_p) != 0) { 254 /* 255 * unprotected error, check for all errors. 256 */ 257 if (pci_errtrig_pa) 258 (void) ldphysio(pci_errtrig_pa); 259 derr.fme_flag = DDI_FM_ERR_UNEXPECTED; 260 err = pci_pbm_err_handler(pci_p->pci_dip, &derr, (void *)pci_p, 261 PCI_INTR_CALL); 262 } 263 264 if (err == DDI_FM_FATAL) { 265 if (pci_panic_on_fatal_errors) { 266 mutex_exit(&pci_p->pci_common_p->pci_fm_mutex); 267 fm_panic("%s-%d: Fatal PCI bus error(s)\n", 268 ddi_driver_name(pci_p->pci_dip), 269 ddi_get_instance(pci_p->pci_dip)); 270 } 271 } 272 273 mutex_exit(&pci_p->pci_common_p->pci_fm_mutex); 274 ib_nintr_clear(pci_p->pci_ib_p, pci_p->pci_inos[CBNINTR_PBM]); 275 return (DDI_INTR_CLAIMED); 276 } 277 278 void 279 pbm_suspend(pbm_t *pbm_p) 280 { 281 pci_t *pci_p = pbm_p->pbm_pci_p; 282 ib_ino_t ino = pci_p->pci_inos[CBNINTR_PBM]; 283 pbm_p->pbm_imr_save = *ib_intr_map_reg_addr(pci_p->pci_ib_p, ino); 284 285 pci_pbm_suspend(pci_p); 286 } 287 288 void 289 pbm_resume(pbm_t *pbm_p) 290 { 291 pci_t *pci_p = pbm_p->pbm_pci_p; 292 ib_ino_t ino = pci_p->pci_inos[CBNINTR_PBM]; 293 294 ib_nintr_clear(pci_p->pci_ib_p, ino); 295 *ib_intr_map_reg_addr(pci_p->pci_ib_p, ino) = pbm_p->pbm_imr_save; 296 297 pci_pbm_resume(pci_p); 298 } 299 300 void 301 pbm_intr_dist(void *arg) 302 { 303 pbm_t *pbm_p = (pbm_t *)arg; 304 pci_t *pci_p = pbm_p->pbm_pci_p; 305 ib_t *ib_p = pci_p->pci_ib_p; 306 ib_ino_t ino = IB_MONDO_TO_INO(pci_p->pci_inos[CBNINTR_PBM]); 307 308 mutex_enter(&ib_p->ib_intr_lock); 309 ib_intr_dist_nintr(ib_p, ino, ib_intr_map_reg_addr(ib_p, ino)); 310 pci_pbm_intr_dist(pbm_p); 311 mutex_exit(&ib_p->ib_intr_lock); 312 } 313 314 /* 315 * Function used to log PBM AFSR register bits and to lookup and fault 316 * handle associated with PBM AFAR register. Called by pci_pbm_err_handler with 317 * pci_fm_mutex held. 318 */ 319 int 320 pbm_afsr_report(dev_info_t *dip, uint64_t fme_ena, pbm_errstate_t *pbm_err_p) 321 { 322 int fatal = 0; 323 int ret = 0; 324 pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 325 pci_common_t *cmn_p = pci_p->pci_common_p; 326 pci_target_err_t tgt_err; 327 328 ASSERT(MUTEX_HELD(&cmn_p->pci_fm_mutex)); 329 330 pbm_err_p->pbm_pri = PBM_PRIMARY; 331 (void) pci_pbm_classify(pbm_err_p); 332 333 pci_format_addr(dip, &pbm_err_p->pbm_pci.pci_pa, pbm_err_p->pbm_afsr); 334 335 if (pbm_err_p->pbm_log == FM_LOG_PBM) 336 pbm_ereport_post(dip, fme_ena, pbm_err_p); 337 338 /* 339 * Lookup and fault errant handle 340 */ 341 if (((ret = pci_handle_lookup(dip, ACC_HANDLE, fme_ena, 342 (void *)&pbm_err_p->pbm_pci.pci_pa)) 343 == DDI_FM_FATAL) || (ret == DDI_FM_UNKNOWN)) { 344 fatal++; 345 } 346 347 /* 348 * queue target ereport if appropriate 349 */ 350 if (pbm_err_p->pbm_terr_class) { 351 tgt_err.tgt_err_ena = fme_ena; 352 tgt_err.tgt_err_class = pbm_err_p->pbm_terr_class; 353 if (pbm_err_p->pbm_log == FM_LOG_PCI) 354 tgt_err.tgt_bridge_type = "pci"; 355 else 356 tgt_err.tgt_bridge_type = pbm_err_p->pbm_bridge_type; 357 tgt_err.tgt_err_addr = pbm_err_p->pbm_pci.pci_pa; 358 errorq_dispatch(pci_target_queue, (void *)&tgt_err, 359 sizeof (pci_target_err_t), ERRORQ_ASYNC); 360 } 361 362 /* 363 * We are currently not dealing with the multiple error 364 * case, for any secondary errors we will panic. 365 */ 366 pbm_err_p->pbm_pri = PBM_SECONDARY; 367 if (pci_pbm_classify(pbm_err_p)) { 368 fatal++; 369 if (pbm_err_p->pbm_log == FM_LOG_PBM) 370 pbm_ereport_post(dip, fme_ena, pbm_err_p); 371 } 372 373 if (fatal) 374 return (DDI_FM_FATAL); 375 376 return (DDI_FM_NONFATAL); 377 } 378