1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * PCI nexus interrupt handling: 30 * PCI device interrupt handler wrapper 31 * pil lookup routine 32 * PCI device interrupt related initchild code 33 */ 34 35 #include <sys/types.h> 36 #include <sys/kmem.h> 37 #include <sys/async.h> 38 #include <sys/spl.h> 39 #include <sys/sunddi.h> 40 #include <sys/machsystm.h> /* e_ddi_nodeid_to_dip() */ 41 #include <sys/ddi_impldefs.h> 42 #include <sys/pci/pci_obj.h> 43 #include <sys/sdt.h> 44 #include <sys/clock.h> 45 46 #ifdef _STARFIRE 47 #include <sys/starfire.h> 48 #endif /* _STARFIRE */ 49 50 /* 51 * interrupt jabber: 52 * 53 * When an interrupt line is jabbering, every time the state machine for the 54 * associated ino is idled, a new mondo will be sent and the ino will go into 55 * the pending state again. The mondo will cause a new call to 56 * pci_intr_wrapper() which normally idles the ino's state machine which would 57 * precipitate another trip round the loop. 58 * The loop can be broken by preventing the ino's state machine from being 59 * idled when an interrupt line is jabbering. See the comment at the 60 * beginning of pci_intr_wrapper() explaining how the 'interrupt jabber 61 * protection' code does this. 62 */ 63 64 /*LINTLIBRARY*/ 65 66 #ifdef NOT_DEFINED 67 /* 68 * This array is used to determine the sparc PIL at the which the 69 * handler for a given INO will execute. This table is for onboard 70 * devices only. A different scheme will be used for plug-in cards. 71 */ 72 73 uint_t ino_to_pil[] = { 74 75 /* pil */ /* ino */ 76 77 0, 0, 0, 0, /* 0x00 - 0x03: bus A slot 0 int#A, B, C, D */ 78 0, 0, 0, 0, /* 0x04 - 0x07: bus A slot 1 int#A, B, C, D */ 79 0, 0, 0, 0, /* 0x08 - 0x0B: unused */ 80 0, 0, 0, 0, /* 0x0C - 0x0F: unused */ 81 82 0, 0, 0, 0, /* 0x10 - 0x13: bus B slot 0 int#A, B, C, D */ 83 0, 0, 0, 0, /* 0x14 - 0x17: bus B slot 1 int#A, B, C, D */ 84 0, 0, 0, 0, /* 0x18 - 0x1B: bus B slot 2 int#A, B, C, D */ 85 4, 0, 0, 0, /* 0x1C - 0x1F: bus B slot 3 int#A, B, C, D */ 86 87 4, /* 0x20: SCSI */ 88 6, /* 0x21: ethernet */ 89 3, /* 0x22: parallel port */ 90 9, /* 0x23: audio record */ 91 9, /* 0x24: audio playback */ 92 14, /* 0x25: power fail */ 93 4, /* 0x26: 2nd SCSI */ 94 8, /* 0x27: floppy */ 95 14, /* 0x28: thermal warning */ 96 12, /* 0x29: keyboard */ 97 12, /* 0x2A: mouse */ 98 12, /* 0x2B: serial */ 99 0, /* 0x2C: timer/counter 0 */ 100 0, /* 0x2D: timer/counter 1 */ 101 14, /* 0x2E: uncorrectable ECC errors */ 102 14, /* 0x2F: correctable ECC errors */ 103 14, /* 0x30: PCI bus A error */ 104 14, /* 0x31: PCI bus B error */ 105 14, /* 0x32: power management wakeup */ 106 14, /* 0x33 */ 107 14, /* 0x34 */ 108 14, /* 0x35 */ 109 14, /* 0x36 */ 110 14, /* 0x37 */ 111 14, /* 0x38 */ 112 14, /* 0x39 */ 113 14, /* 0x3a */ 114 14, /* 0x3b */ 115 14, /* 0x3c */ 116 14, /* 0x3d */ 117 14, /* 0x3e */ 118 14, /* 0x3f */ 119 14 /* 0x40 */ 120 }; 121 #endif /* NOT_DEFINED */ 122 123 124 #define PCI_SIMBA_VENID 0x108e /* vendor id for simba */ 125 #define PCI_SIMBA_DEVID 0x5000 /* device id for simba */ 126 127 /* 128 * map_pcidev_cfg_reg - create mapping to pci device configuration registers 129 * if we have a simba AND a pci to pci bridge along the 130 * device path. 131 * Called with corresponding mutexes held!! 132 * 133 * XXX XXX XXX The purpose of this routine is to overcome a hardware 134 * defect in Sabre CPU and Simba bridge configuration 135 * which does not drain DMA write data stalled in 136 * PCI to PCI bridges (such as the DEC bridge) beyond 137 * Simba. This routine will setup the data structures 138 * to allow the pci_intr_wrapper to perform a manual 139 * drain data operation before passing the control to 140 * interrupt handlers of device drivers. 141 * return value: 142 * DDI_SUCCESS 143 * DDI_FAILURE if unable to create mapping 144 */ 145 static int 146 map_pcidev_cfg_reg(dev_info_t *dip, dev_info_t *rdip, ddi_acc_handle_t *hdl_p) 147 { 148 dev_info_t *cdip; 149 dev_info_t *pci_dip = NULL; 150 pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 151 int simba_found = 0, pci_bridge_found = 0; 152 153 for (cdip = rdip; cdip && cdip != dip; cdip = ddi_get_parent(cdip)) { 154 ddi_acc_handle_t config_handle; 155 uint32_t vendor_id = ddi_getprop(DDI_DEV_T_ANY, cdip, 156 DDI_PROP_DONTPASS, "vendor-id", 0xffff); 157 158 DEBUG4(DBG_A_INTX, pci_p->pci_dip, 159 "map dev cfg reg for %s%d: @%s%d\n", 160 ddi_driver_name(rdip), ddi_get_instance(rdip), 161 ddi_driver_name(cdip), ddi_get_instance(cdip)); 162 163 if (ddi_prop_exists(DDI_DEV_T_ANY, cdip, DDI_PROP_DONTPASS, 164 "no-dma-interrupt-sync")) 165 continue; 166 167 /* continue to search up-stream if not a PCI device */ 168 if (vendor_id == 0xffff) 169 continue; 170 171 /* record the deepest pci device */ 172 if (!pci_dip) 173 pci_dip = cdip; 174 175 /* look for simba */ 176 if (vendor_id == PCI_SIMBA_VENID) { 177 uint32_t device_id = ddi_getprop(DDI_DEV_T_ANY, 178 cdip, DDI_PROP_DONTPASS, "device-id", -1); 179 if (device_id == PCI_SIMBA_DEVID) { 180 simba_found = 1; 181 DEBUG0(DBG_A_INTX, pci_p->pci_dip, 182 "\tFound simba\n"); 183 continue; /* do not check bridge if simba */ 184 } 185 } 186 187 /* look for pci to pci bridge */ 188 if (pci_config_setup(cdip, &config_handle) != DDI_SUCCESS) { 189 cmn_err(CE_WARN, 190 "%s%d: can't get brdg cfg space for %s%d\n", 191 ddi_driver_name(dip), ddi_get_instance(dip), 192 ddi_driver_name(cdip), ddi_get_instance(cdip)); 193 return (DDI_FAILURE); 194 } 195 if (pci_config_get8(config_handle, PCI_CONF_BASCLASS) 196 == PCI_CLASS_BRIDGE) { 197 DEBUG0(DBG_A_INTX, pci_p->pci_dip, 198 "\tFound PCI to xBus bridge\n"); 199 pci_bridge_found = 1; 200 } 201 pci_config_teardown(&config_handle); 202 } 203 204 if (!pci_bridge_found) 205 return (DDI_SUCCESS); 206 if (!simba_found && (CHIP_TYPE(pci_p) < PCI_CHIP_SCHIZO)) 207 return (DDI_SUCCESS); 208 if (pci_config_setup(pci_dip, hdl_p) != DDI_SUCCESS) { 209 cmn_err(CE_WARN, "%s%d: can not get config space for %s%d\n", 210 ddi_driver_name(dip), ddi_get_instance(dip), 211 ddi_driver_name(cdip), ddi_get_instance(cdip)); 212 return (DDI_FAILURE); 213 } 214 return (DDI_SUCCESS); 215 } 216 217 /* 218 * If the unclaimed interrupt count has reached the limit set by 219 * pci_unclaimed_intr_max within the time limit, then all interrupts 220 * on this ino is blocked by not idling the interrupt state machine. 221 */ 222 static int 223 pci_spurintr(ib_ino_info_t *ino_p) { 224 int i; 225 ih_t *ih_p = ino_p->ino_ih_start; 226 pci_t *pci_p = ino_p->ino_ib_p->ib_pci_p; 227 char *err_fmt_str; 228 229 if (ino_p->ino_unclaimed > pci_unclaimed_intr_max) 230 return (DDI_INTR_CLAIMED); 231 232 if (!ino_p->ino_unclaimed) 233 ino_p->ino_spurintr_begin = ddi_get_lbolt(); 234 235 ino_p->ino_unclaimed++; 236 237 if (ino_p->ino_unclaimed <= pci_unclaimed_intr_max) 238 goto clear; 239 240 if (drv_hztousec(ddi_get_lbolt() - ino_p->ino_spurintr_begin) 241 > pci_spurintr_duration) { 242 ino_p->ino_unclaimed = 0; 243 goto clear; 244 } 245 err_fmt_str = "%s%d: ino 0x%x blocked"; 246 goto warn; 247 clear: 248 IB_INO_INTR_CLEAR(ino_p->ino_clr_reg); /* clear the pending state */ 249 if (!pci_spurintr_msgs) /* tomatillo errata #71 spurious mondo */ 250 return (DDI_INTR_CLAIMED); 251 252 err_fmt_str = "!%s%d: spurious interrupt from ino 0x%x"; 253 warn: 254 cmn_err(CE_WARN, err_fmt_str, NAMEINST(pci_p->pci_dip), ino_p->ino_ino); 255 for (i = 0; i < ino_p->ino_ih_size; i++, ih_p = ih_p->ih_next) 256 cmn_err(CE_CONT, "!%s-%d#%x ", NAMEINST(ih_p->ih_dip), 257 ih_p->ih_inum); 258 cmn_err(CE_CONT, "!\n"); 259 return (DDI_INTR_CLAIMED); 260 } 261 262 /* 263 * pci_intr_wrapper 264 * 265 * This routine is used as wrapper around interrupt handlers installed by child 266 * device drivers. This routine invokes the driver interrupt handlers and 267 * examines the return codes. 268 * There is a count of unclaimed interrupts kept on a per-ino basis. If at 269 * least one handler claims the interrupt then the counter is halved and the 270 * interrupt state machine is idled. If no handler claims the interrupt then 271 * the counter is incremented by one and the state machine is idled. 272 * If the count ever reaches the limit value set by pci_unclaimed_intr_max 273 * then the interrupt state machine is not idled thus preventing any further 274 * interrupts on that ino. The state machine will only be idled again if a 275 * handler is subsequently added or removed. 276 * 277 * return value: DDI_INTR_CLAIMED if any handlers claimed the interrupt, 278 * DDI_INTR_UNCLAIMED otherwise. 279 */ 280 281 extern uint64_t intr_get_time(void); 282 283 uint_t 284 pci_intr_wrapper(caddr_t arg) 285 { 286 ib_ino_info_t *ino_p = (ib_ino_info_t *)arg; 287 uint_t result = 0, r; 288 pci_t *pci_p = ino_p->ino_ib_p->ib_pci_p; 289 pbm_t *pbm_p = pci_p->pci_pbm_p; 290 ih_t *ih_p = ino_p->ino_ih_start; 291 int i; 292 293 for (i = 0; i < ino_p->ino_ih_size; i++, ih_p = ih_p->ih_next) { 294 dev_info_t *dip = ih_p->ih_dip; 295 uint_t (*handler)() = ih_p->ih_handler; 296 caddr_t arg1 = ih_p->ih_handler_arg1; 297 caddr_t arg2 = ih_p->ih_handler_arg2; 298 ddi_acc_handle_t cfg_hdl = ih_p->ih_config_handle; 299 300 if (pci_intr_dma_sync && cfg_hdl && pbm_p->pbm_sync_reg_pa) { 301 (void) pci_config_get16(cfg_hdl, PCI_CONF_VENID); 302 pci_pbm_dma_sync(pbm_p, ino_p->ino_ino); 303 } 304 305 if (ih_p->ih_intr_state == PCI_INTR_STATE_DISABLE) { 306 DEBUG3(DBG_INTR, pci_p->pci_dip, 307 "pci_intr_wrapper: %s%d interrupt %d is disabled\n", 308 ddi_driver_name(dip), ddi_get_instance(dip), 309 ino_p->ino_ino); 310 311 continue; 312 } 313 314 DTRACE_PROBE4(interrupt__start, dev_info_t, dip, 315 void *, handler, caddr_t, arg1, caddr_t, arg2); 316 317 r = (*handler)(arg1, arg2); 318 319 /* 320 * Account for time used by this interrupt. Protect against 321 * conflicting writes to ih_ticks from ib_intr_dist_all() by 322 * using atomic ops. 323 */ 324 325 if (ino_p->ino_pil <= LOCK_LEVEL) 326 atomic_add_64(&ih_p->ih_ticks, intr_get_time()); 327 328 DTRACE_PROBE4(interrupt__complete, dev_info_t, dip, 329 void *, handler, caddr_t, arg1, int, r); 330 331 result += r; 332 333 if (pci_check_all_handlers) 334 continue; 335 if (result) 336 break; 337 } 338 339 if (!result) 340 return (pci_spurintr(ino_p)); 341 342 ino_p->ino_unclaimed = 0; 343 IB_INO_INTR_CLEAR(ino_p->ino_clr_reg); /* clear the pending state */ 344 345 return (DDI_INTR_CLAIMED); 346 } 347 348 dev_info_t * 349 get_my_childs_dip(dev_info_t *dip, dev_info_t *rdip) 350 { 351 dev_info_t *cdip = rdip; 352 353 for (; ddi_get_parent(cdip) != dip; cdip = ddi_get_parent(cdip)) 354 ; 355 356 return (cdip); 357 } 358 359 /* default class to pil value mapping */ 360 pci_class_val_t pci_default_pil [] = { 361 {0x000000, 0xff0000, 0x1}, /* Class code for pre-2.0 devices */ 362 {0x010000, 0xff0000, 0x4}, /* Mass Storage Controller */ 363 {0x020000, 0xff0000, 0x6}, /* Network Controller */ 364 {0x030000, 0xff0000, 0x9}, /* Display Controller */ 365 {0x040000, 0xff0000, 0x9}, /* Multimedia Controller */ 366 {0x050000, 0xff0000, 0xb}, /* Memory Controller */ 367 {0x060000, 0xff0000, 0xb}, /* Bridge Controller */ 368 {0x0c0000, 0xffff00, 0x9}, /* Serial Bus, FireWire (IEEE 1394) */ 369 {0x0c0100, 0xffff00, 0x4}, /* Serial Bus, ACCESS.bus */ 370 {0x0c0200, 0xffff00, 0x4}, /* Serial Bus, SSA */ 371 {0x0c0300, 0xffff00, 0x9}, /* Serial Bus Universal Serial Bus */ 372 {0x0c0400, 0xffff00, 0x6}, /* Serial Bus, Fibre Channel */ 373 {0x0c0600, 0xffff00, 0x6} /* Serial Bus, Infiniband */ 374 }; 375 376 /* 377 * Default class to intr_weight value mapping (% of CPU). A driver.conf 378 * entry on or above the pci node like 379 * 380 * pci-class-intr-weights= 0x020000, 0xff0000, 30; 381 * 382 * can be used to augment or override entries in the default table below. 383 * 384 * NB: The values below give NICs preference on redistribution, and provide 385 * NICs some isolation from other interrupt sources. We need better interfaces 386 * that allow the NIC driver to identify a specific NIC instance as high 387 * bandwidth, and thus deserving of separation from other low bandwidth 388 * NICs additional isolation from other interrupt sources. 389 * 390 * NB: We treat Infiniband like a NIC. 391 */ 392 pci_class_val_t pci_default_intr_weight [] = { 393 {0x020000, 0xff0000, 35}, /* Network Controller */ 394 {0x010000, 0xff0000, 10}, /* Mass Storage Controller */ 395 {0x0c0400, 0xffff00, 10}, /* Serial Bus, Fibre Channel */ 396 {0x0c0600, 0xffff00, 50} /* Serial Bus, Infiniband */ 397 }; 398 399 static uint32_t 400 pci_match_class_val(uint32_t key, pci_class_val_t *rec_p, int nrec, 401 uint32_t default_val) 402 { 403 int i; 404 405 for (i = 0; i < nrec; rec_p++, i++) { 406 if ((rec_p->class_code & rec_p->class_mask) == 407 (key & rec_p->class_mask)) 408 return (rec_p->class_val); 409 } 410 411 return (default_val); 412 } 413 414 /* 415 * Return the configuration value, based on class code and sub class code, 416 * from the specified property based or default pci_class_val_t table. 417 */ 418 uint32_t 419 pci_class_to_val(dev_info_t *rdip, char *property_name, pci_class_val_t *rec_p, 420 int nrec, uint32_t default_val) 421 { 422 int property_len; 423 uint32_t class_code; 424 pci_class_val_t *conf; 425 uint32_t val = default_val; 426 427 /* 428 * Use the "class-code" property to get the base and sub class 429 * codes for the requesting device. 430 */ 431 class_code = (uint32_t)ddi_prop_get_int(DDI_DEV_T_ANY, rdip, 432 DDI_PROP_DONTPASS, "class-code", -1); 433 434 if (class_code == -1) 435 return (val); 436 437 /* look up the val from the default table */ 438 val = pci_match_class_val(class_code, rec_p, nrec, val); 439 440 441 /* see if there is a more specific property specified value */ 442 if (ddi_getlongprop(DDI_DEV_T_ANY, rdip, DDI_PROP_NOTPROM, 443 property_name, (caddr_t)&conf, &property_len)) 444 return (val); 445 446 if ((property_len % sizeof (pci_class_val_t)) == 0) 447 val = pci_match_class_val(class_code, conf, 448 property_len / sizeof (pci_class_val_t), val); 449 kmem_free(conf, property_len); 450 return (val); 451 } 452 453 /* pci_class_to_pil: return the pil for a given PCI device. */ 454 uint32_t 455 pci_class_to_pil(dev_info_t *rdip) 456 { 457 uint32_t pil; 458 459 /* default pil is 0 (uninitialized) */ 460 pil = pci_class_to_val(rdip, 461 "pci-class-priorities", pci_default_pil, 462 sizeof (pci_default_pil) / sizeof (pci_class_val_t), 0); 463 464 /* range check the result */ 465 if (pil >= 0xf) 466 pil = 0; 467 468 return (pil); 469 } 470 471 /* pci_class_to_intr_weight: return the intr_weight for a given PCI device. */ 472 int32_t 473 pci_class_to_intr_weight(dev_info_t *rdip) 474 { 475 int32_t intr_weight; 476 477 /* default weight is 0% */ 478 intr_weight = pci_class_to_val(rdip, 479 "pci-class-intr-weights", pci_default_intr_weight, 480 sizeof (pci_default_intr_weight) / sizeof (pci_class_val_t), 0); 481 482 /* range check the result */ 483 if (intr_weight < 0) 484 intr_weight = 0; 485 if (intr_weight > 1000) 486 intr_weight = 1000; 487 488 return (intr_weight); 489 } 490 491 static struct { 492 kstat_named_t pciintr_ks_name; 493 kstat_named_t pciintr_ks_type; 494 kstat_named_t pciintr_ks_cpu; 495 kstat_named_t pciintr_ks_pil; 496 kstat_named_t pciintr_ks_time; 497 kstat_named_t pciintr_ks_ino; 498 kstat_named_t pciintr_ks_cookie; 499 kstat_named_t pciintr_ks_devpath; 500 kstat_named_t pciintr_ks_buspath; 501 } pciintr_ks_template = { 502 { "name", KSTAT_DATA_CHAR }, 503 { "type", KSTAT_DATA_CHAR }, 504 { "cpu", KSTAT_DATA_UINT64 }, 505 { "pil", KSTAT_DATA_UINT64 }, 506 { "time", KSTAT_DATA_UINT64 }, 507 { "ino", KSTAT_DATA_UINT64 }, 508 { "cookie", KSTAT_DATA_UINT64 }, 509 { "devpath", KSTAT_DATA_STRING }, 510 { "buspath", KSTAT_DATA_STRING }, 511 }; 512 static uint32_t pciintr_ks_instance; 513 static char ih_devpath[MAXPATHLEN]; 514 static char ih_buspath[MAXPATHLEN]; 515 516 kmutex_t pciintr_ks_template_lock; 517 518 int 519 pci_ks_update(kstat_t *ksp, int rw) 520 { 521 ih_t *ih_p = ksp->ks_private; 522 int maxlen = sizeof (pciintr_ks_template.pciintr_ks_name.value.c); 523 ib_t *ib_p = ih_p->ih_ino_p->ino_ib_p; 524 pci_t *pci_p = ib_p->ib_pci_p; 525 ib_ino_t ino; 526 527 ino = ih_p->ih_ino_p->ino_ino; 528 529 (void) snprintf(pciintr_ks_template.pciintr_ks_name.value.c, maxlen, 530 "%s%d", ddi_driver_name(ih_p->ih_dip), 531 ddi_get_instance(ih_p->ih_dip)); 532 533 (void) ddi_pathname(ih_p->ih_dip, ih_devpath); 534 (void) ddi_pathname(pci_p->pci_dip, ih_buspath); 535 kstat_named_setstr(&pciintr_ks_template.pciintr_ks_devpath, ih_devpath); 536 kstat_named_setstr(&pciintr_ks_template.pciintr_ks_buspath, ih_buspath); 537 538 if (ih_p->ih_intr_state == PCI_INTR_STATE_ENABLE) { 539 (void) strcpy(pciintr_ks_template.pciintr_ks_type.value.c, 540 "fixed"); 541 pciintr_ks_template.pciintr_ks_cpu.value.ui64 = 542 ih_p->ih_ino_p->ino_cpuid; 543 pciintr_ks_template.pciintr_ks_pil.value.ui64 = 544 ih_p->ih_ino_p->ino_pil; 545 pciintr_ks_template.pciintr_ks_time.value.ui64 = ih_p->ih_nsec + 546 (uint64_t)tick2ns((hrtime_t)ih_p->ih_ticks, 547 ih_p->ih_ino_p->ino_cpuid); 548 pciintr_ks_template.pciintr_ks_ino.value.ui64 = ino; 549 pciintr_ks_template.pciintr_ks_cookie.value.ui64 = 550 IB_INO_TO_MONDO(ib_p, ino); 551 } else { 552 (void) strcpy(pciintr_ks_template.pciintr_ks_type.value.c, 553 "disabled"); 554 pciintr_ks_template.pciintr_ks_cpu.value.ui64 = 0; 555 pciintr_ks_template.pciintr_ks_pil.value.ui64 = 0; 556 pciintr_ks_template.pciintr_ks_time.value.ui64 = 0; 557 pciintr_ks_template.pciintr_ks_ino.value.ui64 = 0; 558 pciintr_ks_template.pciintr_ks_cookie.value.ui64 = 0; 559 } 560 561 return (0); 562 } 563 564 int 565 pci_add_intr(dev_info_t *dip, dev_info_t *rdip, ddi_intr_handle_impl_t *hdlp) 566 { 567 pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 568 ib_t *ib_p = pci_p->pci_ib_p; 569 cb_t *cb_p = pci_p->pci_cb_p; 570 ih_t *ih_p; 571 ib_ino_t ino; 572 ib_ino_info_t *ino_p; /* pulse interrupts have no ino */ 573 ib_mondo_t mondo; 574 uint32_t cpu_id; 575 int ret; 576 int32_t weight; 577 578 ino = IB_MONDO_TO_INO(hdlp->ih_vector); 579 580 DEBUG3(DBG_A_INTX, dip, "pci_add_intr: rdip=%s%d ino=%x\n", 581 ddi_driver_name(rdip), ddi_get_instance(rdip), ino); 582 583 if (ino > ib_p->ib_max_ino) { 584 DEBUG1(DBG_A_INTX, dip, "ino %x is invalid\n", ino); 585 return (DDI_INTR_NOTFOUND); 586 } 587 588 if (hdlp->ih_vector & PCI_PULSE_INO) { 589 volatile uint64_t *map_reg_addr; 590 map_reg_addr = ib_intr_map_reg_addr(ib_p, ino); 591 592 mondo = pci_xlate_intr(dip, rdip, ib_p, ino); 593 if (mondo == 0) 594 goto fail1; 595 596 hdlp->ih_vector = CB_MONDO_TO_XMONDO(cb_p, mondo); 597 598 if (i_ddi_add_ivintr(hdlp) != DDI_SUCCESS) 599 goto fail1; 600 601 /* 602 * Select cpu and program. 603 * 604 * Since there is no good way to always derive cpuid in 605 * pci_remove_intr for PCI_PULSE_INO (esp. for STARFIRE), we 606 * don't add (or remove) device weight for pulsed interrupt 607 * sources. 608 */ 609 mutex_enter(&ib_p->ib_intr_lock); 610 cpu_id = intr_dist_cpuid(); 611 *map_reg_addr = ib_get_map_reg(mondo, cpu_id); 612 mutex_exit(&ib_p->ib_intr_lock); 613 *map_reg_addr; /* flush previous write */ 614 goto done; 615 } 616 617 if ((mondo = pci_xlate_intr(dip, rdip, pci_p->pci_ib_p, ino)) == 0) 618 goto fail1; 619 620 ino = IB_MONDO_TO_INO(mondo); 621 622 mutex_enter(&ib_p->ib_ino_lst_mutex); 623 ih_p = ib_alloc_ih(rdip, hdlp->ih_inum, 624 hdlp->ih_cb_func, hdlp->ih_cb_arg1, hdlp->ih_cb_arg2); 625 if (map_pcidev_cfg_reg(dip, rdip, &ih_p->ih_config_handle)) 626 goto fail2; 627 628 if (ino_p = ib_locate_ino(ib_p, ino)) { /* sharing ino */ 629 uint32_t intr_index = hdlp->ih_inum; 630 if (ib_ino_locate_intr(ino_p, rdip, intr_index)) { 631 DEBUG1(DBG_A_INTX, dip, "dup intr #%d\n", intr_index); 632 goto fail3; 633 } 634 635 /* add weight to the cpu that we are already targeting */ 636 cpu_id = ino_p->ino_cpuid; 637 weight = pci_class_to_intr_weight(rdip); 638 intr_dist_cpuid_add_device_weight(cpu_id, rdip, weight); 639 640 ib_ino_add_intr(pci_p, ino_p, ih_p); 641 goto ino_done; 642 } 643 644 ino_p = ib_new_ino(ib_p, ino, ih_p); 645 646 if (hdlp->ih_pri == 0) 647 hdlp->ih_pri = pci_class_to_pil(rdip); 648 649 hdlp->ih_vector = CB_MONDO_TO_XMONDO(cb_p, mondo); 650 651 /* Store this global mondo */ 652 ino_p->ino_mondo = hdlp->ih_vector; 653 654 DEBUG2(DBG_A_INTX, dip, "pci_add_intr: pil=0x%x mondo=0x%x\n", 655 hdlp->ih_pri, hdlp->ih_vector); 656 657 DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, 658 (ddi_intr_handler_t *)pci_intr_wrapper, (caddr_t)ino_p, NULL); 659 660 ret = i_ddi_add_ivintr(hdlp); 661 662 /* 663 * Restore original interrupt handler 664 * and arguments in interrupt handle. 665 */ 666 DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, ih_p->ih_handler, 667 ih_p->ih_handler_arg1, ih_p->ih_handler_arg2); 668 669 if (ret != DDI_SUCCESS) 670 goto fail4; 671 672 /* Save the pil for this ino */ 673 ino_p->ino_pil = hdlp->ih_pri; 674 675 /* clear and enable interrupt */ 676 IB_INO_INTR_CLEAR(ino_p->ino_clr_reg); 677 678 /* select cpu and compute weight, saving both for sharing and removal */ 679 cpu_id = pci_intr_dist_cpuid(ib_p, ino_p); 680 ino_p->ino_cpuid = cpu_id; 681 ino_p->ino_established = 1; 682 weight = pci_class_to_intr_weight(rdip); 683 intr_dist_cpuid_add_device_weight(cpu_id, rdip, weight); 684 685 #ifdef _STARFIRE 686 cpu_id = pc_translate_tgtid(cb_p->cb_ittrans_cookie, cpu_id, 687 IB_GET_MAPREG_INO(ino)); 688 #endif /* _STARFIRE */ 689 *ino_p->ino_map_reg = ib_get_map_reg(mondo, cpu_id); 690 *ino_p->ino_map_reg; 691 ino_done: 692 ih_p->ih_ino_p = ino_p; 693 ih_p->ih_ksp = kstat_create("pci_intrs", 694 atomic_inc_32_nv(&pciintr_ks_instance), "config", "interrupts", 695 KSTAT_TYPE_NAMED, 696 sizeof (pciintr_ks_template) / sizeof (kstat_named_t), 697 KSTAT_FLAG_VIRTUAL); 698 if (ih_p->ih_ksp != NULL) { 699 ih_p->ih_ksp->ks_data_size += MAXPATHLEN * 2; 700 ih_p->ih_ksp->ks_lock = &pciintr_ks_template_lock; 701 ih_p->ih_ksp->ks_data = &pciintr_ks_template; 702 ih_p->ih_ksp->ks_private = ih_p; 703 ih_p->ih_ksp->ks_update = pci_ks_update; 704 kstat_install(ih_p->ih_ksp); 705 } 706 ib_ino_map_reg_share(ib_p, ino, ino_p); 707 mutex_exit(&ib_p->ib_ino_lst_mutex); 708 done: 709 DEBUG2(DBG_A_INTX, dip, "done! Interrupt 0x%x pil=%x\n", 710 hdlp->ih_vector, hdlp->ih_pri); 711 return (DDI_SUCCESS); 712 fail4: 713 ib_delete_ino(ib_p, ino_p); 714 fail3: 715 if (ih_p->ih_config_handle) 716 pci_config_teardown(&ih_p->ih_config_handle); 717 fail2: 718 mutex_exit(&ib_p->ib_ino_lst_mutex); 719 kmem_free(ih_p, sizeof (ih_t)); 720 fail1: 721 DEBUG2(DBG_A_INTX, dip, "Failed! Interrupt 0x%x pil=%x\n", 722 hdlp->ih_vector, hdlp->ih_pri); 723 return (DDI_FAILURE); 724 } 725 726 int 727 pci_remove_intr(dev_info_t *dip, dev_info_t *rdip, ddi_intr_handle_impl_t *hdlp) 728 { 729 pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 730 ib_t *ib_p = pci_p->pci_ib_p; 731 cb_t *cb_p = pci_p->pci_cb_p; 732 ib_ino_t ino; 733 ib_mondo_t mondo; 734 ib_ino_info_t *ino_p; /* non-pulse only */ 735 ih_t *ih_p; /* non-pulse only */ 736 737 ino = IB_MONDO_TO_INO(hdlp->ih_vector); 738 739 DEBUG3(DBG_R_INTX, dip, "pci_rem_intr: rdip=%s%d ino=%x\n", 740 ddi_driver_name(rdip), ddi_get_instance(rdip), ino); 741 742 if (hdlp->ih_vector & PCI_PULSE_INO) { /* pulse interrupt */ 743 volatile uint64_t *map_reg_addr; 744 745 /* 746 * No weight was added by pci_add_intr for PCI_PULSE_INO 747 * because it is difficult to determine cpuid here. 748 */ 749 map_reg_addr = ib_intr_map_reg_addr(ib_p, ino); 750 IB_INO_INTR_RESET(map_reg_addr); /* disable intr */ 751 *map_reg_addr; 752 753 mondo = pci_xlate_intr(dip, rdip, ib_p, ino); 754 if (mondo == 0) { 755 DEBUG1(DBG_R_INTX, dip, 756 "can't get mondo for ino %x\n", ino); 757 return (DDI_FAILURE); 758 } 759 760 if (hdlp->ih_pri == 0) 761 hdlp->ih_pri = pci_class_to_pil(rdip); 762 763 hdlp->ih_vector = CB_MONDO_TO_XMONDO(cb_p, mondo); 764 765 DEBUG2(DBG_R_INTX, dip, "pci_rem_intr: pil=0x%x mondo=0x%x\n", 766 hdlp->ih_pri, hdlp->ih_vector); 767 768 i_ddi_rem_ivintr(hdlp); 769 770 DEBUG2(DBG_R_INTX, dip, "pulse success mondo=%x reg=%p\n", 771 mondo, map_reg_addr); 772 return (DDI_SUCCESS); 773 } 774 775 /* Translate the interrupt property */ 776 mondo = pci_xlate_intr(dip, rdip, pci_p->pci_ib_p, ino); 777 if (mondo == 0) { 778 DEBUG1(DBG_R_INTX, dip, "can't get mondo for ino %x\n", ino); 779 return (DDI_FAILURE); 780 } 781 ino = IB_MONDO_TO_INO(mondo); 782 783 mutex_enter(&ib_p->ib_ino_lst_mutex); 784 ino_p = ib_locate_ino(ib_p, ino); 785 if (!ino_p) { 786 int r = cb_remove_xintr(pci_p, dip, rdip, ino, mondo); 787 if (r != DDI_SUCCESS) 788 cmn_err(CE_WARN, "%s%d-xintr: ino %x is invalid", 789 ddi_driver_name(dip), ddi_get_instance(dip), ino); 790 mutex_exit(&ib_p->ib_ino_lst_mutex); 791 return (r); 792 } 793 794 ih_p = ib_ino_locate_intr(ino_p, rdip, hdlp->ih_inum); 795 ib_ino_rem_intr(pci_p, ino_p, ih_p); 796 intr_dist_cpuid_rem_device_weight(ino_p->ino_cpuid, rdip); 797 if (ino_p->ino_ih_size == 0) { 798 IB_INO_INTR_PEND(ib_clear_intr_reg_addr(ib_p, ino)); 799 hdlp->ih_vector = CB_MONDO_TO_XMONDO(cb_p, mondo); 800 if (hdlp->ih_pri == 0) 801 hdlp->ih_pri = pci_class_to_pil(rdip); 802 803 i_ddi_rem_ivintr(hdlp); 804 ib_delete_ino(ib_p, ino_p); 805 } 806 807 /* re-enable interrupt only if mapping register still shared */ 808 if (ib_ino_map_reg_unshare(ib_p, ino, ino_p)) { 809 IB_INO_INTR_ON(ino_p->ino_map_reg); 810 *ino_p->ino_map_reg; 811 } 812 mutex_exit(&ib_p->ib_ino_lst_mutex); 813 814 if (ino_p->ino_ih_size == 0) 815 kmem_free(ino_p, sizeof (ib_ino_info_t)); 816 817 DEBUG1(DBG_R_INTX, dip, "success! mondo=%x\n", mondo); 818 return (DDI_SUCCESS); 819 } 820 821 /* 822 * free the pci_inos array allocated during pci_intr_setup. the actual 823 * interrupts are torn down by their respective block destroy routines: 824 * cb_destroy, pbm_destroy, and ib_destroy. 825 */ 826 void 827 pci_intr_teardown(pci_t *pci_p) 828 { 829 kmem_free(pci_p->pci_inos, pci_p->pci_inos_len); 830 pci_p->pci_inos = NULL; 831 pci_p->pci_inos_len = 0; 832 } 833