1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * This is the nexus driver for SMBUS devices. It mostly does not use 30 * the SMBUS protocol so that it fits better into the solaris i2c 31 * framework. 32 */ 33 34 #include <sys/types.h> 35 #include <sys/conf.h> 36 #include <sys/file.h> 37 #include <sys/open.h> 38 #include <sys/ddi.h> 39 #include <sys/sunddi.h> 40 #include <sys/modctl.h> 41 #include <sys/stat.h> 42 #include <sys/kmem.h> 43 #include <sys/archsystm.h> 44 #include <sys/platform_module.h> 45 46 #include <sys/i2c/clients/i2c_client.h> 47 #include <sys/i2c/misc/i2c_svc.h> 48 #include <sys/i2c/misc/i2c_svc_impl.h> 49 #include <sys/i2c/nexus/smbus.h> 50 51 /* 52 * static function declarations 53 */ 54 static uint_t smbus_intr_cmn(smbus_t *smbus, char *src); 55 static void smbus_intr_timeout(void *arg); 56 static void smbus_resume(dev_info_t *dip); 57 static void smbus_suspend(dev_info_t *dip); 58 static int smbus_bus_ctl(dev_info_t *dip, dev_info_t *rdip, 59 ddi_ctl_enum_t op, void *arg, void *result); 60 static int smbus_acquire(smbus_t *, dev_info_t *dip, 61 i2c_transfer_t *tp); 62 static void smbus_release(smbus_t *); 63 static int smbus_attach(dev_info_t *dip, ddi_attach_cmd_t cmd); 64 static int smbus_detach(dev_info_t *dip, ddi_detach_cmd_t cmd); 65 static void smbus_free_regs(smbus_t *smbus); 66 static int smbus_setup_regs(dev_info_t *dip, smbus_t *smbus); 67 static void smbus_reportdev(dev_info_t *dip, dev_info_t *rdip); 68 static void smbus_uninitchild(dev_info_t *cdip); 69 static int smbus_initchild(dev_info_t *cdip); 70 static int smbus_rd(smbus_t *smbus); 71 static int smbus_wr(smbus_t *smbus); 72 static void smbus_put(smbus_t *smbus, uint8_t reg, uint8_t data, uint8_t flags); 73 static uint8_t smbus_get(smbus_t *smbus, uint8_t reg); 74 static int smbus_dip_to_addr(dev_info_t *dip); 75 static uint_t smbus_intr(caddr_t arg); 76 static int smbus_switch(smbus_t *smbus); 77 78 static struct bus_ops smbus_busops = { 79 BUSO_REV, 80 nullbusmap, /* bus_map */ 81 NULL, /* bus_get_intrspec */ 82 NULL, /* bus_add_intrspec */ 83 NULL, /* bus_remove_intrspec */ 84 NULL, /* bus_map_fault */ 85 ddi_no_dma_map, /* bus_dma_map */ 86 ddi_no_dma_allochdl, /* bus_dma_allochdl */ 87 ddi_no_dma_freehdl, /* bus_dma_freehdl */ 88 ddi_no_dma_bindhdl, /* bus_dma_bindhdl */ 89 ddi_no_dma_unbindhdl, /* bus_unbindhdl */ 90 ddi_no_dma_flush, /* bus_dma_flush */ 91 ddi_no_dma_win, /* bus_dma_win */ 92 ddi_no_dma_mctl, /* bus_dma_ctl */ 93 smbus_bus_ctl, /* bus_ctl */ 94 ddi_bus_prop_op, /* bus_prop_op */ 95 NULL, /* bus_get_eventcookie */ 96 NULL, /* bus_add_eventcall */ 97 NULL, /* bus_remove_eventcall */ 98 NULL, /* bus_post_event */ 99 0, /* bus_intr_ctl */ 100 0, /* bus_config */ 101 0, /* bus_unconfig */ 102 0, /* bus_fm_init */ 103 0, /* bus_fm_fini */ 104 0, /* bus_fm_access_enter */ 105 0, /* bus_fm_access_exit */ 106 0, /* bus_power */ 107 i_ddi_intr_ops /* bus_intr_op */ 108 }; 109 110 struct cb_ops smbus_cb_ops = { 111 nodev, /* open */ 112 nodev, /* close */ 113 nodev, /* strategy */ 114 nodev, /* print */ 115 nodev, /* dump */ 116 nodev, /* read */ 117 nodev, /* write */ 118 nodev, /* ioctl */ 119 nodev, /* devmap */ 120 nodev, /* mmap */ 121 nodev, /* segmap */ 122 nochpoll, /* poll */ 123 ddi_prop_op, /* cb_prop_op */ 124 0, /* streamtab */ 125 D_MP | D_NEW /* Driver compatibility flag */ 126 }; 127 128 static struct dev_ops smbus_ops = { 129 DEVO_REV, 130 0, 131 ddi_no_info, 132 nulldev, 133 nulldev, 134 smbus_attach, 135 smbus_detach, 136 nodev, 137 &smbus_cb_ops, 138 &smbus_busops 139 }; 140 141 static struct modldrv modldrv = { 142 &mod_driverops, /* Type of module. This one is a driver */ 143 "SMBUS nexus Driver %I%", /* Name of the module. */ 144 &smbus_ops, /* driver ops */ 145 }; 146 147 static struct modlinkage modlinkage = { 148 MODREV_1, 149 &modldrv, 150 NULL 151 }; 152 153 /* 154 * Globals 155 */ 156 static void *smbus_state; 157 158 static int intr_timeout = INTR_TIMEOUT; 159 160 /* 161 * The "interrupt-priorities" property is how a driver can specify a SPARC 162 * PIL level to associate with each of its interrupt properties. Most 163 * self-identifying busses have a better mechanism for managing this, but I2C 164 * doesn't. 165 */ 166 int smbus_pil = SMBUS_PIL; 167 168 i2c_nexus_reg_t smbus_regvec = { 169 I2C_NEXUS_REV, 170 smbus_transfer, 171 }; 172 173 #ifdef DEBUG 174 175 static int smbus_print_lvl = 0; 176 static char msg_buff[1024]; 177 static kmutex_t msg_buf_lock; 178 179 void 180 smbus_print(int flags, const char *fmt, ...) 181 { 182 if (flags & smbus_print_lvl) { 183 va_list ap; 184 185 va_start(ap, fmt); 186 187 if (smbus_print_lvl & PRT_PROM) { 188 prom_vprintf(fmt, ap); 189 } else { 190 191 mutex_enter(&msg_buf_lock); 192 (void) vsprintf(msg_buff, fmt, ap); 193 if (smbus_print_lvl & PRT_BUFFONLY) { 194 cmn_err(CE_CONT, "?%s", msg_buff); 195 } else { 196 cmn_err(CE_CONT, "%s", msg_buff); 197 } 198 mutex_exit(&msg_buf_lock); 199 } 200 va_end(ap); 201 } 202 } 203 #endif /* DEBUG */ 204 205 int 206 _init(void) 207 { 208 int status; 209 210 status = ddi_soft_state_init(&smbus_state, sizeof (smbus_t), 211 1); 212 if (status != 0) { 213 214 return (status); 215 } 216 217 if ((status = mod_install(&modlinkage)) != 0) { 218 ddi_soft_state_fini(&smbus_state); 219 } else { 220 #ifdef DEBUG 221 mutex_init(&msg_buf_lock, NULL, MUTEX_DRIVER, NULL); 222 #endif 223 } 224 return (status); 225 } 226 227 int 228 _fini(void) 229 { 230 int status; 231 232 if ((status = mod_remove(&modlinkage)) == 0) { 233 ddi_soft_state_fini(&smbus_state); 234 #ifdef DEBUG 235 mutex_destroy(&msg_buf_lock); 236 #endif 237 } 238 239 return (status); 240 } 241 242 /* 243 * The loadable-module _info(9E) entry point 244 */ 245 int 246 _info(struct modinfo *modinfop) 247 { 248 return (mod_info(&modlinkage, modinfop)); 249 } 250 251 static void 252 smbus_interrupts_on(smbus_t *smbus) 253 { 254 int src_enable; 255 256 src_enable = ddi_get32(smbus->smbus_confighandle, 257 (uint32_t *)&smbus->smbus_configregaddr[SMBUS_SRC_ENA]); 258 src_enable |= SMBUS_SMI; 259 ddi_put32(smbus->smbus_confighandle, 260 (uint32_t *)&smbus->smbus_configregaddr[SMBUS_SRC_ENA], 261 src_enable); 262 (void) ddi_get32(smbus->smbus_confighandle, 263 (uint32_t *)&smbus->smbus_configregaddr[SMBUS_SRC_ENA]); 264 } 265 266 static void 267 smbus_interrupts_off(smbus_t *smbus) 268 { 269 int src_enable; 270 271 src_enable = ddi_get32(smbus->smbus_confighandle, 272 (uint32_t *)&smbus->smbus_configregaddr[SMBUS_SRC_ENA]); 273 src_enable &= ~SMBUS_SMI; 274 ddi_put32(smbus->smbus_confighandle, 275 (uint32_t *)&smbus->smbus_configregaddr[SMBUS_SRC_ENA], 276 src_enable); 277 (void) ddi_get32(smbus->smbus_confighandle, 278 (uint32_t *)&smbus->smbus_configregaddr[SMBUS_SRC_ENA]); 279 } 280 281 static void 282 smbus_dodetach(dev_info_t *dip) 283 { 284 smbus_t *smbus; 285 int instance = ddi_get_instance(dip); 286 287 smbus = ddi_get_soft_state(smbus_state, instance); 288 289 if (smbus == NULL) { 290 291 return; 292 } 293 294 cv_destroy(&smbus->smbus_cv); 295 mutex_destroy(&smbus->smbus_mutex); 296 297 if ((smbus->smbus_attachflags & INTERRUPT_PRI) != 0) { 298 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, 299 "interrupt-priorities"); 300 } 301 302 smbus_free_regs(smbus); 303 304 if ((smbus->smbus_attachflags & NEXUS_REGISTER) != 0) { 305 i2c_nexus_unregister(dip); 306 } 307 if ((smbus->smbus_attachflags & IMUTEX) != 0) { 308 mutex_destroy(&smbus->smbus_imutex); 309 cv_destroy(&smbus->smbus_icv); 310 } 311 312 if (smbus->smbus_timeout != 0) { 313 (void) untimeout(smbus->smbus_timeout); 314 } 315 316 if ((smbus->smbus_attachflags & ADD_INTR) != 0) { 317 ddi_remove_intr(dip, 0, smbus->smbus_icookie); 318 } 319 320 ddi_soft_state_free(smbus_state, instance); 321 } 322 323 static int 324 smbus_doattach(dev_info_t *dip) 325 { 326 smbus_t *smbus; 327 int instance = ddi_get_instance(dip); 328 329 /* 330 * Allocate soft state structure. 331 */ 332 if (ddi_soft_state_zalloc(smbus_state, instance) != DDI_SUCCESS) { 333 334 goto bad; 335 } 336 337 smbus = ddi_get_soft_state(smbus_state, instance); 338 339 (void) snprintf(smbus->smbus_name, sizeof (smbus->smbus_name), 340 "%s%d", ddi_node_name(dip), instance); 341 342 smbus->smbus_dip = dip; 343 344 mutex_init(&smbus->smbus_mutex, NULL, MUTEX_DRIVER, NULL); 345 mutex_init(&smbus->smbus_imutex, NULL, MUTEX_DRIVER, NULL); 346 cv_init(&smbus->smbus_cv, NULL, CV_DRIVER, NULL); 347 cv_init(&smbus->smbus_intr_cv, NULL, CV_DRIVER, NULL); 348 349 if (smbus_setup_regs(dip, smbus) != DDI_SUCCESS) { 350 goto bad; 351 } 352 353 if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 354 "interrupts") == 1) { 355 smbus->smbus_polling = 0; 356 /* 357 * The "interrupt-priorities" property is how a driver can 358 * specify a SPARC PIL level to associate with each of its 359 * interrupt properties. Most self-identifying busses have 360 * a better mechanism for managing this, but I2C doesn't. 361 */ 362 if (ddi_prop_exists(DDI_DEV_T_ANY, dip, 363 DDI_PROP_NOTPROM | DDI_PROP_DONTPASS, 364 "interrupt-priorities") != 1) { 365 (void) ddi_prop_create(DDI_DEV_T_NONE, dip, 366 DDI_PROP_CANSLEEP, "interrupt-priorities", 367 (caddr_t)&smbus_pil, 368 sizeof (smbus_pil)); 369 smbus->smbus_attachflags |= INTERRUPT_PRI; 370 } 371 372 /* 373 * Clear status to clear any possible interrupt 374 */ 375 smbus_put(smbus, SMB_STS, 0xff, SMBUS_FLUSH); 376 377 if (ddi_get_iblock_cookie(dip, 0, &smbus->smbus_icookie) != 378 DDI_SUCCESS) { 379 goto bad; 380 } 381 382 if (ddi_add_intr(dip, 0, NULL, NULL, smbus_intr, 383 (caddr_t)smbus) != DDI_SUCCESS) { 384 cmn_err(CE_WARN, "%s failed to add interrupt", 385 smbus->smbus_name); 386 goto bad; 387 } 388 smbus->smbus_attachflags |= ADD_INTR; 389 } else { 390 smbus->smbus_polling = 1; 391 /* Clear status */ 392 smbus_put(smbus, SMB_STS, 0xff, SMBUS_FLUSH); 393 } 394 395 /* 396 * initialize a cv and mutex 397 */ 398 cv_init(&smbus->smbus_icv, NULL, CV_DRIVER, NULL); 399 mutex_init(&smbus->smbus_imutex, NULL, MUTEX_DRIVER, 400 (void *)smbus->smbus_icookie); 401 smbus->smbus_attachflags |= IMUTEX; 402 403 /* 404 * Register with the i2c framework 405 */ 406 i2c_nexus_register(dip, &smbus_regvec); 407 smbus->smbus_attachflags |= NEXUS_REGISTER; 408 409 return (DDI_SUCCESS); 410 411 bad: 412 smbus_dodetach(dip); 413 414 return (DDI_FAILURE); 415 } 416 417 static int 418 smbus_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 419 { 420 switch (cmd) { 421 case DDI_ATTACH: 422 423 return (smbus_doattach(dip)); 424 case DDI_RESUME: 425 smbus_resume(dip); 426 427 return (DDI_SUCCESS); 428 default: 429 430 return (DDI_FAILURE); 431 } 432 } 433 434 static int 435 smbus_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 436 { 437 switch (cmd) { 438 case DDI_DETACH: 439 smbus_dodetach(dip); 440 441 return (DDI_SUCCESS); 442 case DDI_SUSPEND: 443 smbus_suspend(dip); 444 445 return (DDI_SUCCESS); 446 default: 447 448 return (DDI_FAILURE); 449 } 450 } 451 452 static int 453 smbus_bus_ctl(dev_info_t *dip, dev_info_t *rdip, ddi_ctl_enum_t op, 454 void *arg, void *result) 455 { 456 switch (op) { 457 case DDI_CTLOPS_INITCHILD: 458 459 return (smbus_initchild((dev_info_t *)arg)); 460 case DDI_CTLOPS_UNINITCHILD: 461 smbus_uninitchild((dev_info_t *)arg); 462 463 return (DDI_SUCCESS); 464 case DDI_CTLOPS_REPORTDEV: 465 smbus_reportdev(dip, rdip); 466 467 return (DDI_SUCCESS); 468 case DDI_CTLOPS_DMAPMAPC: 469 case DDI_CTLOPS_POKE: 470 case DDI_CTLOPS_PEEK: 471 case DDI_CTLOPS_IOMIN: 472 case DDI_CTLOPS_REPORTINT: 473 case DDI_CTLOPS_SIDDEV: 474 case DDI_CTLOPS_SLAVEONLY: 475 case DDI_CTLOPS_AFFINITY: 476 case DDI_CTLOPS_PTOB: 477 case DDI_CTLOPS_BTOP: 478 case DDI_CTLOPS_BTOPR: 479 case DDI_CTLOPS_DVMAPAGESIZE: 480 481 return (DDI_FAILURE); 482 default: 483 484 return (ddi_ctlops(dip, rdip, op, arg, result)); 485 } 486 } 487 488 static int 489 smbus_initchild(dev_info_t *cdip) 490 { 491 int32_t cell_size; 492 int len; 493 int32_t regs[2]; 494 int err; 495 smbus_ppvt_t *ppvt; 496 char name[30]; 497 498 SMBUS_PRINT((PRT_INIT, "smbus_initchild ENTER: %s\n", 499 ddi_node_name(cdip))); 500 501 len = sizeof (cell_size); 502 err = ddi_getlongprop_buf(DDI_DEV_T_ANY, cdip, 503 DDI_PROP_CANSLEEP, "#address-cells", 504 (caddr_t)&cell_size, &len); 505 if (err != DDI_PROP_SUCCESS || len != sizeof (cell_size)) { 506 cmn_err(CE_WARN, "cannot find address-cells"); 507 508 return (DDI_FAILURE); 509 } 510 511 len = sizeof (regs); 512 err = ddi_getlongprop_buf(DDI_DEV_T_ANY, cdip, 513 DDI_PROP_DONTPASS | DDI_PROP_CANSLEEP, 514 "reg", (caddr_t)regs, &len); 515 516 if (err != DDI_PROP_SUCCESS) { 517 cmn_err(CE_WARN, "cannot get reg property"); 518 519 return (DDI_FAILURE); 520 } 521 522 ppvt = kmem_zalloc(sizeof (smbus_ppvt_t), KM_SLEEP); 523 ddi_set_parent_data(cdip, ppvt); 524 525 /* 526 * The reg property contains an unused first element (which is 527 * the mux addr on xcal), and the second element is the i2c bus 528 * address of the device. 529 */ 530 ppvt->smbus_ppvt_addr = regs[1]; 531 (void) sprintf(name, "%x", regs[1]); 532 533 ddi_set_name_addr(cdip, name); 534 535 SMBUS_PRINT((PRT_INIT, "smbus_initchild SUCCESS: %s\n", 536 ddi_node_name(cdip))); 537 538 return (DDI_SUCCESS); 539 } 540 541 static void 542 smbus_uninitchild(dev_info_t *cdip) 543 { 544 smbus_ppvt_t *ppvt; 545 546 ppvt = ddi_get_parent_data(cdip); 547 ddi_set_parent_data(cdip, NULL); 548 549 ddi_set_name_addr(cdip, NULL); 550 551 kmem_free(ppvt, sizeof (smbus_ppvt_t)); 552 553 SMBUS_PRINT((PRT_INIT, "smbus_uninitchild: %s\n", ddi_node_name(cdip))); 554 } 555 556 static void 557 smbus_reportdev(dev_info_t *dip, dev_info_t *rdip) 558 { 559 smbus_ppvt_t *ppvt; 560 561 ppvt = ddi_get_parent_data(rdip); 562 563 cmn_err(CE_CONT, "?%s%d at %s%d: addr 0x%x", 564 ddi_driver_name(rdip), ddi_get_instance(rdip), 565 ddi_driver_name(dip), ddi_get_instance(dip), 566 ppvt->smbus_ppvt_addr); 567 } 568 569 /* 570 * smbus_setup_regs() is called to map in the registers 571 * specific to the smbus. 572 */ 573 static int 574 smbus_setup_regs(dev_info_t *dip, smbus_t *smbus) 575 { 576 ddi_device_acc_attr_t attr; 577 int ret; 578 579 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 580 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 581 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 582 583 ret = ddi_regs_map_setup(dip, 1, (caddr_t *)&smbus->smbus_regaddr, 584 0, 0, &attr, &smbus->smbus_rhandle); 585 586 if (ret == DDI_FAILURE) { 587 cmn_err(CE_WARN, "%s unable to map regs", smbus->smbus_name); 588 589 } else if (ret == DDI_REGS_ACC_CONFLICT) { 590 cmn_err(CE_WARN, 591 "%s unable to map regs because of conflict", 592 smbus->smbus_name); 593 ret = DDI_FAILURE; 594 } 595 596 if (ret == DDI_FAILURE) { 597 598 return (ret); 599 } 600 601 ret = ddi_regs_map_setup(dip, 0, (caddr_t *)&smbus->smbus_configregaddr, 602 0, 0, &attr, &smbus->smbus_confighandle); 603 604 if (ret == DDI_FAILURE) { 605 cmn_err(CE_WARN, "%s unable to map config regs", 606 smbus->smbus_name); 607 608 } else if (ret == DDI_REGS_ACC_CONFLICT) { 609 cmn_err(CE_WARN, 610 "%s unable to map config regs because of conflict", 611 smbus->smbus_name); 612 ret = DDI_FAILURE; 613 } 614 615 return (ret); 616 } 617 618 /* 619 * smbus_free_regs() frees any registers previously allocated. 620 */ 621 static void 622 smbus_free_regs(smbus_t *smbus) 623 { 624 if (smbus->smbus_regaddr != NULL) { 625 ddi_regs_map_free(&smbus->smbus_rhandle); 626 } 627 628 if (smbus->smbus_configregaddr != NULL) { 629 ddi_regs_map_free(&smbus->smbus_confighandle); 630 } 631 } 632 633 /* 634 * smbus_dip_to_addr() takes a dip and returns an I2C address. 635 */ 636 static int 637 smbus_dip_to_addr(dev_info_t *cdip) 638 { 639 smbus_ppvt_t *ppvt; 640 641 ppvt = ddi_get_parent_data(cdip); 642 643 return (ppvt->smbus_ppvt_addr); 644 } 645 646 /* 647 * smbus_suspend() is called before the system suspends. Existing 648 * transfer in progress or waiting will complete, but new transfers are 649 * effectively blocked by "acquiring" the bus. 650 */ 651 static void 652 smbus_suspend(dev_info_t *dip) 653 { 654 smbus_t *smbus; 655 int instance; 656 657 instance = ddi_get_instance(dip); 658 smbus = ddi_get_soft_state(smbus_state, instance); 659 660 (void) smbus_acquire(smbus, NULL, NULL); 661 } 662 663 /* 664 * smbus_resume() is called when the system resumes from CPR. It releases 665 * the hold that was placed on the i2c bus, which allows any real 666 * transfers to continue. 667 */ 668 static void 669 smbus_resume(dev_info_t *dip) 670 { 671 smbus_t *smbus; 672 int instance; 673 674 instance = ddi_get_instance(dip); 675 smbus = ddi_get_soft_state(smbus_state, instance); 676 677 smbus_release(smbus); 678 } 679 680 /* 681 * smbus_acquire() is called by a thread wishing to "own" the SMbus. 682 * It should not be held across multiple transfers. 683 */ 684 static int 685 smbus_acquire(smbus_t *smbus, dev_info_t *dip, i2c_transfer_t *tp) 686 { 687 mutex_enter(&smbus->smbus_mutex); 688 while (smbus->smbus_busy) { 689 cv_wait(&smbus->smbus_cv, &smbus->smbus_mutex); 690 } 691 smbus->smbus_busy = 1; 692 mutex_exit(&smbus->smbus_mutex); 693 694 /* 695 * On systems where OBP shares a smbus controller with the 696 * OS, plat_shared_i2c_enter will serialize access to the 697 * smbus controller. Do not grab this lock during CPR 698 * suspend as the CPR thread also acquires this muxex 699 * through through prom_setprop which causes recursive 700 * mutex enter. 701 * 702 * dip == NULL during CPR. 703 */ 704 if ((&plat_shared_i2c_enter != NULL) && (dip != NULL)) { 705 plat_shared_i2c_enter(smbus->smbus_dip); 706 } 707 708 smbus->smbus_cur_tran = tp; 709 smbus->smbus_cur_dip = dip; 710 711 return (SMBUS_SUCCESS); 712 } 713 714 /* 715 * smbus_release() is called to release a hold made by smbus_acquire(). 716 */ 717 static void 718 smbus_release(smbus_t *smbus) 719 { 720 mutex_enter(&smbus->smbus_mutex); 721 smbus->smbus_busy = 0; 722 cv_signal(&smbus->smbus_cv); 723 smbus->smbus_cur_tran = NULL; 724 smbus->smbus_cur_dip = NULL; 725 mutex_exit(&smbus->smbus_mutex); 726 727 if ((&plat_shared_i2c_exit != NULL) && (smbus->smbus_cur_dip != NULL)) { 728 plat_shared_i2c_exit(smbus->smbus_dip); 729 } 730 } 731 732 static void 733 smbus_put(smbus_t *smbus, uint8_t reg, uint8_t data, uint8_t flags) 734 { 735 ddi_acc_handle_t hp = smbus->smbus_rhandle; 736 uint8_t *reg_addr = smbus->smbus_regaddr; 737 uint8_t *config_addr = smbus->smbus_configregaddr; 738 ddi_acc_handle_t config_handle = smbus->smbus_confighandle; 739 740 ddi_put8(hp, ®_addr[reg], data); 741 742 SMBUS_PRINT((PRT_PUT, "smbus_put: addr = %p data = %x\n", 743 ®_addr[reg], data)); 744 745 /* 746 * if FLUSH flag is passed, read a config regs to make sure 747 * data written is flushed. 748 */ 749 if (flags & SMBUS_FLUSH) { 750 (void) ddi_get8(config_handle, &config_addr[0]); 751 } 752 } 753 754 static uint8_t 755 smbus_get(smbus_t *smbus, uint8_t reg) 756 { 757 758 ddi_acc_handle_t hp = smbus->smbus_rhandle; 759 uint8_t *regaddr = smbus->smbus_regaddr; 760 uint8_t data; 761 762 data = ddi_get8(hp, ®addr[reg]); 763 764 SMBUS_PRINT((PRT_GET, "smbus_get: data = %x\n", data)); 765 766 return (data); 767 } 768 769 770 /* 771 * The southbridge smbus device appears to have a feature where 772 * reads from the status register return 0 for a few microseconds 773 * after clearing the status. 774 * 775 * "status_wait_idle" allows for this by retrying until 776 * it gets the right answer or times out. The loop count 777 * and the delay are empirical. The routine uses up 778 * 400 us if it fails. 779 * 780 * The fact that this routine waits for 10 us before the 781 * first check is deliberate. 782 */ 783 static int 784 smbus_wait_idle(smbus_t *smbus) 785 { 786 int retries = 40; 787 int status; 788 789 smbus_put(smbus, SMB_STS, 0xff, SMBUS_FLUSH); 790 do { 791 drv_usecwait(10); 792 status = smbus_get(smbus, SMB_STS); 793 } while (status != IDLE && --retries > 0); 794 return (status); 795 } 796 /* 797 * smbus_transfer is the function that is registered with 798 * I2C services to be called for each i2c transaction. 799 */ 800 int 801 smbus_transfer(dev_info_t *dip, i2c_transfer_t *tp) 802 { 803 smbus_t *smbus; 804 uint8_t status; 805 clock_t ctime; 806 807 smbus = ddi_get_soft_state(smbus_state, 808 ddi_get_instance(ddi_get_parent(dip))); 809 810 if (smbus_acquire(smbus, dip, tp) == SMBUS_FAILURE) { 811 tp->i2c_result = I2C_FAILURE; 812 813 return (I2C_FAILURE); 814 } 815 816 tp->i2c_r_resid = tp->i2c_rlen; 817 tp->i2c_w_resid = tp->i2c_wlen; 818 tp->i2c_result = I2C_SUCCESS; 819 smbus->smbus_retries = 0; 820 smbus->smbus_bytes_to_read = 0; 821 822 mutex_enter(&smbus->smbus_imutex); 823 824 SMBUS_PRINT((PRT_TRANS, "smbus_transfer: rlen=%d wlen=%d flags=%d", 825 tp->i2c_r_resid, tp->i2c_w_resid, tp->i2c_flags)); 826 827 /* 828 * First clear the status bits, then read them back to determine 829 * the current state. 830 */ 831 status = smbus_wait_idle(smbus); 832 833 if (status != IDLE) { 834 /* 835 * Try to issue bus reset 836 * First reset the state machine. 837 */ 838 smbus_put(smbus, SMB_TYP, KILL, SMBUS_FLUSH); 839 status = smbus_wait_idle(smbus); 840 841 if (status != IDLE) { 842 843 smbus_put(smbus, SMB_TYP, T_OUT, SMBUS_FLUSH); 844 status = smbus_wait_idle(smbus); 845 if (status != IDLE) { 846 cmn_err(CE_WARN, 847 "%s smbus not idle. Unable to reset %x", 848 smbus->smbus_name, status); 849 smbus->smbus_cur_tran->i2c_result = I2C_FAILURE; 850 mutex_exit(&smbus->smbus_imutex); 851 smbus_release(smbus); 852 853 return (I2C_FAILURE); 854 } else { 855 cmn_err(CE_WARN, "%s T_OUT reset required", 856 smbus->smbus_name); 857 } 858 } 859 } 860 861 if (smbus_switch(smbus) != SMBUS_COMPLETE) { 862 if (smbus->smbus_polling) { 863 smbus->smbus_poll_complete = 0; 864 smbus->smbus_poll_retries = 0; 865 do { 866 drv_usecwait(SMBUS_POLL_INTERVAL); 867 (void) smbus_intr_cmn(smbus, SMBUS_POLL); 868 } while (!smbus->smbus_poll_complete); 869 } else { 870 /* 871 * Start a timeout as there is a bug in southbridge 872 * smbus where sometimes a transaction never starts, 873 * and needs to be reinitiated. 874 */ 875 876 smbus->smbus_timeout = timeout(smbus_intr_timeout, 877 smbus, drv_usectohz(intr_timeout)); 878 SMBUS_PRINT((PRT_TRANS, 879 "starting timeout in smbus_transfer %p", 880 smbus->smbus_timeout)); 881 882 ctime = ddi_get_lbolt(); 883 ctime += drv_usectohz(SMBUS_TRANS_TIMEOUT); 884 885 smbus_interrupts_on(smbus); 886 887 888 cv_wait(&smbus->smbus_icv, &smbus->smbus_imutex); 889 } 890 } 891 892 893 mutex_exit(&smbus->smbus_imutex); 894 smbus_release(smbus); 895 896 return (tp->i2c_result); 897 } 898 899 /* 900 * This is called by smbus_intr_cmn() to figure out whether to call 901 * smbus_wr or smbus_rd depending on the command and current state. 902 */ 903 static int 904 smbus_switch(smbus_t *smbus) 905 { 906 int ret; 907 i2c_transfer_t *tp = smbus->smbus_cur_tran; 908 909 if (tp == NULL) { 910 cmn_err(CE_WARN, 911 "%s smbus_cur_tran is NULL. Transaction failed", 912 smbus->smbus_name); 913 914 return (SMBUS_FAILURE); 915 } 916 917 smbus->smbus_saved_w_resid = tp->i2c_w_resid; 918 919 switch (tp->i2c_flags) { 920 case I2C_WR: 921 ret = smbus_wr(smbus); 922 break; 923 case I2C_RD: 924 ret = smbus_rd(smbus); 925 break; 926 case I2C_WR_RD: 927 /* 928 * We could do a bit more decoding here, 929 * to allow the transactions that would 930 * work as a single smbus command to 931 * be done as such. It's not really 932 * worth the trouble. 933 */ 934 if (tp->i2c_w_resid > 0) { 935 ret = smbus_wr(smbus); 936 } else { 937 ret = smbus_rd(smbus); 938 } 939 break; 940 default: 941 tp->i2c_result = I2C_FAILURE; 942 ret = SMBUS_COMPLETE; 943 break; 944 } 945 946 return (ret); 947 } 948 949 /* 950 * 951 */ 952 static void 953 smbus_intr_timeout(void *arg) 954 { 955 smbus_t *smbus = (smbus_t *)arg; 956 957 mutex_enter(&smbus->smbus_imutex); 958 /* 959 * If timeout is already cleared, it means interrupt arrived 960 * while timeout fired. In this case, just return from here. 961 */ 962 if (smbus->smbus_timeout == 0) { 963 964 mutex_exit(&smbus->smbus_imutex); 965 966 return; 967 } 968 969 (void) smbus_intr_cmn(smbus, SMBUS_TIMEOUT); 970 mutex_exit(&smbus->smbus_imutex); 971 } 972 973 /* 974 * smbus_intr() is the interrupt handler for smbus. 975 */ 976 static uint_t 977 smbus_intr(caddr_t arg) 978 { 979 smbus_t *smbus = (smbus_t *)arg; 980 uint32_t intr_status; 981 uint_t result; 982 983 /* 984 * Check to see if intr is really from smbus 985 */ 986 intr_status = ddi_get32(smbus->smbus_confighandle, 987 (uint32_t *)&smbus->smbus_configregaddr[SMBUS_SRC_STATUS]); 988 989 990 if ((intr_status & SMBUS_SMB_INTR_STATUS) == 0) { 991 SMBUS_PRINT((PRT_INTR, "smbus_intr: intr not from smbus\n")); 992 993 return (DDI_INTR_UNCLAIMED); 994 } 995 996 mutex_enter(&smbus->smbus_imutex); 997 998 /* 999 * If timeout is already cleared, it means it arrived before the intr. 1000 * In that case, just return from here. 1001 */ 1002 if (smbus->smbus_timeout == 0) { 1003 1004 mutex_exit(&smbus->smbus_imutex); 1005 1006 return (DDI_INTR_CLAIMED); 1007 } 1008 1009 result = smbus_intr_cmn(smbus, SMBUS_INTR); 1010 mutex_exit(&smbus->smbus_imutex); 1011 return (result); 1012 } 1013 1014 /* 1015 * smbus_intr() is the interrupt handler for smbus. 1016 */ 1017 static uint_t 1018 smbus_intr_cmn(smbus_t *smbus, char *src) 1019 { 1020 i2c_transfer_t *tp; 1021 char error_str[128]; 1022 uint8_t status; 1023 int ret = SMBUS_SUCCESS; 1024 timeout_id_t timer_id; 1025 1026 ASSERT(mutex_owned(&smbus->smbus_imutex)); 1027 error_str[0] = '\0'; 1028 1029 smbus_interrupts_off(smbus); 1030 1031 tp = smbus->smbus_cur_tran; 1032 /* 1033 * This only happens when top half is interrupted or 1034 * times out, then the interrupt arrives. Interrupt 1035 * was already disabled by top half, so just exit. 1036 */ 1037 if (tp == NULL) { 1038 return (DDI_INTR_CLAIMED); 1039 } 1040 1041 /* 1042 * This wait is required before reading the status, otherwise 1043 * a parity error can occur which causes a panic. A bug with 1044 * southbridge SMBUS. 1045 */ 1046 drv_usecwait(15); 1047 status = smbus_get(smbus, SMB_STS); 1048 if (smbus->smbus_polling) { 1049 /* 1050 * If we are polling, then we expect not to 1051 * get the right answer for a while, 1052 * so we don't go on to that error stuff 1053 * until we've polled the status for a 1054 * few times. We check for errors here to save time, 1055 * otherwise we would have to wait for the full 1056 * poll timeout before dealing with them. 1057 */ 1058 if (status != (CMD_CMPL|IDLE) && 1059 (status & (FAILED|BUS_ERR|DRV_ERR)) == 0 && 1060 smbus->smbus_poll_retries++ < SMBUS_POLL_MAX_RETRIES) { 1061 return (DDI_INTR_CLAIMED); 1062 } 1063 /* 1064 * else either ... 1065 * [] the command has completed, or; 1066 * [] There has been an error, or; 1067 * [] we timed out waiting for something useful 1068 * to happen, so we go on to to the error handling bit that 1069 * follows, * which will reset the controller then restart the 1070 * whole transaction. 1071 * 1072 * In all cases, clear "poll_retries" for the next command or 1073 * retry 1074 */ 1075 smbus->smbus_poll_retries = 0; 1076 } 1077 1078 /* 1079 * A bug in southbridge SMBUS sometimes requires a reset. Status 1080 * should NOT be IDLE without any other bit set. If it is, the 1081 * transaction should be restarted. 1082 */ 1083 1084 if (status == IDLE) { 1085 (void) sprintf(error_str, "%s bus is idle, ", error_str); 1086 } 1087 1088 if ((status & CMD_CMPL) == 0) { 1089 (void) sprintf(error_str, "%s command failed to complete, ", 1090 error_str); 1091 } 1092 if (status & BUS_ERR) { 1093 (void) sprintf(error_str, "%s bus error, ", error_str); 1094 } 1095 if (status & FAILED) { 1096 (void) sprintf(error_str, "%s failed transaction, ", error_str); 1097 } 1098 if (status & DRV_ERR) { 1099 (void) sprintf(error_str, "%s timeout or bus reset", error_str); 1100 } 1101 1102 if (error_str[0] != '\0') { 1103 (void) sprintf(error_str, "%s %s ", error_str, src); 1104 } 1105 1106 /* 1107 * Clear status to clear the interrupt. 1108 */ 1109 smbus_put(smbus, SMB_STS, 0xff, SMBUS_FLUSH); 1110 if (error_str[0] != '\0') { 1111 smbus_put(smbus, SMB_TYP, KILL, SMBUS_FLUSH); 1112 if (smbus->smbus_retries++ < SMBUS_MAX_RETRIES) { 1113 /* 1114 * XXXX There was a panic here when the 1115 * intr timeout was greater than the timeout 1116 * for the entire transfer. 1117 * 1118 * Restore the value of w_resid before the 1119 * last transaction. r_resid doesn't need to 1120 * be restored because it is only decremented 1121 * after a successful read. Need to do this 1122 * here since smbus_switch() keys off of a 1123 * resid to know whether to call smbus_rd() or 1124 * smbus_wr(). 1125 */ 1126 tp->i2c_w_resid = smbus->smbus_saved_w_resid; 1127 smbus->smbus_bytes_to_read = 0; 1128 1129 SMBUS_PRINT((PRT_INTR_ERR, 1130 "retrying: %s %s w_resid=%d\n", error_str, 1131 src, tp->i2c_w_resid)); 1132 } else { 1133 cmn_err(CE_WARN, "%s max retries exceeded: %s", 1134 smbus->smbus_name, error_str); 1135 /* 1136 * bailing, but first will reset the bus. 1137 */ 1138 smbus_put(smbus, SMB_TYP, KILL, SMBUS_FLUSH); 1139 smbus_put(smbus, SMB_STS, 0xff, SMBUS_FLUSH); 1140 smbus->smbus_cur_tran->i2c_result = I2C_FAILURE; 1141 1142 ret = SMBUS_FAILURE; 1143 } 1144 } else { 1145 smbus->smbus_retries = 0; 1146 } 1147 1148 if (tp != NULL) { 1149 SMBUS_PRINT((PRT_INTR, "flags=%d wresid=%d r_resid=%d %s\n", 1150 tp->i2c_flags, tp->i2c_w_resid, tp->i2c_r_resid, src)); 1151 } 1152 1153 if (ret != SMBUS_FAILURE) { 1154 ret = smbus_switch(smbus); 1155 } 1156 1157 if (smbus->smbus_polling) { 1158 if (ret == SMBUS_COMPLETE || ret == SMBUS_FAILURE) { 1159 smbus->smbus_poll_complete = 1; 1160 } 1161 } else { 1162 /* 1163 * Disable previous timeout. In case it was about to fire this 1164 * will let it exit without doing anything. 1165 */ 1166 timer_id = smbus->smbus_timeout; 1167 smbus->smbus_timeout = 0; 1168 mutex_exit(&smbus->smbus_imutex); 1169 (void) untimeout(timer_id); 1170 mutex_enter(&smbus->smbus_imutex); 1171 if (ret == SMBUS_COMPLETE || ret == SMBUS_FAILURE) { 1172 cv_signal(&smbus->smbus_icv); 1173 } else { 1174 smbus_interrupts_on(smbus); 1175 smbus->smbus_timeout = timeout(smbus_intr_timeout, 1176 smbus, drv_usectohz(intr_timeout)); 1177 SMBUS_PRINT((PRT_INTR, "smbus_intr starting timeout %p " 1178 "%s", smbus->smbus_timeout, src)); 1179 } 1180 } 1181 1182 return (DDI_INTR_CLAIMED); 1183 } 1184 1185 /* 1186 * smbus_wr handles writes to the smbus. Unlike true I2C busses 1187 * such as provided by pcf8584, smbus attaches a start and stop bit for each 1188 * transaction, so this limits writes to the maximum number of bytes 1189 * in a single transaction, which is 33. 1190 * 1191 * If more than 33 bytes are contained in the transfer, a non-zero 1192 * residual has to be returned, and the calling driver has to restart 1193 * another transaction to complete writing out any remaining data. The 1194 * reason for this is that most devices require a register/offset as the 1195 * first byte to be written for each SMBUS transaction. 1196 */ 1197 static int 1198 smbus_wr(smbus_t *smbus) 1199 { 1200 i2c_transfer_t *tp = smbus->smbus_cur_tran; 1201 uint8_t addr = smbus_dip_to_addr(smbus->smbus_cur_dip); 1202 int bytes_written = 0; 1203 uint8_t a; 1204 uint8_t b; 1205 1206 if (tp->i2c_w_resid != tp->i2c_wlen) { 1207 return (SMBUS_COMPLETE); 1208 } 1209 1210 SMBUS_PRINT((PRT_WR, "smbus_wr: addr = %x resid = %d\n", 1211 addr, tp->i2c_w_resid)); 1212 1213 smbus_put(smbus, SMB_STS, 0xff, 0); 1214 1215 /* 1216 * Address must be re-written for each command and it has to 1217 * be written before SMB_TYP. 1218 */ 1219 smbus_put(smbus, DEV_ADDR, addr, 0); 1220 1221 switch (tp->i2c_w_resid) { 1222 1223 case 1: 1224 a = tp->i2c_wbuf[tp->i2c_wlen - tp->i2c_w_resid--]; 1225 smbus_put(smbus, SMB_CMD, a, 0); 1226 smbus_put(smbus, SMB_TYP, SEND_BYTE, 0); 1227 SMBUS_PRINT((PRT_WR, "smbus_wr: send one byte:" 1228 " %d\n", a)); 1229 break; 1230 case 2: 1231 a = tp->i2c_wbuf[tp->i2c_wlen - tp->i2c_w_resid--]; 1232 smbus_put(smbus, SMB_CMD, a, 0); 1233 1234 b = tp->i2c_wbuf[tp->i2c_wlen - tp->i2c_w_resid--]; 1235 smbus_put(smbus, DEV_DATA0, b, 0); 1236 smbus_put(smbus, SMB_TYP, WR_BYTE, 0); 1237 SMBUS_PRINT((PRT_WR, "smbus_wr: send two bytes:" 1238 " %d %d\n", a, b)); 1239 break; 1240 1241 default: 1242 /* 1243 * Write out as many bytes as possible in a single command. 1244 * Note that BLK_DATA just creats a byte stream. ie, the 1245 * smbus protocol is not used or interpreted by this driver. 1246 */ 1247 smbus_put(smbus, SMB_TYP, WR_BLK, 0); 1248 a = tp->i2c_wbuf[tp->i2c_wlen - tp->i2c_w_resid--]; 1249 1250 smbus_put(smbus, SMB_CMD, a, 0); 1251 1252 SMBUS_PRINT((PRT_WR, "smbus_wr: send multiple bytes: ")); 1253 SMBUS_PRINT((PRT_WR, "%x ", a)); 1254 1255 while (tp->i2c_w_resid != 0) { 1256 a = tp->i2c_wbuf[tp->i2c_wlen - tp->i2c_w_resid--]; 1257 smbus_put(smbus, BLK_DATA, a, 0); 1258 SMBUS_PRINT((PRT_WR, "%x ", a)); 1259 /* 1260 * Note that MAX_BLK_SEND defines how many bytes may 1261 * be sent to the BLK_DATA register. The leading byte 1262 * already sent to the SMB_CMD register doesn't count 1263 * But ALL the BLK_DATA bytes count so pre-increment 1264 * bytes_written before testing. 1265 */ 1266 if (++bytes_written == MAX_BLK_SEND) { 1267 break; 1268 } 1269 } 1270 SMBUS_PRINT((PRT_WR, "\n")); 1271 smbus_put(smbus, DEV_DATA0, bytes_written, 0); 1272 break; 1273 } 1274 1275 /* 1276 * writing anything to port reg starts transfer 1277 */ 1278 smbus_put(smbus, STR_PORT, 0, SMBUS_FLUSH); 1279 1280 return (SMBUS_PENDING); 1281 } 1282 1283 /* 1284 * smbus_rd handles reads to the smbus. Unlike a true I2C bus 1285 * such as provided by pcf8584, smbus attaches a start and stop bit 1286 * for each transaction, which limits reads to the maximum number of 1287 * bytes in a single SMBUS transaction. (Block reads don't 1288 * seem to work on smbus, and the southbridge documentation is poor). 1289 * 1290 * It doesn't appear that reads spanning multiple I2C transactions 1291 * (ie each with a start-stop) affects the transfer when reading 1292 * multiple bytes from devices with internal counters. The counter 1293 * is correctly maintained. 1294 * 1295 * RD_WORD and RD_BYTE write out the byte in the SMB_CMD register 1296 * before reading, so RCV_BYTE is used instead. 1297 * 1298 * Multi-byte reads iniatiate a SMBUS transaction for each byte to be 1299 * received. Because register/offset information doesn't need to 1300 * be resent for each I2C transaction (as opposed to when writing data), 1301 * the driver can continue reading data in separate SMBUS transactions 1302 * until the requested buffer is filled. 1303 */ 1304 static int 1305 smbus_rd(smbus_t *smbus) 1306 { 1307 i2c_transfer_t *tp = smbus->smbus_cur_tran; 1308 uint8_t addr = smbus_dip_to_addr(smbus->smbus_cur_dip); 1309 1310 if (smbus->smbus_bytes_to_read == 1) { 1311 tp->i2c_rbuf[tp->i2c_rlen - tp->i2c_r_resid] = 1312 smbus_get(smbus, DEV_DATA0); 1313 SMBUS_PRINT((PRT_RD, "smbus_rd: data in = %d\n", 1314 tp->i2c_rbuf[tp->i2c_rlen - tp->i2c_r_resid])); 1315 tp->i2c_r_resid--; 1316 smbus->smbus_bytes_to_read = 0; 1317 1318 if (tp->i2c_r_resid == 0) { 1319 return (SMBUS_COMPLETE); 1320 } 1321 } 1322 1323 /* 1324 * Address must be re-written for each command. It must 1325 * be written before SMB_TYP. 1326 */ 1327 smbus_put(smbus, DEV_ADDR, addr | I2C_READ, 0); 1328 1329 if (tp->i2c_r_resid == 0) { 1330 smbus->smbus_bytes_to_read = 0; 1331 1332 return (SMBUS_COMPLETE); 1333 } 1334 1335 smbus->smbus_bytes_to_read = 1; 1336 smbus_put(smbus, SMB_TYP, RCV_BYTE, 0); 1337 1338 smbus_put(smbus, SMB_STS, 0xff, 0); 1339 1340 SMBUS_PRINT((PRT_RD, "smbus_rd: starting a read addr = %x resid = %d " 1341 "bytes_to_read=%d\n", addr, tp->i2c_r_resid, 1342 smbus->smbus_bytes_to_read)); 1343 1344 smbus_put(smbus, STR_PORT, 0, SMBUS_FLUSH); 1345 1346 return (SMBUS_PENDING); 1347 } 1348