1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/sysmacros.h> 32 #include <sys/sunddi.h> 33 #include <sys/esunddi.h> 34 #include <sys/platform_module.h> 35 #include <sys/errno.h> 36 #include <sys/lgrp.h> 37 #include <sys/memnode.h> 38 #include <sys/promif.h> 39 40 int (*p2get_mem_unum)(int, uint64_t, char *, int, int *); 41 42 void 43 startup_platform(void) 44 { 45 } 46 47 int 48 set_platform_tsb_spares() 49 { 50 return (0); 51 } 52 53 void 54 set_platform_defaults(void) 55 { 56 } 57 58 /* 59 * Definitions for accessing the pci config space of the isa node 60 * of Southbridge. 61 */ 62 #define ENCHILADA_ISA_PATHNAME "/pci@1e,600000/isa@7" 63 static ddi_acc_handle_t isa_handle; /* handle for isa pci space */ 64 65 66 void 67 load_platform_drivers(void) 68 { 69 dev_info_t *dip; /* dip of the isa driver */ 70 71 /* 72 * Install power driver which handles the power button. 73 */ 74 if (i_ddi_attach_hw_nodes("power") != DDI_SUCCESS) 75 cmn_err(CE_WARN, "Failed to install \"power\" driver."); 76 (void) ddi_hold_driver(ddi_name_to_major("power")); 77 78 /* 79 * It is OK to return error because 'us' driver is not available 80 * in all clusters (e.g. missing in Core cluster). 81 */ 82 (void) i_ddi_attach_hw_nodes("us"); 83 84 if (i_ddi_attach_hw_nodes("grbeep") != DDI_SUCCESS) 85 cmn_err(CE_WARN, "Failed to install \"beep\" driver."); 86 87 88 /* 89 * mc-us3i must stay loaded for plat_get_mem_unum() 90 */ 91 if (i_ddi_attach_hw_nodes("mc-us3i") != DDI_SUCCESS) 92 cmn_err(CE_WARN, "mc-us3i driver failed to install"); 93 (void) ddi_hold_driver(ddi_name_to_major("mc-us3i")); 94 95 /* 96 * Install Isa driver. This is required for the southbridge IDE 97 * workaround - to reset the IDE channel during IDE bus reset. 98 * Panic the system in case ISA driver could not be loaded or 99 * any problem in accessing its pci config space. Since the register 100 * to reset the channel for IDE is in ISA config space!. 101 */ 102 103 dip = e_ddi_hold_devi_by_path(ENCHILADA_ISA_PATHNAME, 0); 104 if (dip == NULL) { 105 cmn_err(CE_PANIC, "Could not install the isa driver\n"); 106 return; 107 } 108 109 if (pci_config_setup(dip, &isa_handle) != DDI_SUCCESS) { 110 cmn_err(CE_PANIC, "Could not get the config space of isa\n"); 111 return; 112 } 113 } 114 115 /* 116 * This routine provides a workaround for a bug in the SB chip which 117 * can cause data corruption. Will be invoked from the IDE HBA driver for 118 * Acer SouthBridge at the time of IDE bus reset. 119 */ 120 /*ARGSUSED*/ 121 int 122 plat_ide_chipreset(dev_info_t *dip, int chno) 123 { 124 uint8_t val; 125 int ret = DDI_SUCCESS; 126 127 if (isa_handle == NULL) { 128 return (DDI_FAILURE); 129 } 130 131 val = pci_config_get8(isa_handle, 0x58); 132 /* 133 * The dip passed as the argument is not used here. 134 * This will be needed for platforms which have multiple on-board SB, 135 * The dip passed will be used to match the corresponding ISA node. 136 */ 137 switch (chno) { 138 case 0: 139 /* 140 * First disable the primary channel then re-enable it. 141 * As per ALI no wait should be required in between have 142 * given 1ms delay in between to be on safer side. 143 * bit 2 of register 0x58 when 0 disable the channel 0. 144 * bit 2 of register 0x58 when 1 enables the channel 0. 145 */ 146 pci_config_put8(isa_handle, 0x58, val & 0xFB); 147 drv_usecwait(1000); 148 pci_config_put8(isa_handle, 0x58, val); 149 break; 150 case 1: 151 /* 152 * bit 3 of register 0x58 when 0 disable the channel 1. 153 * bit 3 of register 0x58 when 1 enables the channel 1. 154 */ 155 pci_config_put8(isa_handle, 0x58, val & 0xF7); 156 drv_usecwait(1000); 157 pci_config_put8(isa_handle, 0x58, val); 158 break; 159 default: 160 /* 161 * Unknown channel number passed. Return failure. 162 */ 163 ret = DDI_FAILURE; 164 } 165 166 return (ret); 167 } 168 169 170 /*ARGSUSED*/ 171 int 172 plat_cpu_poweron(struct cpu *cp) 173 { 174 return (ENOTSUP); /* not supported on this platform */ 175 } 176 177 /*ARGSUSED*/ 178 int 179 plat_cpu_poweroff(struct cpu *cp) 180 { 181 return (ENOTSUP); /* not supported on this platform */ 182 } 183 184 /*ARGSUSED*/ 185 void 186 plat_freelist_process(int mnode) 187 { 188 } 189 190 char *platform_module_list[] = { 191 "m1535ppm", 192 "jbusppm", 193 "ics951601", 194 "pca9556", 195 "ppm", 196 (char *)0 197 }; 198 199 /*ARGSUSED*/ 200 void 201 plat_tod_fault(enum tod_fault_type tod_bad) 202 { 203 } 204 205 /*ARGSUSED*/ 206 int 207 plat_get_mem_unum(int synd_code, uint64_t flt_addr, int flt_bus_id, 208 int flt_in_memory, ushort_t flt_status, char *buf, int buflen, int *lenp) 209 { 210 if (flt_in_memory && (p2get_mem_unum != NULL)) 211 return (p2get_mem_unum(synd_code, P2ALIGN(flt_addr, 8), 212 buf, buflen, lenp)); 213 else 214 return (ENOTSUP); 215 } 216 217 /*ARGSUSED*/ 218 int 219 plat_get_cpu_unum(int cpuid, char *buf, int buflen, int *lenp) 220 { 221 if (snprintf(buf, buflen, "MB") >= buflen) { 222 return (ENOSPC); 223 } else { 224 *lenp = strlen(buf); 225 return (0); 226 } 227 } 228 229 /* 230 * Fiesta support for lgroups. 231 * 232 * On fiesta platform, an lgroup platform handle == CPU id 233 */ 234 235 /* 236 * Macro for extracting the CPU number from the CPU id 237 */ 238 #define CPUID_TO_LGRP(id) ((id) & 0x7) 239 #define ENCHILADA_MC_SHIFT 36 240 241 /* 242 * Return the platform handle for the lgroup containing the given CPU 243 */ 244 lgrp_handle_t 245 plat_lgrp_cpu_to_hand(processorid_t id) 246 { 247 return (CPUID_TO_LGRP(id)); 248 } 249 250 /* 251 * Platform specific lgroup initialization 252 */ 253 void 254 plat_lgrp_init(void) 255 { 256 pnode_t curnode; 257 char tmp_name[MAXSYSNAME]; 258 int portid; 259 int cpucnt = 0; 260 int max_portid = -1; 261 extern uint32_t lgrp_expand_proc_thresh; 262 extern uint32_t lgrp_expand_proc_diff; 263 extern pgcnt_t lgrp_mem_free_thresh; 264 extern uint32_t lgrp_loadavg_tolerance; 265 extern uint32_t lgrp_loadavg_max_effect; 266 extern uint32_t lgrp_load_thresh; 267 extern lgrp_mem_policy_t lgrp_mem_policy_root; 268 269 /* 270 * Count the number of CPUs installed to determine if 271 * NUMA optimization should be enabled or not. 272 * 273 * All CPU nodes reside in the root node and have a 274 * device type "cpu". 275 */ 276 curnode = prom_rootnode(); 277 for (curnode = prom_childnode(curnode); curnode; 278 curnode = prom_nextnode(curnode)) { 279 bzero(tmp_name, MAXSYSNAME); 280 if (prom_getprop(curnode, OBP_NAME, (caddr_t)tmp_name) == -1 || 281 prom_getprop(curnode, OBP_DEVICETYPE, tmp_name) == -1 || 282 strcmp(tmp_name, "cpu") != 0) 283 continue; 284 285 cpucnt++; 286 if (prom_getprop(curnode, "portid", (caddr_t)&portid) != -1 && 287 portid > max_portid) 288 max_portid = portid; 289 } 290 if (cpucnt <= 1) 291 max_mem_nodes = 1; 292 else if (max_portid >= 0 && max_portid < MAX_MEM_NODES) 293 max_mem_nodes = max_portid + 1; 294 295 /* 296 * Set tuneables for fiesta architecture 297 * 298 * lgrp_expand_proc_thresh is the minimum load on the lgroups 299 * this process is currently running on before considering 300 * expanding threads to another lgroup. 301 * 302 * lgrp_expand_proc_diff determines how much less the remote lgroup 303 * must be loaded before expanding to it. 304 * 305 * Optimize for memory bandwidth by spreading multi-threaded 306 * program to different lgroups. 307 */ 308 lgrp_expand_proc_thresh = lgrp_loadavg_max_effect - 1; 309 lgrp_expand_proc_diff = lgrp_loadavg_max_effect / 2; 310 lgrp_loadavg_tolerance = lgrp_loadavg_max_effect / 2; 311 lgrp_mem_free_thresh = 1; /* home lgrp must have some memory */ 312 lgrp_expand_proc_thresh = lgrp_loadavg_max_effect - 1; 313 lgrp_mem_policy_root = LGRP_MEM_POLICY_NEXT; 314 lgrp_load_thresh = 0; 315 316 mem_node_pfn_shift = ENCHILADA_MC_SHIFT - MMU_PAGESHIFT; 317 } 318 319 /* 320 * Return latency between "from" and "to" lgroups 321 * 322 * This latency number can only be used for relative comparison 323 * between lgroups on the running system, cannot be used across platforms, 324 * and may not reflect the actual latency. It is platform and implementation 325 * specific, so platform gets to decide its value. It would be nice if the 326 * number was at least proportional to make comparisons more meaningful though. 327 * NOTE: The numbers below are supposed to be load latencies for uncached 328 * memory divided by 10. 329 */ 330 int 331 plat_lgrp_latency(lgrp_handle_t from, lgrp_handle_t to) 332 { 333 /* 334 * Return remote latency when there are more than two lgroups 335 * (root and child) and getting latency between two different 336 * lgroups or root is involved 337 */ 338 if (lgrp_optimizations() && (from != to || 339 from == LGRP_DEFAULT_HANDLE || to == LGRP_DEFAULT_HANDLE)) 340 return (17); 341 else 342 return (12); 343 } 344 345 int 346 plat_pfn_to_mem_node(pfn_t pfn) 347 { 348 ASSERT(max_mem_nodes > 1); 349 return (pfn >> mem_node_pfn_shift); 350 } 351 352 /* 353 * Assign memnode to lgroups 354 */ 355 void 356 plat_fill_mc(pnode_t nodeid) 357 { 358 int portid; 359 360 /* 361 * Enchilada memory controller portid == global CPU id 362 */ 363 if ((prom_getprop(nodeid, "portid", (caddr_t)&portid) == -1) || 364 (portid < 0)) 365 return; 366 367 if (portid < max_mem_nodes) 368 plat_assign_lgrphand_to_mem_node(portid, portid); 369 } 370 371 /* ARGSUSED */ 372 void 373 plat_build_mem_nodes(u_longlong_t *list, size_t nelems) 374 { 375 size_t elem; 376 pfn_t basepfn; 377 pgcnt_t npgs; 378 379 /* 380 * Boot install lists are arranged <addr, len>, <addr, len>, ... 381 */ 382 for (elem = 0; elem < nelems; elem += 2) { 383 basepfn = btop(list[elem]); 384 npgs = btop(list[elem+1]); 385 mem_node_add_slice(basepfn, basepfn + npgs - 1); 386 } 387 } 388