1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/param.h> 29 #include <sys/systm.h> 30 #include <sys/sysmacros.h> 31 #include <sys/sunddi.h> 32 #include <sys/esunddi.h> 33 #include <sys/platform_module.h> 34 #include <sys/errno.h> 35 #include <sys/lgrp.h> 36 #include <sys/memnode.h> 37 #include <sys/promif.h> 38 39 int (*p2get_mem_unum)(int, uint64_t, char *, int, int *); 40 41 void 42 startup_platform(void) 43 { 44 } 45 46 int 47 set_platform_tsb_spares() 48 { 49 return (0); 50 } 51 52 void 53 set_platform_defaults(void) 54 { 55 } 56 57 /* 58 * Definitions for accessing the pci config space of the isa node 59 * of Southbridge. 60 */ 61 #define ENCHILADA_ISA_PATHNAME "/pci@1e,600000/isa@7" 62 static ddi_acc_handle_t isa_handle; /* handle for isa pci space */ 63 64 65 void 66 load_platform_drivers(void) 67 { 68 dev_info_t *dip; /* dip of the isa driver */ 69 70 /* 71 * Install power driver which handles the power button. 72 */ 73 if (i_ddi_attach_hw_nodes("power") != DDI_SUCCESS) 74 cmn_err(CE_WARN, "Failed to install \"power\" driver."); 75 (void) ddi_hold_driver(ddi_name_to_major("power")); 76 77 /* 78 * It is OK to return error because 'us' driver is not available 79 * in all clusters (e.g. missing in Core cluster). 80 */ 81 (void) i_ddi_attach_hw_nodes("us"); 82 83 if (i_ddi_attach_hw_nodes("grbeep") != DDI_SUCCESS) 84 cmn_err(CE_WARN, "Failed to install \"beep\" driver."); 85 86 87 /* 88 * mc-us3i must stay loaded for plat_get_mem_unum() 89 */ 90 if (i_ddi_attach_hw_nodes("mc-us3i") != DDI_SUCCESS) 91 cmn_err(CE_WARN, "mc-us3i driver failed to install"); 92 (void) ddi_hold_driver(ddi_name_to_major("mc-us3i")); 93 94 /* 95 * Install Isa driver. This is required for the southbridge IDE 96 * workaround - to reset the IDE channel during IDE bus reset. 97 * Panic the system in case ISA driver could not be loaded or 98 * any problem in accessing its pci config space. Since the register 99 * to reset the channel for IDE is in ISA config space!. 100 */ 101 102 dip = e_ddi_hold_devi_by_path(ENCHILADA_ISA_PATHNAME, 0); 103 if (dip == NULL) { 104 cmn_err(CE_PANIC, "Could not install the isa driver\n"); 105 return; 106 } 107 108 if (pci_config_setup(dip, &isa_handle) != DDI_SUCCESS) { 109 cmn_err(CE_PANIC, "Could not get the config space of isa\n"); 110 return; 111 } 112 } 113 114 /* 115 * This routine provides a workaround for a bug in the SB chip which 116 * can cause data corruption. Will be invoked from the IDE HBA driver for 117 * Acer SouthBridge at the time of IDE bus reset. 118 */ 119 /*ARGSUSED*/ 120 int 121 plat_ide_chipreset(dev_info_t *dip, int chno) 122 { 123 uint8_t val; 124 int ret = DDI_SUCCESS; 125 126 if (isa_handle == NULL) { 127 return (DDI_FAILURE); 128 } 129 130 val = pci_config_get8(isa_handle, 0x58); 131 /* 132 * The dip passed as the argument is not used here. 133 * This will be needed for platforms which have multiple on-board SB, 134 * The dip passed will be used to match the corresponding ISA node. 135 */ 136 switch (chno) { 137 case 0: 138 /* 139 * First disable the primary channel then re-enable it. 140 * As per ALI no wait should be required in between have 141 * given 1ms delay in between to be on safer side. 142 * bit 2 of register 0x58 when 0 disable the channel 0. 143 * bit 2 of register 0x58 when 1 enables the channel 0. 144 */ 145 pci_config_put8(isa_handle, 0x58, val & 0xFB); 146 drv_usecwait(1000); 147 pci_config_put8(isa_handle, 0x58, val); 148 break; 149 case 1: 150 /* 151 * bit 3 of register 0x58 when 0 disable the channel 1. 152 * bit 3 of register 0x58 when 1 enables the channel 1. 153 */ 154 pci_config_put8(isa_handle, 0x58, val & 0xF7); 155 drv_usecwait(1000); 156 pci_config_put8(isa_handle, 0x58, val); 157 break; 158 default: 159 /* 160 * Unknown channel number passed. Return failure. 161 */ 162 ret = DDI_FAILURE; 163 } 164 165 return (ret); 166 } 167 168 169 /*ARGSUSED*/ 170 int 171 plat_cpu_poweron(struct cpu *cp) 172 { 173 return (ENOTSUP); /* not supported on this platform */ 174 } 175 176 /*ARGSUSED*/ 177 int 178 plat_cpu_poweroff(struct cpu *cp) 179 { 180 return (ENOTSUP); /* not supported on this platform */ 181 } 182 183 /*ARGSUSED*/ 184 void 185 plat_freelist_process(int mnode) 186 { 187 } 188 189 char *platform_module_list[] = { 190 "m1535ppm", 191 "jbusppm", 192 "ics951601", 193 "pca9556", 194 "ppm", 195 (char *)0 196 }; 197 198 /*ARGSUSED*/ 199 void 200 plat_tod_fault(enum tod_fault_type tod_bad) 201 { 202 } 203 204 /*ARGSUSED*/ 205 int 206 plat_get_mem_unum(int synd_code, uint64_t flt_addr, int flt_bus_id, 207 int flt_in_memory, ushort_t flt_status, char *buf, int buflen, int *lenp) 208 { 209 if (flt_in_memory && (p2get_mem_unum != NULL)) 210 return (p2get_mem_unum(synd_code, P2ALIGN(flt_addr, 8), 211 buf, buflen, lenp)); 212 else 213 return (ENOTSUP); 214 } 215 216 /*ARGSUSED*/ 217 int 218 plat_get_cpu_unum(int cpuid, char *buf, int buflen, int *lenp) 219 { 220 if (snprintf(buf, buflen, "MB") >= buflen) { 221 return (ENOSPC); 222 } else { 223 *lenp = strlen(buf); 224 return (0); 225 } 226 } 227 228 /* 229 * Fiesta support for lgroups. 230 * 231 * On fiesta platform, an lgroup platform handle == CPU id 232 */ 233 234 /* 235 * Macro for extracting the CPU number from the CPU id 236 */ 237 #define CPUID_TO_LGRP(id) ((id) & 0x7) 238 #define ENCHILADA_MC_SHIFT 36 239 240 /* 241 * Return the platform handle for the lgroup containing the given CPU 242 */ 243 lgrp_handle_t 244 plat_lgrp_cpu_to_hand(processorid_t id) 245 { 246 return (CPUID_TO_LGRP(id)); 247 } 248 249 /* 250 * Platform specific lgroup initialization 251 */ 252 void 253 plat_lgrp_init(void) 254 { 255 pnode_t curnode; 256 char tmp_name[MAXSYSNAME]; 257 int portid; 258 int cpucnt = 0; 259 int max_portid = -1; 260 extern uint32_t lgrp_expand_proc_thresh; 261 extern uint32_t lgrp_expand_proc_diff; 262 extern pgcnt_t lgrp_mem_free_thresh; 263 extern uint32_t lgrp_loadavg_tolerance; 264 extern uint32_t lgrp_loadavg_max_effect; 265 extern uint32_t lgrp_load_thresh; 266 extern lgrp_mem_policy_t lgrp_mem_policy_root; 267 268 /* 269 * Count the number of CPUs installed to determine if 270 * NUMA optimization should be enabled or not. 271 * 272 * All CPU nodes reside in the root node and have a 273 * device type "cpu". 274 */ 275 curnode = prom_rootnode(); 276 for (curnode = prom_childnode(curnode); curnode; 277 curnode = prom_nextnode(curnode)) { 278 bzero(tmp_name, MAXSYSNAME); 279 if (prom_getprop(curnode, OBP_NAME, (caddr_t)tmp_name) == -1 || 280 prom_getprop(curnode, OBP_DEVICETYPE, tmp_name) == -1 || 281 strcmp(tmp_name, "cpu") != 0) 282 continue; 283 284 cpucnt++; 285 if (prom_getprop(curnode, "portid", (caddr_t)&portid) != -1 && 286 portid > max_portid) 287 max_portid = portid; 288 } 289 if (cpucnt <= 1) 290 max_mem_nodes = 1; 291 else if (max_portid >= 0 && max_portid < MAX_MEM_NODES) 292 max_mem_nodes = max_portid + 1; 293 294 /* 295 * Set tuneables for fiesta architecture 296 * 297 * lgrp_expand_proc_thresh is the minimum load on the lgroups 298 * this process is currently running on before considering 299 * expanding threads to another lgroup. 300 * 301 * lgrp_expand_proc_diff determines how much less the remote lgroup 302 * must be loaded before expanding to it. 303 * 304 * Optimize for memory bandwidth by spreading multi-threaded 305 * program to different lgroups. 306 */ 307 lgrp_expand_proc_thresh = lgrp_loadavg_max_effect - 1; 308 lgrp_expand_proc_diff = lgrp_loadavg_max_effect / 2; 309 lgrp_loadavg_tolerance = lgrp_loadavg_max_effect / 2; 310 lgrp_mem_free_thresh = 1; /* home lgrp must have some memory */ 311 lgrp_expand_proc_thresh = lgrp_loadavg_max_effect - 1; 312 lgrp_mem_policy_root = LGRP_MEM_POLICY_NEXT; 313 lgrp_load_thresh = 0; 314 315 mem_node_pfn_shift = ENCHILADA_MC_SHIFT - MMU_PAGESHIFT; 316 } 317 318 /* 319 * Return latency between "from" and "to" lgroups 320 * 321 * This latency number can only be used for relative comparison 322 * between lgroups on the running system, cannot be used across platforms, 323 * and may not reflect the actual latency. It is platform and implementation 324 * specific, so platform gets to decide its value. It would be nice if the 325 * number was at least proportional to make comparisons more meaningful though. 326 * NOTE: The numbers below are supposed to be load latencies for uncached 327 * memory divided by 10. 328 */ 329 int 330 plat_lgrp_latency(lgrp_handle_t from, lgrp_handle_t to) 331 { 332 /* 333 * Return remote latency when there are more than two lgroups 334 * (root and child) and getting latency between two different 335 * lgroups or root is involved 336 */ 337 if (lgrp_optimizations() && (from != to || 338 from == LGRP_DEFAULT_HANDLE || to == LGRP_DEFAULT_HANDLE)) 339 return (17); 340 else 341 return (12); 342 } 343 344 int 345 plat_pfn_to_mem_node(pfn_t pfn) 346 { 347 ASSERT(max_mem_nodes > 1); 348 return (pfn >> mem_node_pfn_shift); 349 } 350 351 /* 352 * Assign memnode to lgroups 353 */ 354 void 355 plat_fill_mc(pnode_t nodeid) 356 { 357 int portid; 358 359 /* 360 * Enchilada memory controller portid == global CPU id 361 */ 362 if ((prom_getprop(nodeid, "portid", (caddr_t)&portid) == -1) || 363 (portid < 0)) 364 return; 365 366 if (portid < max_mem_nodes) 367 plat_assign_lgrphand_to_mem_node(portid, portid); 368 } 369