1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/types.h> 29 #include <sys/systm.h> 30 #include <sys/ddi.h> 31 #include <sys/sysmacros.h> 32 #include <sys/archsystm.h> 33 #include <sys/vmsystm.h> 34 #include <sys/machparam.h> 35 #include <sys/machsystm.h> 36 #include <sys/machthread.h> 37 #include <sys/cpu.h> 38 #include <sys/cmp.h> 39 #include <sys/elf_SPARC.h> 40 #include <vm/hat_sfmmu.h> 41 #include <vm/seg_kmem.h> 42 #include <sys/cpuvar.h> 43 #include <sys/cheetahregs.h> 44 #include <sys/us3_module.h> 45 #include <sys/async.h> 46 #include <sys/cmn_err.h> 47 #include <sys/debug.h> 48 #include <sys/dditypes.h> 49 #include <sys/prom_debug.h> 50 #include <sys/prom_plat.h> 51 #include <sys/cpu_module.h> 52 #include <sys/sysmacros.h> 53 #include <sys/intreg.h> 54 #include <sys/clock.h> 55 #include <sys/platform_module.h> 56 #include <sys/machtrap.h> 57 #include <sys/ontrap.h> 58 #include <sys/panic.h> 59 #include <sys/memlist.h> 60 #include <sys/bootconf.h> 61 #include <sys/ivintr.h> 62 #include <sys/atomic.h> 63 #include <sys/fm/protocol.h> 64 #include <sys/fm/cpu/UltraSPARC-III.h> 65 #include <vm/vm_dep.h> 66 67 #ifdef CHEETAHPLUS_ERRATUM_25 68 #include <sys/cyclic.h> 69 #endif /* CHEETAHPLUS_ERRATUM_25 */ 70 71 /* 72 * Note that 'Cheetah PRM' refers to: 73 * SPARC V9 JPS1 Implementation Supplement: Sun UltraSPARC-III 74 */ 75 76 /* 77 * Setup trap handlers. 78 */ 79 void 80 cpu_init_trap(void) 81 { 82 CH_SET_TRAP(tt_pil15, ch_pil15_interrupt_instr); 83 84 CH_SET_TRAP(tt0_fecc, fecc_err_instr); 85 CH_SET_TRAP(tt1_fecc, fecc_err_tl1_instr); 86 CH_SET_TRAP(tt1_swtrap0, fecc_err_tl1_cont_instr); 87 } 88 89 static int 90 getintprop(pnode_t node, char *name, int deflt) 91 { 92 int value; 93 94 switch (prom_getproplen(node, name)) { 95 case sizeof (int): 96 (void) prom_getprop(node, name, (caddr_t)&value); 97 break; 98 99 default: 100 value = deflt; 101 break; 102 } 103 104 return (value); 105 } 106 107 /* 108 * Set the magic constants of the implementation. 109 */ 110 /*ARGSUSED*/ 111 void 112 cpu_fiximp(pnode_t dnode) 113 { 114 int i, a; 115 116 static struct { 117 char *name; 118 int *var; 119 int defval; 120 } prop[] = { 121 "dcache-size", &dcache_size, CH_DCACHE_SIZE, 122 "dcache-line-size", &dcache_linesize, CH_DCACHE_LSIZE, 123 "icache-size", &icache_size, CH_ICACHE_SIZE, 124 "icache-line-size", &icache_linesize, CH_ICACHE_LSIZE, 125 "ecache-size", &ecache_size, CH_ECACHE_MAX_SIZE, 126 "ecache-line-size", &ecache_alignsize, CH_ECACHE_MAX_LSIZE, 127 "ecache-associativity", &ecache_associativity, CH_ECACHE_NWAY 128 }; 129 130 for (i = 0; i < sizeof (prop) / sizeof (prop[0]); i++) 131 *prop[i].var = getintprop(dnode, prop[i].name, prop[i].defval); 132 133 ecache_setsize = ecache_size / ecache_associativity; 134 135 vac_size = CH_VAC_SIZE; 136 vac_mask = MMU_PAGEMASK & (vac_size - 1); 137 i = 0; a = vac_size; 138 while (a >>= 1) 139 ++i; 140 vac_shift = i; 141 shm_alignment = vac_size; 142 vac = 1; 143 144 /* 145 * Cheetah's large page support has problems with large numbers of 146 * large pages, so just disable large pages out-of-the-box. 147 * Note that the other defaults are set in sun4u/vm/mach_vm_dep.c. 148 */ 149 max_uheap_lpsize = MMU_PAGESIZE; 150 max_ustack_lpsize = MMU_PAGESIZE; 151 max_privmap_lpsize = MMU_PAGESIZE; 152 max_utext_lpsize = MMU_PAGESIZE; 153 max_shm_lpsize = MMU_PAGESIZE; 154 } 155 156 void 157 send_mondo_set(cpuset_t set) 158 { 159 int lo, busy, nack, shipped = 0; 160 uint16_t i, cpuids[IDSR_BN_SETS]; 161 uint64_t idsr, nackmask = 0, busymask, curnack, curbusy; 162 uint64_t starttick, endtick, tick, lasttick; 163 #if (NCPU > IDSR_BN_SETS) 164 int index = 0; 165 int ncpuids = 0; 166 #endif 167 #ifdef CHEETAHPLUS_ERRATUM_25 168 int recovered = 0; 169 int cpuid; 170 #endif 171 172 ASSERT(!CPUSET_ISNULL(set)); 173 starttick = lasttick = gettick(); 174 175 #if (NCPU <= IDSR_BN_SETS) 176 for (i = 0; i < NCPU; i++) 177 if (CPU_IN_SET(set, i)) { 178 shipit(i, shipped); 179 nackmask |= IDSR_NACK_BIT(shipped); 180 cpuids[shipped++] = i; 181 CPUSET_DEL(set, i); 182 if (CPUSET_ISNULL(set)) 183 break; 184 } 185 CPU_STATS_ADDQ(CPU, sys, xcalls, shipped); 186 #else 187 for (i = 0; i < NCPU; i++) 188 if (CPU_IN_SET(set, i)) { 189 ncpuids++; 190 191 /* 192 * Ship only to the first (IDSR_BN_SETS) CPUs. If we 193 * find we have shipped to more than (IDSR_BN_SETS) 194 * CPUs, set "index" to the highest numbered CPU in 195 * the set so we can ship to other CPUs a bit later on. 196 */ 197 if (shipped < IDSR_BN_SETS) { 198 shipit(i, shipped); 199 nackmask |= IDSR_NACK_BIT(shipped); 200 cpuids[shipped++] = i; 201 CPUSET_DEL(set, i); 202 if (CPUSET_ISNULL(set)) 203 break; 204 } else 205 index = (int)i; 206 } 207 208 CPU_STATS_ADDQ(CPU, sys, xcalls, ncpuids); 209 #endif 210 211 busymask = IDSR_NACK_TO_BUSY(nackmask); 212 busy = nack = 0; 213 endtick = starttick + xc_tick_limit; 214 for (;;) { 215 idsr = getidsr(); 216 #if (NCPU <= IDSR_BN_SETS) 217 if (idsr == 0) 218 break; 219 #else 220 if (idsr == 0 && shipped == ncpuids) 221 break; 222 #endif 223 tick = gettick(); 224 /* 225 * If there is a big jump between the current tick 226 * count and lasttick, we have probably hit a break 227 * point. Adjust endtick accordingly to avoid panic. 228 */ 229 if (tick > (lasttick + xc_tick_jump_limit)) 230 endtick += (tick - lasttick); 231 lasttick = tick; 232 if (tick > endtick) { 233 if (panic_quiesce) 234 return; 235 #ifdef CHEETAHPLUS_ERRATUM_25 236 cpuid = -1; 237 for (i = 0; i < IDSR_BN_SETS; i++) { 238 if (idsr & (IDSR_NACK_BIT(i) | 239 IDSR_BUSY_BIT(i))) { 240 cpuid = cpuids[i]; 241 break; 242 } 243 } 244 if (cheetah_sendmondo_recover && cpuid != -1 && 245 recovered == 0) { 246 if (mondo_recover(cpuid, i)) { 247 /* 248 * We claimed the whole memory or 249 * full scan is disabled. 250 */ 251 recovered++; 252 } 253 tick = gettick(); 254 endtick = tick + xc_tick_limit; 255 lasttick = tick; 256 /* 257 * Recheck idsr 258 */ 259 continue; 260 } else 261 #endif /* CHEETAHPLUS_ERRATUM_25 */ 262 { 263 cmn_err(CE_CONT, "send mondo timeout " 264 "[%d NACK %d BUSY]\nIDSR 0x%" 265 "" PRIx64 " cpuids:", nack, busy, idsr); 266 for (i = 0; i < IDSR_BN_SETS; i++) { 267 if (idsr & (IDSR_NACK_BIT(i) | 268 IDSR_BUSY_BIT(i))) { 269 cmn_err(CE_CONT, " 0x%x", 270 cpuids[i]); 271 } 272 } 273 cmn_err(CE_CONT, "\n"); 274 cmn_err(CE_PANIC, "send_mondo_set: timeout"); 275 } 276 } 277 curnack = idsr & nackmask; 278 curbusy = idsr & busymask; 279 #if (NCPU > IDSR_BN_SETS) 280 if (shipped < ncpuids) { 281 uint64_t cpus_left; 282 uint16_t next = (uint16_t)index; 283 284 cpus_left = ~(IDSR_NACK_TO_BUSY(curnack) | curbusy) & 285 busymask; 286 287 if (cpus_left) { 288 do { 289 /* 290 * Sequence through and ship to the 291 * remainder of the CPUs in the system 292 * (e.g. other than the first 293 * (IDSR_BN_SETS)) in reverse order. 294 */ 295 lo = lowbit(cpus_left) - 1; 296 i = IDSR_BUSY_IDX(lo); 297 shipit(next, i); 298 shipped++; 299 cpuids[i] = next; 300 301 /* 302 * If we've processed all the CPUs, 303 * exit the loop now and save 304 * instructions. 305 */ 306 if (shipped == ncpuids) 307 break; 308 309 for ((index = ((int)next - 1)); 310 index >= 0; index--) 311 if (CPU_IN_SET(set, index)) { 312 next = (uint16_t)index; 313 break; 314 } 315 316 cpus_left &= ~(1ull << lo); 317 } while (cpus_left); 318 #ifdef CHEETAHPLUS_ERRATUM_25 319 /* 320 * Clear recovered because we are sending to 321 * a new set of targets. 322 */ 323 recovered = 0; 324 #endif 325 continue; 326 } 327 } 328 #endif 329 if (curbusy) { 330 busy++; 331 continue; 332 } 333 334 #ifdef SEND_MONDO_STATS 335 { 336 int n = gettick() - starttick; 337 if (n < 8192) 338 x_nack_stimes[n >> 7]++; 339 } 340 #endif 341 while (gettick() < (tick + sys_clock_mhz)) 342 ; 343 do { 344 lo = lowbit(curnack) - 1; 345 i = IDSR_NACK_IDX(lo); 346 shipit(cpuids[i], i); 347 curnack &= ~(1ull << lo); 348 } while (curnack); 349 nack++; 350 busy = 0; 351 } 352 #ifdef SEND_MONDO_STATS 353 { 354 int n = gettick() - starttick; 355 if (n < 8192) 356 x_set_stimes[n >> 7]++; 357 else 358 x_set_ltimes[(n >> 13) & 0xf]++; 359 } 360 x_set_cpus[shipped]++; 361 #endif 362 } 363 364 /* 365 * Handles error logging for implementation specific error types. 366 */ 367 /*ARGSUSED*/ 368 int 369 cpu_impl_async_log_err(void *flt, errorq_elem_t *eqep) 370 { 371 /* There aren't any error types which are specific to cheetah only */ 372 return (CH_ASYNC_LOG_UNKNOWN); 373 } 374 375 /* 376 * Figure out if Ecache is direct-mapped (Cheetah or Cheetah+ with Ecache 377 * control ECCR_ASSOC bit off or 2-way (Cheetah+ with ECCR_ASSOC on). 378 * We need to do this on the fly because we may have mixed Cheetah+'s with 379 * both direct and 2-way Ecaches. 380 */ 381 int 382 cpu_ecache_nway(void) 383 { 384 return (CH_ECACHE_NWAY); 385 } 386 387 /* 388 * Note that these are entered into the table: Fatal Errors (PERR, IERR, 389 * ISAP, EMU) first, orphaned UCU/UCC, AFAR Overwrite policy, finally IVU, IVC. 390 * Afar overwrite policy is: 391 * UCU,UCC > UE,EDU,WDU,CPU > CE,EDC,EMC,WDC,CPC > TO,BERR 392 */ 393 ecc_type_to_info_t ecc_type_to_info[] = { 394 395 /* Fatal Errors */ 396 C_AFSR_PERR, "PERR ", ECC_ALL_TRAPS, CPU_FATAL, 397 "PERR Fatal", 398 FM_EREPORT_PAYLOAD_SYSTEM2, 399 FM_EREPORT_CPU_USIII_PERR, 400 C_AFSR_IERR, "IERR ", ECC_ALL_TRAPS, CPU_FATAL, 401 "IERR Fatal", 402 FM_EREPORT_PAYLOAD_SYSTEM2, 403 FM_EREPORT_CPU_USIII_IERR, 404 C_AFSR_ISAP, "ISAP ", ECC_ALL_TRAPS, CPU_FATAL, 405 "ISAP Fatal", 406 FM_EREPORT_PAYLOAD_SYSTEM1, 407 FM_EREPORT_CPU_USIII_ISAP, 408 C_AFSR_EMU, "EMU ", ECC_ASYNC_TRAPS, CPU_FATAL, 409 "EMU Fatal", 410 FM_EREPORT_PAYLOAD_MEMORY, 411 FM_EREPORT_CPU_USIII_EMU, 412 413 /* Orphaned UCC/UCU Errors */ 414 C_AFSR_UCU, "OUCU ", ECC_ORPH_TRAPS, CPU_ORPH, 415 "Orphaned UCU", 416 FM_EREPORT_PAYLOAD_L2_DATA, 417 FM_EREPORT_CPU_USIII_UCU, 418 C_AFSR_UCC, "OUCC ", ECC_ORPH_TRAPS, CPU_ORPH, 419 "Orphaned UCC", 420 FM_EREPORT_PAYLOAD_L2_DATA, 421 FM_EREPORT_CPU_USIII_UCC, 422 423 /* UCU, UCC */ 424 C_AFSR_UCU, "UCU ", ECC_F_TRAP, CPU_UE_ECACHE, 425 "UCU", 426 FM_EREPORT_PAYLOAD_L2_DATA, 427 FM_EREPORT_CPU_USIII_UCU, 428 C_AFSR_UCC, "UCC ", ECC_F_TRAP, CPU_CE_ECACHE, 429 "UCC", 430 FM_EREPORT_PAYLOAD_L2_DATA, 431 FM_EREPORT_CPU_USIII_UCC, 432 433 /* UE, EDU:ST, EDU:BLD, WDU, CPU */ 434 C_AFSR_UE, "UE ", ECC_ASYNC_TRAPS, CPU_UE, 435 "Uncorrectable system bus (UE)", 436 FM_EREPORT_PAYLOAD_MEMORY, 437 FM_EREPORT_CPU_USIII_UE, 438 C_AFSR_EDU, "EDU ", ECC_C_TRAP, CPU_UE_ECACHE_RETIRE, 439 "EDU:ST", 440 FM_EREPORT_PAYLOAD_L2_DATA, 441 FM_EREPORT_CPU_USIII_EDUST, 442 C_AFSR_EDU, "EDU ", ECC_D_TRAP, CPU_UE_ECACHE_RETIRE, 443 "EDU:BLD", 444 FM_EREPORT_PAYLOAD_L2_DATA, 445 FM_EREPORT_CPU_USIII_EDUBL, 446 C_AFSR_WDU, "WDU ", ECC_C_TRAP, CPU_UE_ECACHE_RETIRE, 447 "WDU", 448 FM_EREPORT_PAYLOAD_L2_DATA, 449 FM_EREPORT_CPU_USIII_WDU, 450 C_AFSR_CPU, "CPU ", ECC_C_TRAP, CPU_UE_ECACHE, 451 "CPU", 452 FM_EREPORT_PAYLOAD_L2_DATA, 453 FM_EREPORT_CPU_USIII_CPU, 454 455 /* CE, EDC, EMC, WDC, CPC */ 456 C_AFSR_CE, "CE ", ECC_C_TRAP, CPU_CE, 457 "Corrected system bus (CE)", 458 FM_EREPORT_PAYLOAD_MEMORY, 459 FM_EREPORT_CPU_USIII_CE, 460 C_AFSR_EDC, "EDC ", ECC_C_TRAP, CPU_CE_ECACHE, 461 "EDC", 462 FM_EREPORT_PAYLOAD_L2_DATA, 463 FM_EREPORT_CPU_USIII_EDC, 464 C_AFSR_EMC, "EMC ", ECC_C_TRAP, CPU_EMC, 465 "EMC", 466 FM_EREPORT_PAYLOAD_MEMORY, 467 FM_EREPORT_CPU_USIII_EMC, 468 C_AFSR_WDC, "WDC ", ECC_C_TRAP, CPU_CE_ECACHE, 469 "WDC", 470 FM_EREPORT_PAYLOAD_L2_DATA, 471 FM_EREPORT_CPU_USIII_WDC, 472 C_AFSR_CPC, "CPC ", ECC_C_TRAP, CPU_CE_ECACHE, 473 "CPC", 474 FM_EREPORT_PAYLOAD_L2_DATA, 475 FM_EREPORT_CPU_USIII_CPC, 476 477 /* TO, BERR */ 478 C_AFSR_TO, "TO ", ECC_ASYNC_TRAPS, CPU_TO, 479 "Timeout (TO)", 480 FM_EREPORT_PAYLOAD_IO, 481 FM_EREPORT_CPU_USIII_TO, 482 C_AFSR_BERR, "BERR ", ECC_ASYNC_TRAPS, CPU_BERR, 483 "Bus Error (BERR)", 484 FM_EREPORT_PAYLOAD_IO, 485 FM_EREPORT_CPU_USIII_BERR, 486 487 /* IVU, IVC */ 488 C_AFSR_IVU, "IVU ", ECC_C_TRAP, CPU_IV, 489 "IVU", 490 FM_EREPORT_PAYLOAD_SYSTEM1, 491 FM_EREPORT_CPU_USIII_IVU, 492 C_AFSR_IVC, "IVC ", ECC_C_TRAP, CPU_IV, 493 "IVC", 494 FM_EREPORT_PAYLOAD_SYSTEM1, 495 FM_EREPORT_CPU_USIII_IVC, 496 497 0, NULL, 0, 0, 498 NULL, 499 FM_EREPORT_PAYLOAD_UNKNOWN, 500 FM_EREPORT_CPU_USIII_UNKNOWN, 501 }; 502 503 /* 504 * Prioritized list of Error bits for AFAR overwrite. 505 * See Cheetah PRM P.6.1 506 * Class 4: UCC, UCU 507 * Class 3: UE, EDU, EMU, WDU, CPU 508 * Class 2: CE, EDC, EMC, WDC, CPC 509 * Class 1: TO, BERR 510 */ 511 uint64_t afar_overwrite[] = { 512 C_AFSR_UCC | C_AFSR_UCU, 513 C_AFSR_UE | C_AFSR_EDU | C_AFSR_EMU | C_AFSR_WDU | C_AFSR_CPU, 514 C_AFSR_CE | C_AFSR_EDC | C_AFSR_EMC | C_AFSR_WDC | C_AFSR_CPC, 515 C_AFSR_TO | C_AFSR_BERR, 516 0 517 }; 518 519 /* 520 * Prioritized list of Error bits for ESYND overwrite. 521 * See Cheetah PRM P.6.2 522 * Class 2: UE, IVU, EDU, WDU, UCU, CPU 523 * Class 1: CE, IVC, EDC, WDC, UCC, CPC 524 */ 525 uint64_t esynd_overwrite[] = { 526 C_AFSR_UE | C_AFSR_IVU | C_AFSR_EDU | C_AFSR_WDU | C_AFSR_UCU | 527 C_AFSR_CPU, 528 C_AFSR_CE | C_AFSR_IVC | C_AFSR_EDC | C_AFSR_WDC | C_AFSR_UCC | 529 C_AFSR_CPC, 530 0 531 }; 532 533 /* 534 * Prioritized list of Error bits for MSYND overwrite. 535 * See Cheetah PRM P.6.3 536 * Class 2: EMU 537 * Class 1: EMC 538 */ 539 uint64_t msynd_overwrite[] = { 540 C_AFSR_EMU, 541 C_AFSR_EMC, 542 0 543 }; 544 545 /* 546 * change cpu speed bits -- new speed will be normal-speed/divisor. 547 * 548 * The Jalapeno memory controllers are required to drain outstanding 549 * memory transactions within 32 JBus clocks in order to be ready 550 * to enter Estar mode. In some corner cases however, that time 551 * fell short. 552 * 553 * A safe software solution is to force MCU to act like in Estar mode, 554 * then delay 1us (in ppm code) prior to assert J_CHNG_L signal. 555 * To reverse the effect, upon exiting Estar, software restores the 556 * MCU to its original state. 557 */ 558 /* ARGSUSED1 */ 559 void 560 cpu_change_speed(uint64_t divisor, uint64_t arg2) 561 { 562 bus_config_eclk_t *bceclk; 563 uint64_t reg; 564 565 for (bceclk = bus_config_eclk; bceclk->divisor; bceclk++) { 566 if (bceclk->divisor != divisor) 567 continue; 568 reg = get_safari_config(); 569 reg &= ~SAFARI_CONFIG_ECLK_MASK; 570 reg |= bceclk->mask; 571 set_safari_config(reg); 572 CPU->cpu_m.divisor = (uchar_t)divisor; 573 return; 574 } 575 /* 576 * We will reach here only if OBP and kernel don't agree on 577 * the speeds supported by the CPU. 578 */ 579 cmn_err(CE_WARN, "cpu_change_speed: bad divisor %" PRIu64, divisor); 580 } 581 582 /* 583 * Cpu private initialization. This includes allocating the cpu_private 584 * data structure, initializing it, and initializing the scrubber for this 585 * cpu. This function calls cpu_init_ecache_scrub_dr to init the scrubber. 586 * We use kmem_cache_create for the cheetah private data structure because 587 * it needs to be allocated on a PAGESIZE (8192) byte boundary. 588 */ 589 void 590 cpu_init_private(struct cpu *cp) 591 { 592 cheetah_private_t *chprp; 593 int i; 594 595 ASSERT(CPU_PRIVATE(cp) == NULL); 596 597 /* LINTED: E_TRUE_LOGICAL_EXPR */ 598 ASSERT((offsetof(cheetah_private_t, chpr_tl1_err_data) + 599 sizeof (ch_err_tl1_data_t) * CH_ERR_TL1_TLMAX) <= PAGESIZE); 600 601 /* 602 * Running with a Cheetah+, Jaguar, or Panther on a Cheetah CPU 603 * machine is not a supported configuration. Attempting to do so 604 * may result in unpredictable failures (e.g. running Cheetah+ 605 * CPUs with Cheetah E$ disp flush) so don't allow it. 606 * 607 * This is just defensive code since this configuration mismatch 608 * should have been caught prior to OS execution. 609 */ 610 if (!IS_CHEETAH(cpunodes[cp->cpu_id].implementation)) { 611 cmn_err(CE_PANIC, "CPU%d: UltraSPARC-III+/IV/IV+ not" 612 " supported on UltraSPARC-III code\n", cp->cpu_id); 613 } 614 615 /* 616 * If the ch_private_cache has not been created, create it. 617 */ 618 if (ch_private_cache == NULL) { 619 ch_private_cache = kmem_cache_create("ch_private_cache", 620 sizeof (cheetah_private_t), PAGESIZE, NULL, NULL, 621 NULL, NULL, static_arena, 0); 622 } 623 624 chprp = CPU_PRIVATE(cp) = kmem_cache_alloc(ch_private_cache, KM_SLEEP); 625 626 bzero(chprp, sizeof (cheetah_private_t)); 627 chprp->chpr_fecctl0_logout.clo_data.chd_afar = LOGOUT_INVALID; 628 chprp->chpr_cecc_logout.clo_data.chd_afar = LOGOUT_INVALID; 629 chprp->chpr_async_logout.clo_data.chd_afar = LOGOUT_INVALID; 630 for (i = 0; i < CH_ERR_TL1_TLMAX; i++) 631 chprp->chpr_tl1_err_data[i].ch_err_tl1_logout.clo_data.chd_afar 632 = LOGOUT_INVALID; 633 634 chprp->chpr_icache_size = CH_ICACHE_SIZE; 635 chprp->chpr_icache_linesize = CH_ICACHE_LSIZE; 636 637 cpu_init_ecache_scrub_dr(cp); 638 639 chprp->chpr_ec_set_size = cpunodes[cp->cpu_id].ecache_size / 640 cpu_ecache_nway(); 641 642 adjust_hw_copy_limits(cpunodes[cp->cpu_id].ecache_size); 643 ch_err_tl1_paddrs[cp->cpu_id] = va_to_pa(chprp); 644 ASSERT(ch_err_tl1_paddrs[cp->cpu_id] != -1); 645 } 646 647 /* 648 * Clear the error state registers for this CPU. 649 * For Cheetah, just clear the AFSR 650 */ 651 void 652 set_cpu_error_state(ch_cpu_errors_t *cpu_error_regs) 653 { 654 set_asyncflt(cpu_error_regs->afsr & ~C_AFSR_FATAL_ERRS); 655 } 656 657 /* 658 * For Cheetah, the error recovery code uses an alternate flush area in the 659 * TL>0 fast ECC handler. ecache_tl1_flushaddr is the physical address of 660 * this exclusive displacement flush area. 661 */ 662 uint64_t ecache_tl1_flushaddr = (uint64_t)-1; /* physaddr for E$ flushing */ 663 664 /* 665 * Allocate and initialize the exclusive displacement flush area. 666 * Must be called before startup_bop_gone(). 667 */ 668 caddr_t 669 ecache_init_scrub_flush_area(caddr_t alloc_base) 670 { 671 unsigned size = 2 * CH_ECACHE_8M_SIZE; 672 caddr_t tmp_alloc_base = alloc_base; 673 caddr_t flush_alloc_base = 674 (caddr_t)roundup((uintptr_t)alloc_base, size); 675 caddr_t ecache_tl1_virtaddr; 676 677 /* 678 * Allocate the physical memory for the exclusive flush area 679 * 680 * Need to allocate an exclusive flush area that is twice the 681 * largest supported E$ size, physically contiguous, and 682 * aligned on twice the largest E$ size boundary. 683 * 684 * Memory allocated via BOP_ALLOC is included in the "cage" 685 * from the DR perspective and due to this, its physical 686 * address will never change and the memory will not be 687 * removed. 688 * 689 * BOP_ALLOC takes 4 arguments: bootops, virtual address hint, 690 * size of the area to allocate, and alignment of the area to 691 * allocate. It returns zero if the allocation fails, or the 692 * virtual address for a successful allocation. Memory BOP_ALLOC'd 693 * is physically contiguous. 694 */ 695 if ((ecache_tl1_virtaddr = (caddr_t)BOP_ALLOC(bootops, 696 flush_alloc_base, size, size)) != NULL) { 697 698 tmp_alloc_base = 699 (caddr_t)roundup((uintptr_t)(ecache_tl1_virtaddr + size), 700 ecache_alignsize); 701 702 /* 703 * get the physical address of the exclusive flush area 704 */ 705 ecache_tl1_flushaddr = va_to_pa(ecache_tl1_virtaddr); 706 707 } else { 708 ecache_tl1_virtaddr = (caddr_t)-1; 709 cmn_err(CE_NOTE, "!ecache_init_scrub_flush_area failed\n"); 710 } 711 712 return (tmp_alloc_base); 713 } 714 715 /* 716 * Update cpu_offline_set so the scrubber knows which cpus are offline 717 */ 718 /*ARGSUSED*/ 719 int 720 cpu_scrub_cpu_setup(cpu_setup_t what, int cpuid, void *arg) 721 { 722 switch (what) { 723 case CPU_ON: 724 case CPU_INIT: 725 CPUSET_DEL(cpu_offline_set, cpuid); 726 break; 727 case CPU_OFF: 728 CPUSET_ADD(cpu_offline_set, cpuid); 729 break; 730 default: 731 break; 732 } 733 return (0); 734 } 735