1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/types.h> 29 #include <sys/systm.h> 30 #include <sys/ddi.h> 31 #include <sys/sysmacros.h> 32 #include <sys/archsystm.h> 33 #include <sys/vmsystm.h> 34 #include <sys/machparam.h> 35 #include <sys/machsystm.h> 36 #include <sys/machthread.h> 37 #include <sys/cpu.h> 38 #include <sys/cmp.h> 39 #include <sys/elf_SPARC.h> 40 #include <vm/vm_dep.h> 41 #include <vm/hat_sfmmu.h> 42 #include <vm/seg_kpm.h> 43 #include <sys/cpuvar.h> 44 #include <sys/opl_olympus_regs.h> 45 #include <sys/opl_module.h> 46 #include <sys/async.h> 47 #include <sys/cmn_err.h> 48 #include <sys/debug.h> 49 #include <sys/dditypes.h> 50 #include <sys/cpu_module.h> 51 #include <sys/sysmacros.h> 52 #include <sys/intreg.h> 53 #include <sys/clock.h> 54 #include <sys/platform_module.h> 55 #include <sys/ontrap.h> 56 #include <sys/panic.h> 57 #include <sys/memlist.h> 58 #include <sys/ndifm.h> 59 #include <sys/ddifm.h> 60 #include <sys/fm/protocol.h> 61 #include <sys/fm/util.h> 62 #include <sys/fm/cpu/SPARC64-VI.h> 63 #include <sys/dtrace.h> 64 #include <sys/watchpoint.h> 65 #include <sys/promif.h> 66 67 /* 68 * Internal functions. 69 */ 70 static int cpu_sync_log_err(void *flt); 71 static void cpu_payload_add_aflt(struct async_flt *, nvlist_t *, nvlist_t *); 72 static void opl_cpu_sync_error(struct regs *, ulong_t, ulong_t, uint_t, uint_t); 73 static int cpu_flt_in_memory(opl_async_flt_t *, uint64_t); 74 75 /* 76 * Error counters resetting interval. 77 */ 78 static int opl_async_check_interval = 60; /* 1 min */ 79 80 /* 81 * Maximum number of contexts for Olympus-C. 82 */ 83 #define MAX_NCTXS (1 << 13) 84 85 /* Will be set !NULL for SPARC64-VI and derivatives. */ 86 static uchar_t ctx_pgsz_arr[MAX_NCTXS]; 87 uchar_t *ctx_pgsz_array = ctx_pgsz_arr; 88 89 /* 90 * PA[22:0] represent Displacement in Jupiter 91 * configuration space. 92 */ 93 uint_t root_phys_addr_lo_mask = 0x7fffffu; 94 95 /* 96 * set in /etc/system to control logging of user BERR/TO's 97 */ 98 int cpu_berr_to_verbose = 0; 99 100 static int min_ecache_size; 101 static uint_t priv_hcl_1; 102 static uint_t priv_hcl_2; 103 static uint_t priv_hcl_4; 104 static uint_t priv_hcl_8; 105 106 /* 107 * Olympus error log 108 */ 109 static opl_errlog_t *opl_err_log; 110 111 /* 112 * UE is classified into four classes (MEM, CHANNEL, CPU, PATH). 113 * No any other ecc_type_info insertion is allowed in between the following 114 * four UE classess. 115 */ 116 ecc_type_to_info_t ecc_type_to_info[] = { 117 SFSR_UE, "UE ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_UE, 118 "Uncorrectable ECC", FM_EREPORT_PAYLOAD_SYNC, 119 FM_EREPORT_CPU_UE_MEM, 120 SFSR_UE, "UE ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_UE, 121 "Uncorrectable ECC", FM_EREPORT_PAYLOAD_SYNC, 122 FM_EREPORT_CPU_UE_CHANNEL, 123 SFSR_UE, "UE ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_UE, 124 "Uncorrectable ECC", FM_EREPORT_PAYLOAD_SYNC, 125 FM_EREPORT_CPU_UE_CPU, 126 SFSR_UE, "UE ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_UE, 127 "Uncorrectable ECC", FM_EREPORT_PAYLOAD_SYNC, 128 FM_EREPORT_CPU_UE_PATH, 129 SFSR_BERR, "BERR ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_OTHERS, 130 "Bus Error", FM_EREPORT_PAYLOAD_SYNC, 131 FM_EREPORT_CPU_BERR, 132 SFSR_TO, "TO ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_OTHERS, 133 "Bus Timeout", FM_EREPORT_PAYLOAD_SYNC, 134 FM_EREPORT_CPU_BTO, 135 SFSR_TLB_MUL, "TLB_MUL ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_OTHERS, 136 "TLB MultiHit", FM_EREPORT_PAYLOAD_SYNC, 137 FM_EREPORT_CPU_MTLB, 138 SFSR_TLB_PRT, "TLB_PRT ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_OTHERS, 139 "TLB Parity", FM_EREPORT_PAYLOAD_SYNC, 140 FM_EREPORT_CPU_TLBP, 141 142 UGESR_IAUG_CRE, "IAUG_CRE", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 143 "IAUG CRE", FM_EREPORT_PAYLOAD_URGENT, 144 FM_EREPORT_CPU_CRE, 145 UGESR_IAUG_TSBCTXT, "IAUG_TSBCTXT", 146 OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 147 "IAUG TSBCTXT", FM_EREPORT_PAYLOAD_URGENT, 148 FM_EREPORT_CPU_TSBCTX, 149 UGESR_IUG_TSBP, "IUG_TSBP", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 150 "IUG TSBP", FM_EREPORT_PAYLOAD_URGENT, 151 FM_EREPORT_CPU_TSBP, 152 UGESR_IUG_PSTATE, "IUG_PSTATE", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 153 "IUG PSTATE", FM_EREPORT_PAYLOAD_URGENT, 154 FM_EREPORT_CPU_PSTATE, 155 UGESR_IUG_TSTATE, "IUG_TSTATE", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 156 "IUG TSTATE", FM_EREPORT_PAYLOAD_URGENT, 157 FM_EREPORT_CPU_TSTATE, 158 UGESR_IUG_F, "IUG_F", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 159 "IUG FREG", FM_EREPORT_PAYLOAD_URGENT, 160 FM_EREPORT_CPU_IUG_F, 161 UGESR_IUG_R, "IUG_R", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 162 "IUG RREG", FM_EREPORT_PAYLOAD_URGENT, 163 FM_EREPORT_CPU_IUG_R, 164 UGESR_AUG_SDC, "AUG_SDC", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 165 "AUG SDC", FM_EREPORT_PAYLOAD_URGENT, 166 FM_EREPORT_CPU_SDC, 167 UGESR_IUG_WDT, "IUG_WDT", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 168 "IUG WDT", FM_EREPORT_PAYLOAD_URGENT, 169 FM_EREPORT_CPU_WDT, 170 UGESR_IUG_DTLB, "IUG_DTLB", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 171 "IUG DTLB", FM_EREPORT_PAYLOAD_URGENT, 172 FM_EREPORT_CPU_DTLB, 173 UGESR_IUG_ITLB, "IUG_ITLB", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 174 "IUG ITLB", FM_EREPORT_PAYLOAD_URGENT, 175 FM_EREPORT_CPU_ITLB, 176 UGESR_IUG_COREERR, "IUG_COREERR", 177 OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 178 "IUG COREERR", FM_EREPORT_PAYLOAD_URGENT, 179 FM_EREPORT_CPU_CORE, 180 UGESR_MULTI_DAE, "MULTI_DAE", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 181 "MULTI DAE", FM_EREPORT_PAYLOAD_URGENT, 182 FM_EREPORT_CPU_DAE, 183 UGESR_MULTI_IAE, "MULTI_IAE", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 184 "MULTI IAE", FM_EREPORT_PAYLOAD_URGENT, 185 FM_EREPORT_CPU_IAE, 186 UGESR_MULTI_UGE, "MULTI_UGE", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 187 "MULTI UGE", FM_EREPORT_PAYLOAD_URGENT, 188 FM_EREPORT_CPU_UGE, 189 0, NULL, 0, 0, 190 NULL, 0, 0, 191 }; 192 193 int (*p2get_mem_info)(int synd_code, uint64_t paddr, 194 uint64_t *mem_sizep, uint64_t *seg_sizep, uint64_t *bank_sizep, 195 int *segsp, int *banksp, int *mcidp); 196 197 198 /* 199 * Setup trap handlers for 0xA, 0x32, 0x40 trap types. 200 */ 201 void 202 cpu_init_trap(void) 203 { 204 OPL_SET_TRAP(tt0_iae, opl_serr_instr); 205 OPL_SET_TRAP(tt1_iae, opl_serr_instr); 206 OPL_SET_TRAP(tt0_dae, opl_serr_instr); 207 OPL_SET_TRAP(tt1_dae, opl_serr_instr); 208 OPL_SET_TRAP(tt0_asdat, opl_ugerr_instr); 209 OPL_SET_TRAP(tt1_asdat, opl_ugerr_instr); 210 } 211 212 static int 213 getintprop(pnode_t node, char *name, int deflt) 214 { 215 int value; 216 217 switch (prom_getproplen(node, name)) { 218 case sizeof (int): 219 (void) prom_getprop(node, name, (caddr_t)&value); 220 break; 221 222 default: 223 value = deflt; 224 break; 225 } 226 227 return (value); 228 } 229 230 /* 231 * Set the magic constants of the implementation. 232 */ 233 /*ARGSUSED*/ 234 void 235 cpu_fiximp(pnode_t dnode) 236 { 237 int i, a; 238 extern int vac_size, vac_shift; 239 extern uint_t vac_mask; 240 241 static struct { 242 char *name; 243 int *var; 244 int defval; 245 } prop[] = { 246 "l1-dcache-size", &dcache_size, OPL_DCACHE_SIZE, 247 "l1-dcache-line-size", &dcache_linesize, OPL_DCACHE_LSIZE, 248 "l1-icache-size", &icache_size, OPL_ICACHE_SIZE, 249 "l1-icache-line-size", &icache_linesize, OPL_ICACHE_LSIZE, 250 "l2-cache-size", &ecache_size, OPL_ECACHE_SIZE, 251 "l2-cache-line-size", &ecache_alignsize, OPL_ECACHE_LSIZE, 252 "l2-cache-associativity", &ecache_associativity, OPL_ECACHE_NWAY 253 }; 254 255 for (i = 0; i < sizeof (prop) / sizeof (prop[0]); i++) 256 *prop[i].var = getintprop(dnode, prop[i].name, prop[i].defval); 257 258 ecache_setsize = ecache_size / ecache_associativity; 259 260 vac_size = OPL_VAC_SIZE; 261 vac_mask = MMU_PAGEMASK & (vac_size - 1); 262 i = 0; a = vac_size; 263 while (a >>= 1) 264 ++i; 265 vac_shift = i; 266 shm_alignment = vac_size; 267 vac = 1; 268 } 269 270 void 271 send_mondo_set(cpuset_t set) 272 { 273 int lo, busy, nack, shipped = 0; 274 uint16_t i, cpuids[IDSR_BN_SETS]; 275 uint64_t idsr, nackmask = 0, busymask, curnack, curbusy; 276 uint64_t starttick, endtick, tick, lasttick; 277 #if (NCPU > IDSR_BN_SETS) 278 int index = 0; 279 int ncpuids = 0; 280 #endif 281 #ifdef OLYMPUS_ERRATA_XCALL 282 int bn_sets = IDSR_BN_SETS; 283 uint64_t ver; 284 285 ASSERT(NCPU > bn_sets); 286 #endif 287 288 ASSERT(!CPUSET_ISNULL(set)); 289 starttick = lasttick = gettick(); 290 291 #ifdef OLYMPUS_ERRATA_XCALL 292 ver = ultra_getver(); 293 if (((ULTRA_VER_IMPL(ver)) == OLYMPUS_C_IMPL) && 294 ((OLYMPUS_REV_MASK(ver)) == OLYMPUS_C_A)) 295 bn_sets = 1; 296 #endif 297 298 #if (NCPU <= IDSR_BN_SETS) 299 for (i = 0; i < NCPU; i++) 300 if (CPU_IN_SET(set, i)) { 301 shipit(i, shipped); 302 nackmask |= IDSR_NACK_BIT(shipped); 303 cpuids[shipped++] = i; 304 CPUSET_DEL(set, i); 305 if (CPUSET_ISNULL(set)) 306 break; 307 } 308 CPU_STATS_ADDQ(CPU, sys, xcalls, shipped); 309 #else 310 for (i = 0; i < NCPU; i++) 311 if (CPU_IN_SET(set, i)) { 312 ncpuids++; 313 314 /* 315 * Ship only to the first (IDSR_BN_SETS) CPUs. If we 316 * find we have shipped to more than (IDSR_BN_SETS) 317 * CPUs, set "index" to the highest numbered CPU in 318 * the set so we can ship to other CPUs a bit later on. 319 */ 320 #ifdef OLYMPUS_ERRATA_XCALL 321 if (shipped < bn_sets) { 322 #else 323 if (shipped < IDSR_BN_SETS) { 324 #endif 325 shipit(i, shipped); 326 nackmask |= IDSR_NACK_BIT(shipped); 327 cpuids[shipped++] = i; 328 CPUSET_DEL(set, i); 329 if (CPUSET_ISNULL(set)) 330 break; 331 } else 332 index = (int)i; 333 } 334 335 CPU_STATS_ADDQ(CPU, sys, xcalls, ncpuids); 336 #endif 337 338 busymask = IDSR_NACK_TO_BUSY(nackmask); 339 busy = nack = 0; 340 endtick = starttick + xc_tick_limit; 341 for (;;) { 342 idsr = getidsr(); 343 #if (NCPU <= IDSR_BN_SETS) 344 if (idsr == 0) 345 break; 346 #else 347 if (idsr == 0 && shipped == ncpuids) 348 break; 349 #endif 350 tick = gettick(); 351 /* 352 * If there is a big jump between the current tick 353 * count and lasttick, we have probably hit a break 354 * point. Adjust endtick accordingly to avoid panic. 355 */ 356 if (tick > (lasttick + xc_tick_jump_limit)) 357 endtick += (tick - lasttick); 358 lasttick = tick; 359 if (tick > endtick) { 360 if (panic_quiesce) 361 return; 362 cmn_err(CE_CONT, "send mondo timeout " 363 "[%d NACK %d BUSY]\nIDSR 0x%" 364 "" PRIx64 " cpuids:", nack, busy, idsr); 365 #ifdef OLYMPUS_ERRATA_XCALL 366 for (i = 0; i < bn_sets; i++) { 367 #else 368 for (i = 0; i < IDSR_BN_SETS; i++) { 369 #endif 370 if (idsr & (IDSR_NACK_BIT(i) | 371 IDSR_BUSY_BIT(i))) { 372 cmn_err(CE_CONT, " 0x%x", 373 cpuids[i]); 374 } 375 } 376 cmn_err(CE_CONT, "\n"); 377 cmn_err(CE_PANIC, "send_mondo_set: timeout"); 378 } 379 curnack = idsr & nackmask; 380 curbusy = idsr & busymask; 381 #if (NCPU > IDSR_BN_SETS) 382 if (shipped < ncpuids) { 383 uint64_t cpus_left; 384 uint16_t next = (uint16_t)index; 385 386 cpus_left = ~(IDSR_NACK_TO_BUSY(curnack) | curbusy) & 387 busymask; 388 389 if (cpus_left) { 390 do { 391 /* 392 * Sequence through and ship to the 393 * remainder of the CPUs in the system 394 * (e.g. other than the first 395 * (IDSR_BN_SETS)) in reverse order. 396 */ 397 lo = lowbit(cpus_left) - 1; 398 i = IDSR_BUSY_IDX(lo); 399 shipit(next, i); 400 shipped++; 401 cpuids[i] = next; 402 403 /* 404 * If we've processed all the CPUs, 405 * exit the loop now and save 406 * instructions. 407 */ 408 if (shipped == ncpuids) 409 break; 410 411 for ((index = ((int)next - 1)); 412 index >= 0; index--) 413 if (CPU_IN_SET(set, index)) { 414 next = (uint16_t)index; 415 break; 416 } 417 418 cpus_left &= ~(1ull << lo); 419 } while (cpus_left); 420 continue; 421 } 422 } 423 #endif 424 if (curbusy) { 425 busy++; 426 continue; 427 } 428 429 #ifdef SEND_MONDO_STATS 430 { 431 int n = gettick() - starttick; 432 if (n < 8192) 433 x_nack_stimes[n >> 7]++; 434 } 435 #endif 436 while (gettick() < (tick + sys_clock_mhz)) 437 ; 438 do { 439 lo = lowbit(curnack) - 1; 440 i = IDSR_NACK_IDX(lo); 441 shipit(cpuids[i], i); 442 curnack &= ~(1ull << lo); 443 } while (curnack); 444 nack++; 445 busy = 0; 446 } 447 #ifdef SEND_MONDO_STATS 448 { 449 int n = gettick() - starttick; 450 if (n < 8192) 451 x_set_stimes[n >> 7]++; 452 else 453 x_set_ltimes[(n >> 13) & 0xf]++; 454 } 455 x_set_cpus[shipped]++; 456 #endif 457 } 458 459 /* 460 * Cpu private initialization. 461 */ 462 void 463 cpu_init_private(struct cpu *cp) 464 { 465 if (!(IS_OLYMPUS_C(cpunodes[cp->cpu_id].implementation))) { 466 cmn_err(CE_PANIC, "CPU%d Impl %d: Only SPARC64-VI is supported", 467 cp->cpu_id, cpunodes[cp->cpu_id].implementation); 468 } 469 470 adjust_hw_copy_limits(cpunodes[cp->cpu_id].ecache_size); 471 } 472 473 void 474 cpu_setup(void) 475 { 476 extern int at_flags; 477 extern int disable_delay_tlb_flush, delay_tlb_flush; 478 extern int cpc_has_overflow_intr; 479 extern int disable_text_largepages; 480 extern int use_text_pgsz4m; 481 uint64_t cpu0_log; 482 extern uint64_t opl_cpu0_err_log; 483 484 /* 485 * Initialize Error log Scratch register for error handling. 486 */ 487 488 cpu0_log = va_to_pa(&opl_cpu0_err_log); 489 opl_error_setup(cpu0_log); 490 491 /* 492 * Enable MMU translating multiple page sizes for 493 * sITLB and sDTLB. 494 */ 495 opl_mpg_enable(); 496 497 /* 498 * Setup chip-specific trap handlers. 499 */ 500 cpu_init_trap(); 501 502 cache |= (CACHE_VAC | CACHE_PTAG | CACHE_IOCOHERENT); 503 504 at_flags = EF_SPARC_32PLUS | EF_SPARC_SUN_US1 | EF_SPARC_SUN_US3; 505 506 /* 507 * Use the maximum number of contexts available for SPARC64-VI 508 * unless it has been tuned for debugging. 509 * We are checking against 0 here since this value can be patched 510 * while booting. It can not be patched via /etc/system since it 511 * will be patched too late and thus cause the system to panic. 512 */ 513 if (nctxs == 0) 514 nctxs = MAX_NCTXS; 515 516 /* 517 * Due to the number of entries in the fully-associative tlb 518 * this may have to be tuned lower than in spitfire. 519 */ 520 pp_slots = MIN(8, MAXPP_SLOTS); 521 522 /* 523 * Block stores do not invalidate all pages of the d$, pagecopy 524 * et. al. need virtual translations with virtual coloring taken 525 * into consideration. prefetch/ldd will pollute the d$ on the 526 * load side. 527 */ 528 pp_consistent_coloring = PPAGE_STORE_VCOLORING | PPAGE_LOADS_POLLUTE; 529 530 if (use_page_coloring) { 531 do_pg_coloring = 1; 532 if (use_virtual_coloring) 533 do_virtual_coloring = 1; 534 } 535 536 isa_list = 537 "sparcv9+vis2 sparcv9+vis sparcv9 " 538 "sparcv8plus+vis2 sparcv8plus+vis sparcv8plus " 539 "sparcv8 sparcv8-fsmuld sparcv7 sparc"; 540 541 cpu_hwcap_flags = AV_SPARC_VIS | AV_SPARC_VIS2; 542 543 /* 544 * On SPARC64-VI, there's no hole in the virtual address space 545 */ 546 hole_start = hole_end = 0; 547 548 /* 549 * The kpm mapping window. 550 * kpm_size: 551 * The size of a single kpm range. 552 * The overall size will be: kpm_size * vac_colors. 553 * kpm_vbase: 554 * The virtual start address of the kpm range within the kernel 555 * virtual address space. kpm_vbase has to be kpm_size aligned. 556 */ 557 kpm_size = (size_t)(128ull * 1024 * 1024 * 1024 * 1024); /* 128TB */ 558 kpm_size_shift = 47; 559 kpm_vbase = (caddr_t)0x8000000000000000ull; /* 8EB */ 560 kpm_smallpages = 1; 561 562 /* 563 * The traptrace code uses either %tick or %stick for 564 * timestamping. We have %stick so we can use it. 565 */ 566 traptrace_use_stick = 1; 567 568 /* 569 * SPARC64-VI has a performance counter overflow interrupt 570 */ 571 cpc_has_overflow_intr = 1; 572 573 /* 574 * Use SPARC64-VI flush-all support 575 */ 576 if (!disable_delay_tlb_flush) 577 delay_tlb_flush = 1; 578 579 /* 580 * Declare that this architecture/cpu combination does not support 581 * fpRAS. 582 */ 583 fpras_implemented = 0; 584 585 /* 586 * Enable 4M pages to be used for mapping user text by default. Don't 587 * use large pages for initialized data segments since we may not know 588 * at exec() time what should be the preferred large page size for DTLB 589 * programming. 590 */ 591 use_text_pgsz4m = 1; 592 disable_text_largepages = (1 << TTE64K) | (1 << TTE512K) | 593 (1 << TTE32M) | (1 << TTE256M); 594 } 595 596 /* 597 * Called by setcpudelay 598 */ 599 void 600 cpu_init_tick_freq(void) 601 { 602 /* 603 * For SPARC64-VI we want to use the system clock rate as 604 * the basis for low level timing, due to support of mixed 605 * speed CPUs and power managment. 606 */ 607 if (system_clock_freq == 0) 608 cmn_err(CE_PANIC, "setcpudelay: invalid system_clock_freq"); 609 610 sys_tick_freq = system_clock_freq; 611 } 612 613 #ifdef SEND_MONDO_STATS 614 uint32_t x_one_stimes[64]; 615 uint32_t x_one_ltimes[16]; 616 uint32_t x_set_stimes[64]; 617 uint32_t x_set_ltimes[16]; 618 uint32_t x_set_cpus[NCPU]; 619 uint32_t x_nack_stimes[64]; 620 #endif 621 622 /* 623 * Note: A version of this function is used by the debugger via the KDI, 624 * and must be kept in sync with this version. Any changes made to this 625 * function to support new chips or to accomodate errata must also be included 626 * in the KDI-specific version. See us3_kdi.c. 627 */ 628 void 629 send_one_mondo(int cpuid) 630 { 631 int busy, nack; 632 uint64_t idsr, starttick, endtick, tick, lasttick; 633 uint64_t busymask; 634 635 CPU_STATS_ADDQ(CPU, sys, xcalls, 1); 636 starttick = lasttick = gettick(); 637 shipit(cpuid, 0); 638 endtick = starttick + xc_tick_limit; 639 busy = nack = 0; 640 busymask = IDSR_BUSY; 641 for (;;) { 642 idsr = getidsr(); 643 if (idsr == 0) 644 break; 645 646 tick = gettick(); 647 /* 648 * If there is a big jump between the current tick 649 * count and lasttick, we have probably hit a break 650 * point. Adjust endtick accordingly to avoid panic. 651 */ 652 if (tick > (lasttick + xc_tick_jump_limit)) 653 endtick += (tick - lasttick); 654 lasttick = tick; 655 if (tick > endtick) { 656 if (panic_quiesce) 657 return; 658 cmn_err(CE_PANIC, "send mondo timeout " 659 "(target 0x%x) [%d NACK %d BUSY]", 660 cpuid, nack, busy); 661 } 662 663 if (idsr & busymask) { 664 busy++; 665 continue; 666 } 667 drv_usecwait(1); 668 shipit(cpuid, 0); 669 nack++; 670 busy = 0; 671 } 672 #ifdef SEND_MONDO_STATS 673 { 674 int n = gettick() - starttick; 675 if (n < 8192) 676 x_one_stimes[n >> 7]++; 677 else 678 x_one_ltimes[(n >> 13) & 0xf]++; 679 } 680 #endif 681 } 682 683 /* 684 * init_mmu_page_sizes is set to one after the bootup time initialization 685 * via mmu_init_mmu_page_sizes, to indicate that mmu_page_sizes has a 686 * valid value. 687 * 688 * mmu_disable_ism_large_pages and mmu_disable_large_pages are the mmu-specific 689 * versions of disable_ism_large_pages and disable_large_pages, and feed back 690 * into those two hat variables at hat initialization time. 691 * 692 */ 693 int init_mmu_page_sizes = 0; 694 static int mmu_disable_ism_large_pages = ((1 << TTE64K) | 695 (1 << TTE512K) | (1 << TTE256M)); 696 static int mmu_disable_large_pages = 0; 697 698 /* 699 * Re-initialize mmu_page_sizes and friends, for SPARC64-VI mmu support. 700 * Called during very early bootup from check_cpus_set(). 701 * Can be called to verify that mmu_page_sizes are set up correctly. 702 * 703 * Set Olympus defaults. We do not use the function parameter. 704 */ 705 /*ARGSUSED*/ 706 int 707 mmu_init_mmu_page_sizes(int32_t not_used) 708 { 709 if (!init_mmu_page_sizes) { 710 mmu_page_sizes = MMU_PAGE_SIZES; 711 mmu_hashcnt = MAX_HASHCNT; 712 mmu_ism_pagesize = MMU_PAGESIZE32M; 713 mmu_exported_pagesize_mask = (1 << TTE8K) | 714 (1 << TTE64K) | (1 << TTE512K) | (1 << TTE4M) | 715 (1 << TTE32M) | (1 << TTE256M); 716 init_mmu_page_sizes = 1; 717 return (0); 718 } 719 return (1); 720 } 721 722 /* SPARC64-VI worst case DTLB parameters */ 723 #ifndef LOCKED_DTLB_ENTRIES 724 #define LOCKED_DTLB_ENTRIES 5 /* 2 user TSBs, 2 nucleus, + OBP */ 725 #endif 726 #define TOTAL_DTLB_ENTRIES 32 727 #define AVAIL_32M_ENTRIES 0 728 #define AVAIL_256M_ENTRIES 0 729 #define AVAIL_DTLB_ENTRIES (TOTAL_DTLB_ENTRIES - LOCKED_DTLB_ENTRIES) 730 static uint64_t ttecnt_threshold[MMU_PAGE_SIZES] = { 731 AVAIL_DTLB_ENTRIES, AVAIL_DTLB_ENTRIES, 732 AVAIL_DTLB_ENTRIES, AVAIL_DTLB_ENTRIES, 733 AVAIL_DTLB_ENTRIES, AVAIL_DTLB_ENTRIES}; 734 735 size_t 736 mmu_map_pgsz(size_t pgsize) 737 { 738 struct proc *p = curproc; 739 struct as *as = p->p_as; 740 struct hat *hat = as->a_hat; 741 uint_t pgsz0, pgsz1; 742 size_t size0, size1; 743 744 ASSERT(mmu_page_sizes == max_mmu_page_sizes); 745 pgsz0 = hat->sfmmu_pgsz[0]; 746 pgsz1 = hat->sfmmu_pgsz[1]; 747 size0 = hw_page_array[pgsz0].hp_size; 748 size1 = hw_page_array[pgsz1].hp_size; 749 /* Allow use of a larger pagesize if neither TLB is reprogrammed. */ 750 if ((pgsz0 == TTE8K) && (pgsz1 == TTE8K)) { 751 return (pgsize); 752 /* Allow use of requested pagesize if TLB is reprogrammed to it. */ 753 } else if ((pgsize == size0) || (pgsize == size1)) { 754 return (pgsize); 755 /* Use larger reprogrammed TLB size if pgsize is atleast that big. */ 756 } else if (pgsz1 > pgsz0) { 757 if (pgsize >= size1) 758 return (size1); 759 /* Use smaller reprogrammed TLB size if pgsize is atleast that big. */ 760 } else { 761 if (pgsize >= size0) 762 return (size0); 763 } 764 return (pgsize); 765 } 766 767 /* 768 * The function returns the mmu-specific values for the 769 * hat's disable_large_pages and disable_ism_large_pages variables. 770 */ 771 int 772 mmu_large_pages_disabled(uint_t flag) 773 { 774 int pages_disable = 0; 775 776 if (flag == HAT_LOAD) { 777 pages_disable = mmu_disable_large_pages; 778 } else if (flag == HAT_LOAD_SHARE) { 779 pages_disable = mmu_disable_ism_large_pages; 780 } 781 return (pages_disable); 782 } 783 784 /* 785 * mmu_init_large_pages is called with the desired ism_pagesize parameter. 786 * It may be called from set_platform_defaults, if some value other than 32M 787 * is desired. mmu_ism_pagesize is the tunable. If it has a bad value, 788 * then only warn, since it would be bad form to panic due to a user typo. 789 * 790 * The function re-initializes the mmu_disable_ism_large_pages variable. 791 */ 792 void 793 mmu_init_large_pages(size_t ism_pagesize) 794 { 795 switch (ism_pagesize) { 796 case MMU_PAGESIZE4M: 797 mmu_disable_ism_large_pages = ((1 << TTE64K) | 798 (1 << TTE512K) | (1 << TTE32M) | (1 << TTE256M)); 799 break; 800 case MMU_PAGESIZE32M: 801 mmu_disable_ism_large_pages = ((1 << TTE64K) | 802 (1 << TTE512K) | (1 << TTE256M)); 803 break; 804 case MMU_PAGESIZE256M: 805 mmu_disable_ism_large_pages = ((1 << TTE64K) | 806 (1 << TTE512K) | (1 << TTE32M)); 807 break; 808 default: 809 cmn_err(CE_WARN, "Unrecognized mmu_ism_pagesize value 0x%lx", 810 ism_pagesize); 811 break; 812 } 813 } 814 815 /*ARGSUSED*/ 816 uint_t 817 mmu_preferred_pgsz(struct hat *hat, caddr_t addr, size_t len) 818 { 819 sfmmu_t *sfmmup = (sfmmu_t *)hat; 820 uint_t pgsz0, pgsz1; 821 uint_t szc, maxszc = mmu_page_sizes - 1; 822 size_t pgsz; 823 extern int disable_large_pages; 824 825 pgsz0 = (uint_t)sfmmup->sfmmu_pgsz[0]; 826 pgsz1 = (uint_t)sfmmup->sfmmu_pgsz[1]; 827 828 /* 829 * If either of the TLBs are reprogrammed, choose 830 * the largest mapping size as the preferred size, 831 * if it fits the size and alignment constraints. 832 * Else return the largest mapping size that fits, 833 * if neither TLB is reprogrammed. 834 */ 835 if (pgsz0 > TTE8K || pgsz1 > TTE8K) { 836 if (pgsz1 > pgsz0) { /* First try pgsz1 */ 837 pgsz = hw_page_array[pgsz1].hp_size; 838 if ((len >= pgsz) && IS_P2ALIGNED(addr, pgsz)) 839 return (pgsz1); 840 } 841 if (pgsz0 > TTE8K) { /* Then try pgsz0, if !TTE8K */ 842 pgsz = hw_page_array[pgsz0].hp_size; 843 if ((len >= pgsz) && IS_P2ALIGNED(addr, pgsz)) 844 return (pgsz0); 845 } 846 } else { /* Otherwise pick best fit if neither TLB is reprogrammed. */ 847 for (szc = maxszc; szc > TTE8K; szc--) { 848 if (disable_large_pages & (1 << szc)) 849 continue; 850 851 pgsz = hw_page_array[szc].hp_size; 852 if ((len >= pgsz) && IS_P2ALIGNED(addr, pgsz)) 853 return (szc); 854 } 855 } 856 return (TTE8K); 857 } 858 859 /* 860 * Function to reprogram the TLBs when page sizes used 861 * by a process change significantly. 862 */ 863 void 864 mmu_setup_page_sizes(struct hat *hat, uint64_t *ttecnt) 865 { 866 extern int page_szc(size_t); 867 uint8_t pgsz0, pgsz1; 868 869 /* 870 * Don't program 2nd dtlb for kernel and ism hat 871 */ 872 if (hat->sfmmu_ismhat || hat == ksfmmup) 873 return; 874 875 /* 876 * hat->sfmmu_pgsz[] is an array whose elements 877 * contain a sorted order of page sizes. Element 878 * 0 is the most commonly used page size, followed 879 * by element 1, and so on. 880 * 881 * ttecnt[] is an array of per-page-size page counts 882 * mapped into the process. 883 * 884 * If the HAT's choice for page sizes is unsuitable, 885 * we can override it here. The new values written 886 * to the array will be handed back to us later to 887 * do the actual programming of the TLB hardware. 888 * 889 */ 890 pgsz0 = (uint8_t)MIN(hat->sfmmu_pgsz[0], hat->sfmmu_pgsz[1]); 891 pgsz1 = (uint8_t)MAX(hat->sfmmu_pgsz[0], hat->sfmmu_pgsz[1]); 892 893 /* 894 * This implements PAGESIZE programming of the sTLB 895 * if large TTE counts don't exceed the thresholds. 896 */ 897 if (ttecnt[pgsz0] < ttecnt_threshold[pgsz0]) 898 pgsz0 = page_szc(MMU_PAGESIZE); 899 if (ttecnt[pgsz1] < ttecnt_threshold[pgsz1]) 900 pgsz1 = page_szc(MMU_PAGESIZE); 901 hat->sfmmu_pgsz[0] = pgsz0; 902 hat->sfmmu_pgsz[1] = pgsz1; 903 /* otherwise, accept what the HAT chose for us */ 904 } 905 906 /* 907 * The HAT calls this function when an MMU context is allocated so that we 908 * can reprogram the large TLBs appropriately for the new process using 909 * the context. 910 * 911 * The caller must hold the HAT lock. 912 */ 913 void 914 mmu_set_ctx_page_sizes(struct hat *hat) 915 { 916 uint8_t pgsz0, pgsz1; 917 uint8_t new_cext; 918 919 ASSERT(sfmmu_hat_lock_held(hat)); 920 /* 921 * Don't program 2nd dtlb for kernel and ism hat 922 */ 923 if (hat->sfmmu_ismhat || hat == ksfmmup) 924 return; 925 926 /* 927 * If supported, reprogram the TLBs to a larger pagesize. 928 */ 929 pgsz0 = hat->sfmmu_pgsz[0]; 930 pgsz1 = hat->sfmmu_pgsz[1]; 931 ASSERT(pgsz0 < mmu_page_sizes); 932 ASSERT(pgsz1 < mmu_page_sizes); 933 new_cext = TAGACCEXT_MKSZPAIR(pgsz1, pgsz0); 934 if (hat->sfmmu_cext != new_cext) { 935 hat->sfmmu_cext = new_cext; 936 } 937 ctx_pgsz_array[hat->sfmmu_cnum] = hat->sfmmu_cext; 938 /* 939 * sfmmu_setctx_sec() will take care of the 940 * rest of the dirty work for us. 941 */ 942 } 943 944 /* 945 * Return processor specific async error structure 946 * size used. 947 */ 948 int 949 cpu_aflt_size(void) 950 { 951 return (sizeof (opl_async_flt_t)); 952 } 953 954 /* 955 * The cpu_sync_log_err() function is called via the [uc]e_drain() function to 956 * post-process CPU events that are dequeued. As such, it can be invoked 957 * from softint context, from AST processing in the trap() flow, or from the 958 * panic flow. We decode the CPU-specific data, and take appropriate actions. 959 * Historically this entry point was used to log the actual cmn_err(9F) text; 960 * now with FMA it is used to prepare 'flt' to be converted into an ereport. 961 * With FMA this function now also returns a flag which indicates to the 962 * caller whether the ereport should be posted (1) or suppressed (0). 963 */ 964 /*ARGSUSED*/ 965 static int 966 cpu_sync_log_err(void *flt) 967 { 968 opl_async_flt_t *opl_flt = (opl_async_flt_t *)flt; 969 struct async_flt *aflt = (struct async_flt *)flt; 970 971 /* 972 * No extra processing of urgent error events. 973 * Always generate ereports for these events. 974 */ 975 if (aflt->flt_status == OPL_ECC_URGENT_TRAP) 976 return (1); 977 978 /* 979 * Additional processing for synchronous errors. 980 */ 981 switch (opl_flt->flt_type) { 982 case OPL_CPU_INV_SFSR: 983 return (1); 984 985 case OPL_CPU_SYNC_UE: 986 /* 987 * The validity: SFSR_MK_UE bit has been checked 988 * in opl_cpu_sync_error() 989 * No more check is required. 990 * 991 * opl_flt->flt_eid_mod and flt_eid_sid have been set by H/W, 992 * and they have been retrieved in cpu_queue_events() 993 */ 994 995 if (opl_flt->flt_eid_mod == OPL_ERRID_MEM) { 996 ASSERT(aflt->flt_in_memory); 997 /* 998 * We want to skip logging only if ALL the following 999 * conditions are true: 1000 * 1001 * 1. We are not panicing already. 1002 * 2. The error is a memory error. 1003 * 3. There is only one error. 1004 * 4. The error is on a retired page. 1005 * 5. The error occurred under on_trap 1006 * protection AFLT_PROT_EC 1007 */ 1008 if (!panicstr && aflt->flt_prot == AFLT_PROT_EC && 1009 page_retire_check(aflt->flt_addr, NULL) == 0) { 1010 /* 1011 * Do not log an error from 1012 * the retired page 1013 */ 1014 softcall(ecc_page_zero, (void *)aflt->flt_addr); 1015 return (0); 1016 } 1017 if (!panicstr) 1018 cpu_page_retire(opl_flt); 1019 } 1020 return (1); 1021 1022 case OPL_CPU_SYNC_OTHERS: 1023 /* 1024 * For the following error cases, the processor HW does 1025 * not set the flt_eid_mod/flt_eid_sid. Instead, SW will attempt 1026 * to assign appropriate values here to reflect what we 1027 * think is the most likely cause of the problem w.r.t to 1028 * the particular error event. For Buserr and timeout 1029 * error event, we will assign OPL_ERRID_CHANNEL as the 1030 * most likely reason. For TLB parity or multiple hit 1031 * error events, we will assign the reason as 1032 * OPL_ERRID_CPU (cpu related problem) and set the 1033 * flt_eid_sid to point to the cpuid. 1034 */ 1035 1036 if (opl_flt->flt_bit & (SFSR_BERR|SFSR_TO)) { 1037 /* 1038 * flt_eid_sid will not be used for this case. 1039 */ 1040 opl_flt->flt_eid_mod = OPL_ERRID_CHANNEL; 1041 } 1042 if (opl_flt->flt_bit & (SFSR_TLB_MUL|SFSR_TLB_PRT)) { 1043 opl_flt->flt_eid_mod = OPL_ERRID_CPU; 1044 opl_flt->flt_eid_sid = aflt->flt_inst; 1045 } 1046 1047 /* 1048 * In case of no effective error bit 1049 */ 1050 if ((opl_flt->flt_bit & SFSR_ERRS) == 0) { 1051 opl_flt->flt_eid_mod = OPL_ERRID_CPU; 1052 opl_flt->flt_eid_sid = aflt->flt_inst; 1053 } 1054 break; 1055 1056 default: 1057 return (1); 1058 } 1059 return (1); 1060 } 1061 1062 /* 1063 * Retire the bad page that may contain the flushed error. 1064 */ 1065 void 1066 cpu_page_retire(opl_async_flt_t *opl_flt) 1067 { 1068 struct async_flt *aflt = (struct async_flt *)opl_flt; 1069 (void) page_retire(aflt->flt_addr, PR_UE); 1070 } 1071 1072 /* 1073 * Invoked by error_init() early in startup and therefore before 1074 * startup_errorq() is called to drain any error Q - 1075 * 1076 * startup() 1077 * startup_end() 1078 * error_init() 1079 * cpu_error_init() 1080 * errorq_init() 1081 * errorq_drain() 1082 * start_other_cpus() 1083 * 1084 * The purpose of this routine is to create error-related taskqs. Taskqs 1085 * are used for this purpose because cpu_lock can't be grabbed from interrupt 1086 * context. 1087 * 1088 */ 1089 /*ARGSUSED*/ 1090 void 1091 cpu_error_init(int items) 1092 { 1093 opl_err_log = (opl_errlog_t *) 1094 kmem_alloc(ERRLOG_ALLOC_SZ, KM_SLEEP); 1095 if ((uint64_t)opl_err_log & MMU_PAGEOFFSET) 1096 cmn_err(CE_PANIC, "The base address of the error log " 1097 "is not page aligned"); 1098 } 1099 1100 /* 1101 * We route all errors through a single switch statement. 1102 */ 1103 void 1104 cpu_ue_log_err(struct async_flt *aflt) 1105 { 1106 switch (aflt->flt_class) { 1107 case CPU_FAULT: 1108 if (cpu_sync_log_err(aflt)) 1109 cpu_ereport_post(aflt); 1110 break; 1111 1112 case BUS_FAULT: 1113 bus_async_log_err(aflt); 1114 break; 1115 1116 default: 1117 cmn_err(CE_WARN, "discarding async error %p with invalid " 1118 "fault class (0x%x)", (void *)aflt, aflt->flt_class); 1119 return; 1120 } 1121 } 1122 1123 /* 1124 * Routine for panic hook callback from panic_idle(). 1125 * 1126 * Nothing to do here. 1127 */ 1128 void 1129 cpu_async_panic_callb(void) 1130 { 1131 } 1132 1133 /* 1134 * Routine to return a string identifying the physical name 1135 * associated with a memory/cache error. 1136 */ 1137 /*ARGSUSED*/ 1138 int 1139 cpu_get_mem_unum(int synd_status, ushort_t flt_synd, uint64_t flt_stat, 1140 uint64_t flt_addr, int flt_bus_id, int flt_in_memory, 1141 ushort_t flt_status, char *buf, int buflen, int *lenp) 1142 { 1143 int synd_code; 1144 int ret; 1145 1146 /* 1147 * An AFSR of -1 defaults to a memory syndrome. 1148 */ 1149 synd_code = (int)flt_synd; 1150 1151 if (&plat_get_mem_unum) { 1152 if ((ret = plat_get_mem_unum(synd_code, flt_addr, flt_bus_id, 1153 flt_in_memory, flt_status, buf, buflen, lenp)) != 0) { 1154 buf[0] = '\0'; 1155 *lenp = 0; 1156 } 1157 return (ret); 1158 } 1159 buf[0] = '\0'; 1160 *lenp = 0; 1161 return (ENOTSUP); 1162 } 1163 1164 /* 1165 * Wrapper for cpu_get_mem_unum() routine that takes an 1166 * async_flt struct rather than explicit arguments. 1167 */ 1168 int 1169 cpu_get_mem_unum_aflt(int synd_status, struct async_flt *aflt, 1170 char *buf, int buflen, int *lenp) 1171 { 1172 /* 1173 * We always pass -1 so that cpu_get_mem_unum will interpret this as a 1174 * memory error. 1175 */ 1176 return (cpu_get_mem_unum(synd_status, aflt->flt_synd, 1177 (uint64_t)-1, 1178 aflt->flt_addr, aflt->flt_bus_id, aflt->flt_in_memory, 1179 aflt->flt_status, buf, buflen, lenp)); 1180 } 1181 1182 /* 1183 * This routine is a more generic interface to cpu_get_mem_unum() 1184 * that may be used by other modules (e.g. mm). 1185 */ 1186 /*ARGSUSED*/ 1187 int 1188 cpu_get_mem_name(uint64_t synd, uint64_t *afsr, uint64_t afar, 1189 char *buf, int buflen, int *lenp) 1190 { 1191 int synd_status, flt_in_memory, ret; 1192 ushort_t flt_status = 0; 1193 char unum[UNUM_NAMLEN]; 1194 1195 /* 1196 * Check for an invalid address. 1197 */ 1198 if (afar == (uint64_t)-1) 1199 return (ENXIO); 1200 1201 if (synd == (uint64_t)-1) 1202 synd_status = AFLT_STAT_INVALID; 1203 else 1204 synd_status = AFLT_STAT_VALID; 1205 1206 flt_in_memory = (*afsr & SFSR_MEMORY) && 1207 pf_is_memory(afar >> MMU_PAGESHIFT); 1208 1209 ret = cpu_get_mem_unum(synd_status, (ushort_t)synd, *afsr, afar, 1210 CPU->cpu_id, flt_in_memory, flt_status, unum, 1211 UNUM_NAMLEN, lenp); 1212 if (ret != 0) 1213 return (ret); 1214 1215 if (*lenp >= buflen) 1216 return (ENAMETOOLONG); 1217 1218 (void) strncpy(buf, unum, buflen); 1219 1220 return (0); 1221 } 1222 1223 /* 1224 * Routine to return memory information associated 1225 * with a physical address and syndrome. 1226 */ 1227 /*ARGSUSED*/ 1228 int 1229 cpu_get_mem_info(uint64_t synd, uint64_t afar, 1230 uint64_t *mem_sizep, uint64_t *seg_sizep, uint64_t *bank_sizep, 1231 int *segsp, int *banksp, int *mcidp) 1232 { 1233 int synd_code = (int)synd; 1234 1235 if (afar == (uint64_t)-1) 1236 return (ENXIO); 1237 1238 if (p2get_mem_info != NULL) 1239 return ((p2get_mem_info)(synd_code, afar, 1240 mem_sizep, seg_sizep, bank_sizep, 1241 segsp, banksp, mcidp)); 1242 else 1243 return (ENOTSUP); 1244 } 1245 1246 /* 1247 * Routine to return a string identifying the physical 1248 * name associated with a cpuid. 1249 */ 1250 int 1251 cpu_get_cpu_unum(int cpuid, char *buf, int buflen, int *lenp) 1252 { 1253 int ret; 1254 char unum[UNUM_NAMLEN]; 1255 1256 if (&plat_get_cpu_unum) { 1257 if ((ret = plat_get_cpu_unum(cpuid, unum, UNUM_NAMLEN, lenp)) 1258 != 0) 1259 return (ret); 1260 } else { 1261 return (ENOTSUP); 1262 } 1263 1264 if (*lenp >= buflen) 1265 return (ENAMETOOLONG); 1266 1267 (void) strncpy(buf, unum, *lenp); 1268 1269 return (0); 1270 } 1271 1272 /* 1273 * This routine exports the name buffer size. 1274 */ 1275 size_t 1276 cpu_get_name_bufsize() 1277 { 1278 return (UNUM_NAMLEN); 1279 } 1280 1281 /* 1282 * Flush the entire ecache by ASI_L2_CNTL.U2_FLUSH 1283 */ 1284 void 1285 cpu_flush_ecache(void) 1286 { 1287 flush_ecache(ecache_flushaddr, cpunodes[CPU->cpu_id].ecache_size, 1288 cpunodes[CPU->cpu_id].ecache_linesize); 1289 } 1290 1291 static uint8_t 1292 flt_to_trap_type(struct async_flt *aflt) 1293 { 1294 if (aflt->flt_status & OPL_ECC_ISYNC_TRAP) 1295 return (TRAP_TYPE_ECC_I); 1296 if (aflt->flt_status & OPL_ECC_DSYNC_TRAP) 1297 return (TRAP_TYPE_ECC_D); 1298 if (aflt->flt_status & OPL_ECC_URGENT_TRAP) 1299 return (TRAP_TYPE_URGENT); 1300 return (-1); 1301 } 1302 1303 /* 1304 * Encode the data saved in the opl_async_flt_t struct into 1305 * the FM ereport payload. 1306 */ 1307 /* ARGSUSED */ 1308 static void 1309 cpu_payload_add_aflt(struct async_flt *aflt, nvlist_t *payload, 1310 nvlist_t *resource) 1311 { 1312 opl_async_flt_t *opl_flt = (opl_async_flt_t *)aflt; 1313 char unum[UNUM_NAMLEN]; 1314 char sbuf[21]; /* sizeof (UINT64_MAX) + '\0' */ 1315 int len; 1316 1317 1318 if (aflt->flt_payload & FM_EREPORT_PAYLOAD_FLAG_SFSR) { 1319 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_SFSR, 1320 DATA_TYPE_UINT64, aflt->flt_stat, NULL); 1321 } 1322 if (aflt->flt_payload & FM_EREPORT_PAYLOAD_FLAG_SFAR) { 1323 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_SFAR, 1324 DATA_TYPE_UINT64, aflt->flt_addr, NULL); 1325 } 1326 if (aflt->flt_payload & FM_EREPORT_PAYLOAD_FLAG_UGESR) { 1327 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_UGESR, 1328 DATA_TYPE_UINT64, aflt->flt_stat, NULL); 1329 } 1330 if (aflt->flt_payload & FM_EREPORT_PAYLOAD_FLAG_PC) { 1331 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_PC, 1332 DATA_TYPE_UINT64, (uint64_t)aflt->flt_pc, NULL); 1333 } 1334 if (aflt->flt_payload & FM_EREPORT_PAYLOAD_FLAG_TL) { 1335 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_TL, 1336 DATA_TYPE_UINT8, (uint8_t)aflt->flt_tl, NULL); 1337 } 1338 if (aflt->flt_payload & FM_EREPORT_PAYLOAD_FLAG_TT) { 1339 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_TT, 1340 DATA_TYPE_UINT8, flt_to_trap_type(aflt), NULL); 1341 } 1342 if (aflt->flt_payload & FM_EREPORT_PAYLOAD_FLAG_PRIV) { 1343 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_PRIV, 1344 DATA_TYPE_BOOLEAN_VALUE, 1345 (aflt->flt_priv ? B_TRUE : B_FALSE), NULL); 1346 } 1347 if (aflt->flt_payload & FM_EREPORT_PAYLOAD_FLAG_FLT_STATUS) { 1348 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_FLT_STATUS, 1349 DATA_TYPE_UINT64, (uint64_t)aflt->flt_status, NULL); 1350 } 1351 1352 switch (opl_flt->flt_eid_mod) { 1353 case OPL_ERRID_CPU: 1354 (void) snprintf(sbuf, sizeof (sbuf), "%llX", 1355 (u_longlong_t)cpunodes[opl_flt->flt_eid_sid].device_id); 1356 (void) fm_fmri_cpu_set(resource, FM_CPU_SCHEME_VERSION, 1357 NULL, opl_flt->flt_eid_sid, 1358 (uint8_t *)&cpunodes[opl_flt->flt_eid_sid].version, 1359 sbuf); 1360 fm_payload_set(payload, 1361 FM_EREPORT_PAYLOAD_NAME_RESOURCE, 1362 DATA_TYPE_NVLIST, resource, NULL); 1363 break; 1364 1365 case OPL_ERRID_CHANNEL: 1366 /* 1367 * No resource is created but the cpumem DE will find 1368 * the defective path by retreiving EID from SFSR which is 1369 * included in the payload. 1370 */ 1371 break; 1372 1373 case OPL_ERRID_MEM: 1374 (void) cpu_get_mem_unum_aflt(0, aflt, unum, UNUM_NAMLEN, &len); 1375 (void) fm_fmri_mem_set(resource, FM_MEM_SCHEME_VERSION, 1376 NULL, unum, NULL, (uint64_t)-1); 1377 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_RESOURCE, 1378 DATA_TYPE_NVLIST, resource, NULL); 1379 break; 1380 1381 case OPL_ERRID_PATH: 1382 /* 1383 * No resource is created but the cpumem DE will find 1384 * the defective path by retreiving EID from SFSR which is 1385 * included in the payload. 1386 */ 1387 break; 1388 } 1389 } 1390 1391 /* 1392 * Returns whether fault address is valid for this error bit and 1393 * whether the address is "in memory" (i.e. pf_is_memory returns 1). 1394 */ 1395 /*ARGSUSED*/ 1396 static int 1397 cpu_flt_in_memory(opl_async_flt_t *opl_flt, uint64_t t_afsr_bit) 1398 { 1399 struct async_flt *aflt = (struct async_flt *)opl_flt; 1400 1401 if (aflt->flt_status & (OPL_ECC_SYNC_TRAP)) { 1402 return ((t_afsr_bit & SFSR_MEMORY) && 1403 pf_is_memory(aflt->flt_addr >> MMU_PAGESHIFT)); 1404 } 1405 return (0); 1406 } 1407 1408 /* 1409 * In OPL SCF does the stick synchronization. 1410 */ 1411 void 1412 sticksync_slave(void) 1413 { 1414 } 1415 1416 /* 1417 * In OPL SCF does the stick synchronization. 1418 */ 1419 void 1420 sticksync_master(void) 1421 { 1422 } 1423 1424 /* 1425 * Cpu private unitialization. OPL cpus do not use the private area. 1426 */ 1427 void 1428 cpu_uninit_private(struct cpu *cp) 1429 { 1430 cmp_delete_cpu(cp->cpu_id); 1431 } 1432 1433 /* 1434 * Always flush an entire cache. 1435 */ 1436 void 1437 cpu_error_ecache_flush(void) 1438 { 1439 cpu_flush_ecache(); 1440 } 1441 1442 void 1443 cpu_ereport_post(struct async_flt *aflt) 1444 { 1445 char *cpu_type, buf[FM_MAX_CLASS]; 1446 nv_alloc_t *nva = NULL; 1447 nvlist_t *ereport, *detector, *resource; 1448 errorq_elem_t *eqep; 1449 char sbuf[21]; /* sizeof (UINT64_MAX) + '\0' */ 1450 1451 if (aflt->flt_panic || panicstr) { 1452 eqep = errorq_reserve(ereport_errorq); 1453 if (eqep == NULL) 1454 return; 1455 ereport = errorq_elem_nvl(ereport_errorq, eqep); 1456 nva = errorq_elem_nva(ereport_errorq, eqep); 1457 } else { 1458 ereport = fm_nvlist_create(nva); 1459 } 1460 1461 /* 1462 * Create the scheme "cpu" FMRI. 1463 */ 1464 detector = fm_nvlist_create(nva); 1465 resource = fm_nvlist_create(nva); 1466 switch (cpunodes[aflt->flt_inst].implementation) { 1467 case OLYMPUS_C_IMPL: 1468 cpu_type = FM_EREPORT_CPU_SPARC64_VI; 1469 break; 1470 default: 1471 cpu_type = FM_EREPORT_CPU_UNSUPPORTED; 1472 break; 1473 } 1474 (void) snprintf(sbuf, sizeof (sbuf), "%llX", 1475 (u_longlong_t)cpunodes[aflt->flt_inst].device_id); 1476 (void) fm_fmri_cpu_set(detector, FM_CPU_SCHEME_VERSION, NULL, 1477 aflt->flt_inst, (uint8_t *)&cpunodes[aflt->flt_inst].version, 1478 sbuf); 1479 1480 /* 1481 * Encode all the common data into the ereport. 1482 */ 1483 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s.%s", 1484 FM_ERROR_CPU, cpu_type, aflt->flt_erpt_class); 1485 1486 fm_ereport_set(ereport, FM_EREPORT_VERSION, buf, 1487 fm_ena_generate(aflt->flt_id, FM_ENA_FMT1), detector, NULL); 1488 1489 /* 1490 * Encode the error specific data that was saved in 1491 * the async_flt structure into the ereport. 1492 */ 1493 cpu_payload_add_aflt(aflt, ereport, resource); 1494 1495 if (aflt->flt_panic || panicstr) { 1496 errorq_commit(ereport_errorq, eqep, ERRORQ_SYNC); 1497 } else { 1498 (void) fm_ereport_post(ereport, EVCH_TRYHARD); 1499 fm_nvlist_destroy(ereport, FM_NVA_FREE); 1500 fm_nvlist_destroy(detector, FM_NVA_FREE); 1501 fm_nvlist_destroy(resource, FM_NVA_FREE); 1502 } 1503 } 1504 1505 void 1506 cpu_run_bus_error_handlers(struct async_flt *aflt, int expected) 1507 { 1508 int status; 1509 ddi_fm_error_t de; 1510 1511 bzero(&de, sizeof (ddi_fm_error_t)); 1512 1513 de.fme_version = DDI_FME_VERSION; 1514 de.fme_ena = fm_ena_generate(aflt->flt_id, FM_ENA_FMT1); 1515 de.fme_flag = expected; 1516 de.fme_bus_specific = (void *)aflt->flt_addr; 1517 status = ndi_fm_handler_dispatch(ddi_root_node(), NULL, &de); 1518 if ((aflt->flt_prot == AFLT_PROT_NONE) && (status == DDI_FM_FATAL)) 1519 aflt->flt_panic = 1; 1520 } 1521 1522 void 1523 cpu_errorq_dispatch(char *error_class, void *payload, size_t payload_sz, 1524 errorq_t *eqp, uint_t flag) 1525 { 1526 struct async_flt *aflt = (struct async_flt *)payload; 1527 1528 aflt->flt_erpt_class = error_class; 1529 errorq_dispatch(eqp, payload, payload_sz, flag); 1530 } 1531 1532 void 1533 adjust_hw_copy_limits(int ecache_size) 1534 { 1535 /* 1536 * Set hw copy limits. 1537 * 1538 * /etc/system will be parsed later and can override one or more 1539 * of these settings. 1540 * 1541 * At this time, ecache size seems only mildly relevant. 1542 * We seem to run into issues with the d-cache and stalls 1543 * we see on misses. 1544 * 1545 * Cycle measurement indicates that 2 byte aligned copies fare 1546 * little better than doing things with VIS at around 512 bytes. 1547 * 4 byte aligned shows promise until around 1024 bytes. 8 Byte 1548 * aligned is faster whenever the source and destination data 1549 * in cache and the total size is less than 2 Kbytes. The 2K 1550 * limit seems to be driven by the 2K write cache. 1551 * When more than 2K of copies are done in non-VIS mode, stores 1552 * backup in the write cache. In VIS mode, the write cache is 1553 * bypassed, allowing faster cache-line writes aligned on cache 1554 * boundaries. 1555 * 1556 * In addition, in non-VIS mode, there is no prefetching, so 1557 * for larger copies, the advantage of prefetching to avoid even 1558 * occasional cache misses is enough to justify using the VIS code. 1559 * 1560 * During testing, it was discovered that netbench ran 3% slower 1561 * when hw_copy_limit_8 was 2K or larger. Apparently for server 1562 * applications, data is only used once (copied to the output 1563 * buffer, then copied by the network device off the system). Using 1564 * the VIS copy saves more L2 cache state. Network copies are 1565 * around 1.3K to 1.5K in size for historical reasons. 1566 * 1567 * Therefore, a limit of 1K bytes will be used for the 8 byte 1568 * aligned copy even for large caches and 8 MB ecache. The 1569 * infrastructure to allow different limits for different sized 1570 * caches is kept to allow further tuning in later releases. 1571 */ 1572 1573 if (min_ecache_size == 0 && use_hw_bcopy) { 1574 /* 1575 * First time through - should be before /etc/system 1576 * is read. 1577 * Could skip the checks for zero but this lets us 1578 * preserve any debugger rewrites. 1579 */ 1580 if (hw_copy_limit_1 == 0) { 1581 hw_copy_limit_1 = VIS_COPY_THRESHOLD; 1582 priv_hcl_1 = hw_copy_limit_1; 1583 } 1584 if (hw_copy_limit_2 == 0) { 1585 hw_copy_limit_2 = 2 * VIS_COPY_THRESHOLD; 1586 priv_hcl_2 = hw_copy_limit_2; 1587 } 1588 if (hw_copy_limit_4 == 0) { 1589 hw_copy_limit_4 = 4 * VIS_COPY_THRESHOLD; 1590 priv_hcl_4 = hw_copy_limit_4; 1591 } 1592 if (hw_copy_limit_8 == 0) { 1593 hw_copy_limit_8 = 4 * VIS_COPY_THRESHOLD; 1594 priv_hcl_8 = hw_copy_limit_8; 1595 } 1596 min_ecache_size = ecache_size; 1597 } else { 1598 /* 1599 * MP initialization. Called *after* /etc/system has 1600 * been parsed. One CPU has already been initialized. 1601 * Need to cater for /etc/system having scragged one 1602 * of our values. 1603 */ 1604 if (ecache_size == min_ecache_size) { 1605 /* 1606 * Same size ecache. We do nothing unless we 1607 * have a pessimistic ecache setting. In that 1608 * case we become more optimistic (if the cache is 1609 * large enough). 1610 */ 1611 if (hw_copy_limit_8 == 4 * VIS_COPY_THRESHOLD) { 1612 /* 1613 * Need to adjust hw_copy_limit* from our 1614 * pessimistic uniprocessor value to a more 1615 * optimistic UP value *iff* it hasn't been 1616 * reset. 1617 */ 1618 if ((ecache_size > 1048576) && 1619 (priv_hcl_8 == hw_copy_limit_8)) { 1620 if (ecache_size <= 2097152) 1621 hw_copy_limit_8 = 4 * 1622 VIS_COPY_THRESHOLD; 1623 else if (ecache_size <= 4194304) 1624 hw_copy_limit_8 = 4 * 1625 VIS_COPY_THRESHOLD; 1626 else 1627 hw_copy_limit_8 = 4 * 1628 VIS_COPY_THRESHOLD; 1629 priv_hcl_8 = hw_copy_limit_8; 1630 } 1631 } 1632 } else if (ecache_size < min_ecache_size) { 1633 /* 1634 * A different ecache size. Can this even happen? 1635 */ 1636 if (priv_hcl_8 == hw_copy_limit_8) { 1637 /* 1638 * The previous value that we set 1639 * is unchanged (i.e., it hasn't been 1640 * scragged by /etc/system). Rewrite it. 1641 */ 1642 if (ecache_size <= 1048576) 1643 hw_copy_limit_8 = 8 * 1644 VIS_COPY_THRESHOLD; 1645 else if (ecache_size <= 2097152) 1646 hw_copy_limit_8 = 8 * 1647 VIS_COPY_THRESHOLD; 1648 else if (ecache_size <= 4194304) 1649 hw_copy_limit_8 = 8 * 1650 VIS_COPY_THRESHOLD; 1651 else 1652 hw_copy_limit_8 = 10 * 1653 VIS_COPY_THRESHOLD; 1654 priv_hcl_8 = hw_copy_limit_8; 1655 min_ecache_size = ecache_size; 1656 } 1657 } 1658 } 1659 } 1660 1661 #define VIS_BLOCKSIZE 64 1662 1663 int 1664 dtrace_blksuword32_err(uintptr_t addr, uint32_t *data) 1665 { 1666 int ret, watched; 1667 1668 watched = watch_disable_addr((void *)addr, VIS_BLOCKSIZE, S_WRITE); 1669 ret = dtrace_blksuword32(addr, data, 0); 1670 if (watched) 1671 watch_enable_addr((void *)addr, VIS_BLOCKSIZE, S_WRITE); 1672 1673 return (ret); 1674 } 1675 1676 void 1677 opl_cpu_reg_init() 1678 { 1679 uint64_t this_cpu_log; 1680 1681 /* 1682 * We do not need to re-initialize cpu0 registers. 1683 */ 1684 if (cpu[getprocessorid()] == &cpu0) 1685 return; 1686 1687 /* 1688 * Initialize Error log Scratch register for error handling. 1689 */ 1690 1691 this_cpu_log = va_to_pa((void*)(((uint64_t)opl_err_log) + 1692 ERRLOG_BUFSZ * (getprocessorid()))); 1693 opl_error_setup(this_cpu_log); 1694 1695 /* 1696 * Enable MMU translating multiple page sizes for 1697 * sITLB and sDTLB. 1698 */ 1699 opl_mpg_enable(); 1700 } 1701 1702 /* 1703 * Queue one event in ue_queue based on ecc_type_to_info entry. 1704 */ 1705 static void 1706 cpu_queue_one_event(opl_async_flt_t *opl_flt, char *reason, 1707 ecc_type_to_info_t *eccp) 1708 { 1709 struct async_flt *aflt = (struct async_flt *)opl_flt; 1710 1711 if (reason && 1712 strlen(reason) + strlen(eccp->ec_reason) < MAX_REASON_STRING) { 1713 (void) strcat(reason, eccp->ec_reason); 1714 } 1715 1716 opl_flt->flt_bit = eccp->ec_afsr_bit; 1717 opl_flt->flt_type = eccp->ec_flt_type; 1718 aflt->flt_in_memory = cpu_flt_in_memory(opl_flt, opl_flt->flt_bit); 1719 aflt->flt_payload = eccp->ec_err_payload; 1720 1721 ASSERT(aflt->flt_status & (OPL_ECC_SYNC_TRAP|OPL_ECC_URGENT_TRAP)); 1722 cpu_errorq_dispatch(eccp->ec_err_class, 1723 (void *)opl_flt, sizeof (opl_async_flt_t), 1724 ue_queue, 1725 aflt->flt_panic); 1726 } 1727 1728 /* 1729 * Queue events on async event queue one event per error bit. 1730 * Return number of events queued. 1731 */ 1732 int 1733 cpu_queue_events(opl_async_flt_t *opl_flt, char *reason, uint64_t t_afsr_errs) 1734 { 1735 struct async_flt *aflt = (struct async_flt *)opl_flt; 1736 ecc_type_to_info_t *eccp; 1737 int nevents = 0; 1738 1739 /* 1740 * Queue expected errors, error bit and fault type must must match 1741 * in the ecc_type_to_info table. 1742 */ 1743 for (eccp = ecc_type_to_info; t_afsr_errs != 0 && eccp->ec_desc != NULL; 1744 eccp++) { 1745 if ((eccp->ec_afsr_bit & t_afsr_errs) != 0 && 1746 (eccp->ec_flags & aflt->flt_status) != 0) { 1747 /* 1748 * UE error event can be further 1749 * classified/breakdown into finer granularity 1750 * based on the flt_eid_mod value set by HW. We do 1751 * special handling here so that we can report UE 1752 * error in finer granularity as ue_mem, 1753 * ue_channel, ue_cpu or ue_path. 1754 */ 1755 if (eccp->ec_flt_type == OPL_CPU_SYNC_UE) { 1756 opl_flt->flt_eid_mod = 1757 (aflt->flt_stat & SFSR_EID_MOD) 1758 >> SFSR_EID_MOD_SHIFT; 1759 opl_flt->flt_eid_sid = 1760 (aflt->flt_stat & SFSR_EID_SID) 1761 >> SFSR_EID_SID_SHIFT; 1762 /* 1763 * Need to advance eccp pointer by flt_eid_mod 1764 * so that we get an appropriate ecc pointer 1765 * 1766 * EID # of advances 1767 * ---------------------------------- 1768 * OPL_ERRID_MEM 0 1769 * OPL_ERRID_CHANNEL 1 1770 * OPL_ERRID_CPU 2 1771 * OPL_ERRID_PATH 3 1772 */ 1773 eccp += opl_flt->flt_eid_mod; 1774 } 1775 cpu_queue_one_event(opl_flt, reason, eccp); 1776 t_afsr_errs &= ~eccp->ec_afsr_bit; 1777 nevents++; 1778 } 1779 } 1780 1781 return (nevents); 1782 } 1783 1784 /* 1785 * Sync. error wrapper functions. 1786 * We use these functions in order to transfer here from the 1787 * nucleus trap handler information about trap type (data or 1788 * instruction) and trap level (0 or above 0). This way we 1789 * get rid of using SFSR's reserved bits. 1790 */ 1791 1792 #define OPL_SYNC_TL0 0 1793 #define OPL_SYNC_TL1 1 1794 #define OPL_ISYNC_ERR 0 1795 #define OPL_DSYNC_ERR 1 1796 1797 void 1798 opl_cpu_isync_tl0_error(struct regs *rp, ulong_t p_sfar, ulong_t p_sfsr) 1799 { 1800 uint64_t t_sfar = p_sfar; 1801 uint64_t t_sfsr = p_sfsr; 1802 1803 opl_cpu_sync_error(rp, t_sfar, t_sfsr, 1804 OPL_SYNC_TL0, OPL_ISYNC_ERR); 1805 } 1806 1807 void 1808 opl_cpu_isync_tl1_error(struct regs *rp, ulong_t p_sfar, ulong_t p_sfsr) 1809 { 1810 uint64_t t_sfar = p_sfar; 1811 uint64_t t_sfsr = p_sfsr; 1812 1813 opl_cpu_sync_error(rp, t_sfar, t_sfsr, 1814 OPL_SYNC_TL1, OPL_ISYNC_ERR); 1815 } 1816 1817 void 1818 opl_cpu_dsync_tl0_error(struct regs *rp, ulong_t p_sfar, ulong_t p_sfsr) 1819 { 1820 uint64_t t_sfar = p_sfar; 1821 uint64_t t_sfsr = p_sfsr; 1822 1823 opl_cpu_sync_error(rp, t_sfar, t_sfsr, 1824 OPL_SYNC_TL0, OPL_DSYNC_ERR); 1825 } 1826 1827 void 1828 opl_cpu_dsync_tl1_error(struct regs *rp, ulong_t p_sfar, ulong_t p_sfsr) 1829 { 1830 uint64_t t_sfar = p_sfar; 1831 uint64_t t_sfsr = p_sfsr; 1832 1833 opl_cpu_sync_error(rp, t_sfar, t_sfsr, 1834 OPL_SYNC_TL1, OPL_DSYNC_ERR); 1835 } 1836 1837 /* 1838 * The fj sync err handler transfers control here for UE, BERR, TO, TLB_MUL 1839 * and TLB_PRT. 1840 * This function is designed based on cpu_deferred_error(). 1841 */ 1842 1843 static void 1844 opl_cpu_sync_error(struct regs *rp, ulong_t t_sfar, ulong_t t_sfsr, 1845 uint_t tl, uint_t derr) 1846 { 1847 opl_async_flt_t opl_flt; 1848 struct async_flt *aflt; 1849 int trampolined = 0; 1850 char pr_reason[MAX_REASON_STRING]; 1851 uint64_t log_sfsr; 1852 int expected = DDI_FM_ERR_UNEXPECTED; 1853 ddi_acc_hdl_t *hp; 1854 1855 /* 1856 * We need to look at p_flag to determine if the thread detected an 1857 * error while dumping core. We can't grab p_lock here, but it's ok 1858 * because we just need a consistent snapshot and we know that everyone 1859 * else will store a consistent set of bits while holding p_lock. We 1860 * don't have to worry about a race because SDOCORE is set once prior 1861 * to doing i/o from the process's address space and is never cleared. 1862 */ 1863 uint_t pflag = ttoproc(curthread)->p_flag; 1864 1865 pr_reason[0] = '\0'; 1866 1867 /* 1868 * handle the specific error 1869 */ 1870 bzero(&opl_flt, sizeof (opl_async_flt_t)); 1871 aflt = (struct async_flt *)&opl_flt; 1872 aflt->flt_id = gethrtime_waitfree(); 1873 aflt->flt_bus_id = getprocessorid(); 1874 aflt->flt_inst = CPU->cpu_id; 1875 aflt->flt_stat = t_sfsr; 1876 aflt->flt_addr = t_sfar; 1877 aflt->flt_pc = (caddr_t)rp->r_pc; 1878 aflt->flt_prot = (uchar_t)AFLT_PROT_NONE; 1879 aflt->flt_class = (uchar_t)CPU_FAULT; 1880 aflt->flt_priv = (uchar_t) 1881 (tl == 1 ? 1 : ((rp->r_tstate & TSTATE_PRIV) ? 1 : 0)); 1882 aflt->flt_tl = (uchar_t)tl; 1883 aflt->flt_panic = (uchar_t)(tl != 0 || aft_testfatal != 0 || 1884 (t_sfsr & (SFSR_TLB_MUL|SFSR_TLB_PRT)) != 0); 1885 aflt->flt_core = (pflag & SDOCORE) ? 1 : 0; 1886 aflt->flt_status = (derr) ? OPL_ECC_DSYNC_TRAP : OPL_ECC_ISYNC_TRAP; 1887 1888 /* 1889 * If SFSR.FV is not set, both SFSR and SFAR/SFPAR values are uncertain. 1890 * So, clear all error bits to avoid mis-handling and force the system 1891 * panicked. 1892 * We skip all the procedures below down to the panic message call. 1893 */ 1894 if (!(t_sfsr & SFSR_FV)) { 1895 opl_flt.flt_type = OPL_CPU_INV_SFSR; 1896 aflt->flt_panic = 1; 1897 aflt->flt_payload = FM_EREPORT_PAYLOAD_SYNC; 1898 cpu_errorq_dispatch(FM_EREPORT_CPU_INV_SFSR, 1899 (void *)&opl_flt, sizeof (opl_async_flt_t), ue_queue, 1900 aflt->flt_panic); 1901 fm_panic("%sErrors(s)", "invalid SFSR"); 1902 } 1903 1904 /* 1905 * If either UE and MK bit is off, this is not valid UE error. 1906 * If it is not valid UE error, clear UE & MK_UE bits to prevent 1907 * mis-handling below. 1908 * aflt->flt_stat keeps the original bits as a reference. 1909 */ 1910 if ((t_sfsr & (SFSR_MK_UE|SFSR_UE)) != 1911 (SFSR_MK_UE|SFSR_UE)) { 1912 t_sfsr &= ~(SFSR_MK_UE|SFSR_UE); 1913 } 1914 1915 /* 1916 * If the trap occurred in privileged mode at TL=0, we need to check to 1917 * see if we were executing in the kernel under on_trap() or t_lofault 1918 * protection. If so, modify the saved registers so that we return 1919 * from the trap to the appropriate trampoline routine. 1920 */ 1921 if (!aflt->flt_panic && aflt->flt_priv && tl == 0) { 1922 if (curthread->t_ontrap != NULL) { 1923 on_trap_data_t *otp = curthread->t_ontrap; 1924 1925 if (otp->ot_prot & OT_DATA_EC) { 1926 aflt->flt_prot = (uchar_t)AFLT_PROT_EC; 1927 otp->ot_trap |= (ushort_t)OT_DATA_EC; 1928 rp->r_pc = otp->ot_trampoline; 1929 rp->r_npc = rp->r_pc + 4; 1930 trampolined = 1; 1931 } 1932 1933 if ((t_sfsr & (SFSR_TO | SFSR_BERR)) && 1934 (otp->ot_prot & OT_DATA_ACCESS)) { 1935 aflt->flt_prot = (uchar_t)AFLT_PROT_ACCESS; 1936 otp->ot_trap |= (ushort_t)OT_DATA_ACCESS; 1937 rp->r_pc = otp->ot_trampoline; 1938 rp->r_npc = rp->r_pc + 4; 1939 trampolined = 1; 1940 /* 1941 * for peeks and caut_gets errors are expected 1942 */ 1943 hp = (ddi_acc_hdl_t *)otp->ot_handle; 1944 if (!hp) 1945 expected = DDI_FM_ERR_PEEK; 1946 else if (hp->ah_acc.devacc_attr_access == 1947 DDI_CAUTIOUS_ACC) 1948 expected = DDI_FM_ERR_EXPECTED; 1949 } 1950 1951 } else if (curthread->t_lofault) { 1952 aflt->flt_prot = AFLT_PROT_COPY; 1953 rp->r_g1 = EFAULT; 1954 rp->r_pc = curthread->t_lofault; 1955 rp->r_npc = rp->r_pc + 4; 1956 trampolined = 1; 1957 } 1958 } 1959 1960 /* 1961 * If we're in user mode or we're doing a protected copy, we either 1962 * want the ASTON code below to send a signal to the user process 1963 * or we want to panic if aft_panic is set. 1964 * 1965 * If we're in privileged mode and we're not doing a copy, then we 1966 * need to check if we've trampolined. If we haven't trampolined, 1967 * we should panic. 1968 */ 1969 if (!aflt->flt_priv || aflt->flt_prot == AFLT_PROT_COPY) { 1970 if (t_sfsr & (SFSR_ERRS & ~(SFSR_BERR | SFSR_TO))) 1971 aflt->flt_panic |= aft_panic; 1972 } else if (!trampolined) { 1973 aflt->flt_panic = 1; 1974 } 1975 1976 /* 1977 * If we've trampolined due to a privileged TO or BERR, or if an 1978 * unprivileged TO or BERR occurred, we don't want to enqueue an 1979 * event for that TO or BERR. Queue all other events (if any) besides 1980 * the TO/BERR. 1981 */ 1982 log_sfsr = t_sfsr; 1983 if (trampolined) { 1984 log_sfsr &= ~(SFSR_TO | SFSR_BERR); 1985 } else if (!aflt->flt_priv) { 1986 /* 1987 * User mode, suppress messages if 1988 * cpu_berr_to_verbose is not set. 1989 */ 1990 if (!cpu_berr_to_verbose) 1991 log_sfsr &= ~(SFSR_TO | SFSR_BERR); 1992 } 1993 1994 if (((log_sfsr & SFSR_ERRS) && 1995 (cpu_queue_events(&opl_flt, pr_reason, t_sfsr) == 0)) || 1996 ((t_sfsr & SFSR_ERRS) == 0)) { 1997 opl_flt.flt_type = OPL_CPU_INV_SFSR; 1998 aflt->flt_payload = FM_EREPORT_PAYLOAD_SYNC; 1999 cpu_errorq_dispatch(FM_EREPORT_CPU_INV_SFSR, 2000 (void *)&opl_flt, sizeof (opl_async_flt_t), ue_queue, 2001 aflt->flt_panic); 2002 } 2003 2004 if (t_sfsr & (SFSR_UE|SFSR_TO|SFSR_BERR)) { 2005 cpu_run_bus_error_handlers(aflt, expected); 2006 } 2007 2008 /* 2009 * Panic here if aflt->flt_panic has been set. Enqueued errors will 2010 * be logged as part of the panic flow. 2011 */ 2012 if (aflt->flt_panic) { 2013 if (pr_reason[0] == 0) 2014 strcpy(pr_reason, "invalid SFSR "); 2015 2016 fm_panic("%sErrors(s)", pr_reason); 2017 } 2018 2019 /* 2020 * If we queued an error and we are going to return from the trap and 2021 * the error was in user mode or inside of a copy routine, set AST flag 2022 * so the queue will be drained before returning to user mode. The 2023 * AST processing will also act on our failure policy. 2024 */ 2025 if (!aflt->flt_priv || aflt->flt_prot == AFLT_PROT_COPY) { 2026 int pcb_flag = 0; 2027 2028 if (t_sfsr & (SFSR_ERRS & 2029 ~(SFSR_BERR | SFSR_TO))) 2030 pcb_flag |= ASYNC_HWERR; 2031 2032 if (t_sfsr & SFSR_BERR) 2033 pcb_flag |= ASYNC_BERR; 2034 2035 if (t_sfsr & SFSR_TO) 2036 pcb_flag |= ASYNC_BTO; 2037 2038 ttolwp(curthread)->lwp_pcb.pcb_flags |= pcb_flag; 2039 aston(curthread); 2040 } 2041 } 2042 2043 /*ARGSUSED*/ 2044 void 2045 opl_cpu_urgent_error(struct regs *rp, ulong_t p_ugesr, ulong_t tl) 2046 { 2047 opl_async_flt_t opl_flt; 2048 struct async_flt *aflt; 2049 char pr_reason[MAX_REASON_STRING]; 2050 2051 /* normalize tl */ 2052 tl = (tl >= 2 ? 1 : 0); 2053 pr_reason[0] = '\0'; 2054 2055 bzero(&opl_flt, sizeof (opl_async_flt_t)); 2056 aflt = (struct async_flt *)&opl_flt; 2057 aflt->flt_id = gethrtime_waitfree(); 2058 aflt->flt_bus_id = getprocessorid(); 2059 aflt->flt_inst = CPU->cpu_id; 2060 aflt->flt_stat = p_ugesr; 2061 aflt->flt_pc = (caddr_t)rp->r_pc; 2062 aflt->flt_class = (uchar_t)CPU_FAULT; 2063 aflt->flt_tl = tl; 2064 aflt->flt_priv = (uchar_t) 2065 (tl == 1 ? 1 : ((rp->r_tstate & TSTATE_PRIV) ? 1 : 0)); 2066 aflt->flt_status = OPL_ECC_URGENT_TRAP; 2067 aflt->flt_panic = 1; 2068 /* 2069 * HW does not set mod/sid in case of urgent error. 2070 * So we have to set it here. 2071 */ 2072 opl_flt.flt_eid_mod = OPL_ERRID_CPU; 2073 opl_flt.flt_eid_sid = aflt->flt_inst; 2074 2075 if (cpu_queue_events(&opl_flt, pr_reason, p_ugesr) == 0) { 2076 opl_flt.flt_type = OPL_CPU_INV_UGESR; 2077 aflt->flt_payload = FM_EREPORT_PAYLOAD_URGENT; 2078 cpu_errorq_dispatch(FM_EREPORT_CPU_INV_URG, 2079 (void *)&opl_flt, sizeof (opl_async_flt_t), 2080 ue_queue, aflt->flt_panic); 2081 } 2082 2083 fm_panic("Urgent Error"); 2084 } 2085 2086 /* 2087 * Initialization error counters resetting. 2088 */ 2089 /* ARGSUSED */ 2090 static void 2091 opl_ras_online(void *arg, cpu_t *cp, cyc_handler_t *hdlr, cyc_time_t *when) 2092 { 2093 hdlr->cyh_func = (cyc_func_t)ras_cntr_reset; 2094 hdlr->cyh_level = CY_LOW_LEVEL; 2095 hdlr->cyh_arg = (void *)(uintptr_t)cp->cpu_id; 2096 2097 when->cyt_when = cp->cpu_id * (((hrtime_t)NANOSEC * 10)/ NCPU); 2098 when->cyt_interval = (hrtime_t)NANOSEC * opl_async_check_interval; 2099 } 2100 2101 void 2102 cpu_mp_init(void) 2103 { 2104 cyc_omni_handler_t hdlr; 2105 2106 hdlr.cyo_online = opl_ras_online; 2107 hdlr.cyo_offline = NULL; 2108 hdlr.cyo_arg = NULL; 2109 mutex_enter(&cpu_lock); 2110 (void) cyclic_add_omni(&hdlr); 2111 mutex_exit(&cpu_lock); 2112 } 2113 2114 /*ARGSUSED*/ 2115 void 2116 mmu_init_kernel_pgsz(struct hat *hat) 2117 { 2118 } 2119 2120 size_t 2121 mmu_get_kernel_lpsize(size_t lpsize) 2122 { 2123 uint_t tte; 2124 2125 if (lpsize == 0) { 2126 /* no setting for segkmem_lpsize in /etc/system: use default */ 2127 return (MMU_PAGESIZE4M); 2128 } 2129 2130 for (tte = TTE8K; tte <= TTE4M; tte++) { 2131 if (lpsize == TTEBYTES(tte)) 2132 return (lpsize); 2133 } 2134 2135 return (TTEBYTES(TTE8K)); 2136 } 2137 2138 /* 2139 * The following are functions that are unused in 2140 * OPL cpu module. They are defined here to resolve 2141 * dependencies in the "unix" module. 2142 * Unused functions that should never be called in 2143 * OPL are coded with ASSERT(0). 2144 */ 2145 2146 void 2147 cpu_disable_errors(void) 2148 {} 2149 2150 void 2151 cpu_enable_errors(void) 2152 { ASSERT(0); } 2153 2154 /*ARGSUSED*/ 2155 void 2156 cpu_ce_scrub_mem_err(struct async_flt *ecc, boolean_t t) 2157 { ASSERT(0); } 2158 2159 /*ARGSUSED*/ 2160 void 2161 cpu_faulted_enter(struct cpu *cp) 2162 {} 2163 2164 /*ARGSUSED*/ 2165 void 2166 cpu_faulted_exit(struct cpu *cp) 2167 {} 2168 2169 /*ARGSUSED*/ 2170 void 2171 cpu_check_allcpus(struct async_flt *aflt) 2172 {} 2173 2174 /*ARGSUSED*/ 2175 void 2176 cpu_ce_log_err(struct async_flt *aflt, errorq_elem_t *t) 2177 { ASSERT(0); } 2178 2179 /*ARGSUSED*/ 2180 void 2181 cpu_check_ce(int flag, uint64_t pa, caddr_t va, uint_t psz) 2182 { ASSERT(0); } 2183 2184 /*ARGSUSED*/ 2185 void 2186 cpu_ce_count_unum(struct async_flt *ecc, int len, char *unum) 2187 { ASSERT(0); } 2188 2189 /*ARGSUSED*/ 2190 void 2191 cpu_busy_ecache_scrub(struct cpu *cp) 2192 {} 2193 2194 /*ARGSUSED*/ 2195 void 2196 cpu_idle_ecache_scrub(struct cpu *cp) 2197 {} 2198 2199 /* ARGSUSED */ 2200 void 2201 cpu_change_speed(uint64_t divisor, uint64_t arg2) 2202 { ASSERT(0); } 2203 2204 void 2205 cpu_init_cache_scrub(void) 2206 {} 2207 2208 /* ARGSUSED */ 2209 int 2210 cpu_get_mem_sid(char *unum, char *buf, int buflen, int *lenp) 2211 { 2212 return (ENOTSUP); 2213 } 2214 2215 /* ARGSUSED */ 2216 int 2217 cpu_get_mem_addr(char *unum, char *sid, uint64_t offset, uint64_t *addrp) 2218 { 2219 return (ENOTSUP); 2220 } 2221 2222 /* ARGSUSED */ 2223 int 2224 cpu_get_mem_offset(uint64_t flt_addr, uint64_t *offp) 2225 { 2226 return (ENOTSUP); 2227 } 2228 2229 /*ARGSUSED*/ 2230 void 2231 itlb_rd_entry(uint_t entry, tte_t *tte, uint64_t *va_tag) 2232 { ASSERT(0); } 2233 2234 /*ARGSUSED*/ 2235 void 2236 dtlb_rd_entry(uint_t entry, tte_t *tte, uint64_t *va_tag) 2237 { ASSERT(0); } 2238