1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/param.h> 29 #include <sys/systm.h> 30 #include <sys/sunddi.h> 31 #include <sys/esunddi.h> 32 #include <sys/sunndi.h> 33 #include <sys/ddi.h> 34 #include <sys/modctl.h> 35 #include <sys/sysmacros.h> 36 #include <sys/note.h> 37 38 #include <sys/platform_module.h> 39 #include <sys/errno.h> 40 #include <sys/i2c/clients/i2c_client.h> 41 #include <sys/cherrystone.h> 42 #include <sys/machsystm.h> 43 #include <sys/promif.h> 44 #include <vm/page.h> 45 #include <sys/memnode.h> 46 #include <vm/vm_dep.h> 47 48 /* Cherrystone Keyswitch Information */ 49 #define CHERRY_KEY_POLL_PORT 3 50 #define CHERRY_KEY_POLL_BIT 2 51 #define CHERRY_KEY_POLL_INTVL 10 52 53 #define SHARED_PCF8584_PATH "/pci@9,700000/ebus@1/i2c@1,2e/nvram@4,a4" 54 static dev_info_t *shared_pcf8584_dip; 55 static kmutex_t cherry_pcf8584_mutex; 56 57 static boolean_t key_locked_bit; 58 static clock_t keypoll_timeout_hz; 59 60 /* 61 * Table that maps memory slices to a specific memnode. 62 */ 63 int slice_to_memnode[CHERRYSTONE_MAX_SLICE]; 64 65 /* 66 * For software memory interleaving support. 67 */ 68 static void update_mem_bounds(int, int, int, uint64_t, uint64_t); 69 70 static uint64_t 71 slice_table[CHERRYSTONE_SBD_SLOTS][CHERRYSTONE_CPUS_PER_BOARD] 72 [CHERRYSTONE_BANKS_PER_MC][2]; 73 74 #define SLICE_PA 0 75 #define SLICE_SPAN 1 76 77 /* Function prototypes */ 78 int (*p2get_mem_unum)(int, uint64_t, char *, int, int *); 79 80 int (*cherry_ssc050_get_port_bit) (dev_info_t *, int, int, uint8_t *, int); 81 extern void (*abort_seq_handler)(); 82 83 static int cherry_dev_search(dev_info_t *, void *); 84 static void keyswitch_poll(void *); 85 static void cherry_abort_seq_handler(char *msg); 86 87 /* Function definitions from this point forward. */ 88 89 int 90 set_platform_tsb_spares() 91 { 92 return (0); 93 } 94 95 void 96 startup_platform(void) 97 { 98 /* 99 * Disable an active h/w watchdog timer 100 * upon exit to OBP. 101 */ 102 extern int disable_watchdog_on_exit; 103 disable_watchdog_on_exit = 1; 104 105 mutex_init(&cherry_pcf8584_mutex, NULL, NULL, NULL); 106 } 107 108 #pragma weak mmu_init_large_pages 109 110 void 111 set_platform_defaults(void) 112 { 113 extern void mmu_init_large_pages(size_t); 114 115 if ((mmu_page_sizes == max_mmu_page_sizes) && 116 (mmu_ism_pagesize != DEFAULT_ISM_PAGESIZE)) { 117 if (&mmu_init_large_pages) 118 mmu_init_large_pages(mmu_ism_pagesize); 119 } 120 } 121 122 void 123 load_platform_modules(void) 124 { 125 if (modload("drv", "pmc") < 0) { 126 cmn_err(CE_NOTE, "pmc driver failed to load"); 127 } 128 } 129 130 void 131 load_platform_drivers(void) 132 { 133 char **drv; 134 dev_info_t *i2cnexus_dip; 135 dev_info_t *keysw_dip = NULL; 136 137 static char *boot_time_drivers[] = { 138 "todds1287", 139 "mc-us3", 140 "ssc050", 141 NULL 142 }; 143 144 for (drv = boot_time_drivers; *drv; drv++) { 145 if (i_ddi_attach_hw_nodes(*drv) != DDI_SUCCESS) 146 cmn_err(CE_WARN, "Failed to install \"%s\" driver.", 147 *drv); 148 } 149 150 /* 151 * mc-us3 and ssc050 must stay loaded for plat_get_mem_unum() 152 * and keyswitch_poll() 153 */ 154 (void) ddi_hold_driver(ddi_name_to_major("mc-us3")); 155 (void) ddi_hold_driver(ddi_name_to_major("ssc050")); 156 157 /* Gain access into the ssc050_get_port function */ 158 cherry_ssc050_get_port_bit = (int (*) (dev_info_t *, int, int, 159 uint8_t *, int)) modgetsymvalue("ssc050_get_port_bit", 0); 160 if (cherry_ssc050_get_port_bit == NULL) { 161 cmn_err(CE_WARN, "cannot find ssc050_get_port_bit"); 162 return; 163 } 164 165 e_ddi_walk_driver("i2c-ssc050", cherry_dev_search, (void *)&keysw_dip); 166 ASSERT(keysw_dip != NULL); 167 168 /* 169 * prevent detach of i2c-ssc050 170 */ 171 e_ddi_hold_devi(keysw_dip); 172 173 keypoll_timeout_hz = drv_usectohz(10 * MICROSEC); 174 keyswitch_poll(keysw_dip); 175 abort_seq_handler = cherry_abort_seq_handler; 176 177 /* 178 * Figure out which pcf8584_dip is shared with OBP for the nvram 179 * device, so the lock can be acquired. 180 */ 181 182 i2cnexus_dip = e_ddi_hold_devi_by_path(SHARED_PCF8584_PATH, 0); 183 184 ASSERT(i2cnexus_dip != NULL); 185 shared_pcf8584_dip = ddi_get_parent(i2cnexus_dip); 186 187 ndi_hold_devi(shared_pcf8584_dip); 188 ndi_rele_devi(i2cnexus_dip); 189 } 190 191 static int 192 cherry_dev_search(dev_info_t *dip, void *arg) 193 { 194 int *dev_regs; /* Info about where the device is. */ 195 uint_t len; 196 int err; 197 198 if (strcmp(ddi_binding_name(dip), "i2c-ssc050") != 0) 199 return (DDI_WALK_CONTINUE); 200 201 err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 202 DDI_PROP_DONTPASS, "reg", &dev_regs, &len); 203 if (err != DDI_PROP_SUCCESS) { 204 return (DDI_WALK_CONTINUE); 205 } 206 /* 207 * regs[0] contains the bus number and regs[1] 208 * contains the device address of the i2c device. 209 * 0x82 is the device address of the i2c device 210 * from which the key switch position is read. 211 */ 212 if (dev_regs[0] == 0 && dev_regs[1] == 0x82) { 213 *((dev_info_t **)arg) = dip; 214 ddi_prop_free(dev_regs); 215 return (DDI_WALK_TERMINATE); 216 } 217 ddi_prop_free(dev_regs); 218 return (DDI_WALK_CONTINUE); 219 } 220 221 static void 222 keyswitch_poll(void *arg) 223 { 224 dev_info_t *dip = arg; 225 uchar_t port_byte; 226 int port = CHERRY_KEY_POLL_PORT; 227 int bit = CHERRY_KEY_POLL_BIT; 228 int err; 229 230 err = cherry_ssc050_get_port_bit(dip, port, bit, 231 &port_byte, I2C_NOSLEEP); 232 if (err != 0) { 233 cmn_err(CE_WARN, "keyswitch polling disabled: " 234 "errno=%d while reading ssc050", err); 235 return; 236 } 237 238 key_locked_bit = (boolean_t)((port_byte & 0x1)); 239 timeout(keyswitch_poll, (caddr_t)dip, keypoll_timeout_hz); 240 } 241 242 static void 243 cherry_abort_seq_handler(char *msg) 244 { 245 if (key_locked_bit == 0) 246 cmn_err(CE_CONT, "KEY in LOCKED position, " 247 "ignoring debug enter sequence"); 248 else { 249 debug_enter(msg); 250 } 251 } 252 253 254 /*ARGSUSED*/ 255 int 256 plat_cpu_poweron(struct cpu *cp) 257 { 258 return (ENOTSUP); /* not supported on this platform */ 259 } 260 261 /*ARGSUSED*/ 262 int 263 plat_cpu_poweroff(struct cpu *cp) 264 { 265 return (ENOTSUP); /* not supported on this platform */ 266 } 267 268 /* 269 * Given a pfn, return the board and beginning/end of the page's 270 * memory controller's address range. 271 */ 272 static int 273 plat_discover_slice(pfn_t pfn, pfn_t *first, pfn_t *last) 274 { 275 int bd, cpu, bank; 276 277 for (bd = 0; bd < CHERRYSTONE_SBD_SLOTS; bd++) { 278 for (cpu = 0; cpu < CHERRYSTONE_CPUS_PER_BOARD; cpu++) { 279 for (bank = 0; bank < CHERRYSTONE_BANKS_PER_MC; 280 bank++) { 281 uint64_t *slice = slice_table[bd][cpu][bank]; 282 uint64_t base = btop(slice[SLICE_PA]); 283 uint64_t len = btop(slice[SLICE_SPAN]); 284 if (len && pfn >= base && pfn < (base + len)) { 285 *first = base; 286 *last = base + len - 1; 287 return (bd); 288 } 289 } 290 } 291 } 292 panic("plat_discover_slice: no slice for pfn 0x%lx\n", pfn); 293 /* NOTREACHED */ 294 } 295 296 /*ARGSUSED*/ 297 void 298 plat_freelist_process(int mnode) 299 {} 300 301 /* 302 * Called for each board/cpu/PA range detected in plat_fill_mc(). 303 */ 304 static void 305 update_mem_bounds(int boardid, int cpuid, int bankid, 306 uint64_t base, uint64_t size) 307 { 308 uint64_t end; 309 int mnode; 310 311 slice_table[boardid][cpuid][bankid][SLICE_PA] = base; 312 slice_table[boardid][cpuid][bankid][SLICE_SPAN] = size; 313 314 end = base + size - 1; 315 316 /* 317 * First see if this board already has a memnode associated 318 * with it. If not, see if this slice has a memnode. This 319 * covers the cases where a single slice covers multiple 320 * boards (cross-board interleaving) and where a single 321 * board has multiple slices (1+GB DIMMs). 322 */ 323 if ((mnode = plat_lgrphand_to_mem_node(boardid)) == -1) { 324 if ((mnode = slice_to_memnode[PA_2_SLICE(base)]) == -1) 325 mnode = mem_node_alloc(); 326 327 ASSERT(mnode >= 0); 328 ASSERT(mnode < MAX_MEM_NODES); 329 plat_assign_lgrphand_to_mem_node(boardid, mnode); 330 } 331 332 base = P2ALIGN(base, (1ul << PA_SLICE_SHIFT)); 333 334 while (base < end) { 335 slice_to_memnode[PA_2_SLICE(base)] = mnode; 336 base += (1ul << PA_SLICE_SHIFT); 337 } 338 } 339 340 /* 341 * Dynamically detect memory slices in the system by decoding 342 * the cpu memory decoder registers at boot time. 343 */ 344 void 345 plat_fill_mc(pnode_t nodeid) 346 { 347 uint64_t mc_addr, saf_addr; 348 uint64_t mc_decode[CHERRYSTONE_BANKS_PER_MC]; 349 uint64_t base, size; 350 uint64_t saf_mask; 351 uint64_t offset; 352 uint32_t regs[4]; 353 int len; 354 int local_mc; 355 int portid; 356 int boardid; 357 int cpuid; 358 int i; 359 360 if ((prom_getprop(nodeid, "portid", (caddr_t)&portid) < 0) || 361 (portid == -1)) 362 return; 363 364 /* 365 * Decode the board number from the MC portid. Assumes 366 * portid == safari agentid. 367 */ 368 boardid = CHERRYSTONE_GETSLOT(portid); 369 cpuid = CHERRYSTONE_GETSID(portid); 370 371 /* 372 * The "reg" property returns 4 32-bit values. The first two are 373 * combined to form a 64-bit address. The second two are for a 374 * 64-bit size, but we don't actually need to look at that value. 375 */ 376 len = prom_getproplen(nodeid, "reg"); 377 if (len != (sizeof (uint32_t) * 4)) { 378 prom_printf("Warning: malformed 'reg' property\n"); 379 return; 380 } 381 if (prom_getprop(nodeid, "reg", (caddr_t)regs) < 0) 382 return; 383 mc_addr = ((uint64_t)regs[0]) << 32; 384 mc_addr |= (uint64_t)regs[1]; 385 386 /* 387 * Figure out whether the memory controller we are examining 388 * belongs to this CPU or a different one. 389 */ 390 saf_addr = lddsafaddr(8); 391 saf_mask = (uint64_t)SAF_MASK; 392 if ((mc_addr & saf_mask) == saf_addr) 393 local_mc = 1; 394 else 395 local_mc = 0; 396 397 for (i = 0; i < CHERRYSTONE_BANKS_PER_MC; i++) { 398 /* 399 * Memory decode masks are at offsets 0x10 - 0x28. 400 */ 401 offset = 0x10 + (i << 3); 402 403 /* 404 * If the memory controller is local to this CPU, we use 405 * the special ASI to read the decode registers. 406 * Otherwise, we load the values from a magic address in 407 * I/O space. 408 */ 409 if (local_mc) 410 mc_decode[i] = lddmcdecode(offset); 411 else 412 mc_decode[i] = lddphysio(mc_addr | offset); 413 414 /* 415 * If the upper bit is set, we have a valid mask 416 */ 417 if ((int64_t)mc_decode[i] < 0) { 418 /* 419 * The memory decode register is a bitmask field, 420 * so we can decode that into both a base and 421 * a span. 422 */ 423 base = MC_BASE(mc_decode[i]) << PHYS2UM_SHIFT; 424 size = MC_UK2SPAN(mc_decode[i]); 425 update_mem_bounds(boardid, cpuid, i, base, size); 426 } 427 } 428 } 429 430 /* 431 * This routine is run midway through the boot process. By the time we get 432 * here, we know about all the active CPU boards in the system, and we have 433 * extracted information about each board's memory from the memory 434 * controllers. We have also figured out which ranges of memory will be 435 * assigned to which memnodes, so we walk the slice table to build the table 436 * of memnodes. 437 */ 438 /* ARGSUSED */ 439 void 440 plat_build_mem_nodes(u_longlong_t *list, size_t nelems) 441 { 442 int slice; 443 pfn_t basepfn; 444 pgcnt_t npgs; 445 446 mem_node_pfn_shift = PFN_SLICE_SHIFT; 447 mem_node_physalign = (1ull << PA_SLICE_SHIFT); 448 npgs = 1ull << PFN_SLICE_SHIFT; 449 450 for (slice = 0; slice < CHERRYSTONE_MAX_SLICE; slice++) { 451 if (slice_to_memnode[slice] == -1) 452 continue; 453 basepfn = (uint64_t)slice << PFN_SLICE_SHIFT; 454 mem_node_add_slice(basepfn, basepfn + npgs - 1); 455 } 456 } 457 458 459 460 /* 461 * Cherrystone support for lgroups. 462 * 463 * On Cherrystone, an lgroup platform handle == slot number. 464 * 465 * Mappings between lgroup handles and memnodes are managed 466 * in addition to mappings between memory slices and memnodes 467 * to support cross-board interleaving as well as multiple 468 * slices per board (e.g. >1GB DIMMs). The initial mapping 469 * of memnodes to lgroup handles is determined at boot time. 470 */ 471 472 int 473 plat_pfn_to_mem_node(pfn_t pfn) 474 { 475 return (slice_to_memnode[PFN_2_SLICE(pfn)]); 476 } 477 478 /* 479 * Return the platform handle for the lgroup containing the given CPU 480 * 481 * For Cherrystone, lgroup platform handle == slot/board number 482 */ 483 lgrp_handle_t 484 plat_lgrp_cpu_to_hand(processorid_t id) 485 { 486 return (CHERRYSTONE_GETSLOT(id)); 487 } 488 489 /* 490 * Platform specific lgroup initialization 491 */ 492 void 493 plat_lgrp_init(void) 494 { 495 int i; 496 497 /* 498 * Initialize lookup tables to invalid values so we catch 499 * any illegal use of them. 500 */ 501 for (i = 0; i < CHERRYSTONE_MAX_SLICE; i++) { 502 slice_to_memnode[i] = -1; 503 } 504 } 505 506 /* 507 * Return latency between "from" and "to" lgroups 508 * 509 * This latency number can only be used for relative comparison 510 * between lgroups on the running system, cannot be used across platforms, 511 * and may not reflect the actual latency. It is platform and implementation 512 * specific, so platform gets to decide its value. It would be nice if the 513 * number was at least proportional to make comparisons more meaningful though. 514 * NOTE: The numbers below are supposed to be load latencies for uncached 515 * memory divided by 10. 516 */ 517 int 518 plat_lgrp_latency(lgrp_handle_t from, lgrp_handle_t to) 519 { 520 /* 521 * Return min remote latency when there are more than two lgroups 522 * (root and child) and getting latency between two different lgroups 523 * or root is involved 524 */ 525 if (lgrp_optimizations() && (from != to || 526 from == LGRP_DEFAULT_HANDLE || to == LGRP_DEFAULT_HANDLE)) 527 return (21); 528 else 529 return (19); 530 } 531 532 /* 533 * No platform drivers on this platform 534 */ 535 char *platform_module_list[] = { 536 (char *)0 537 }; 538 539 /*ARGSUSED*/ 540 void 541 plat_tod_fault(enum tod_fault_type tod_bad) 542 { 543 } 544 545 /*ARGSUSED*/ 546 int 547 plat_get_mem_unum(int synd_code, uint64_t flt_addr, int flt_bus_id, 548 int flt_in_memory, ushort_t flt_status, char *buf, int buflen, int *lenp) 549 { 550 if (flt_in_memory && (p2get_mem_unum != NULL)) 551 return (p2get_mem_unum(synd_code, P2ALIGN(flt_addr, 8), 552 buf, buflen, lenp)); 553 else 554 return (ENOTSUP); 555 } 556 557 /* 558 * This platform hook gets called from mc_add_mem_unum_label() in the mc-us3 559 * driver giving each platform the opportunity to add platform 560 * specific label information to the unum for ECC error logging purposes. 561 */ 562 void 563 plat_add_mem_unum_label(char *unum, int mcid, int bank, int dimm) 564 { 565 _NOTE(ARGUNUSED(bank, dimm)) 566 567 char board = CHERRYSTONE_GETSLOT_LABEL(mcid); 568 char old_unum[UNUM_NAMLEN]; 569 570 strcpy(old_unum, unum); 571 snprintf(unum, UNUM_NAMLEN, "Slot %c: %s", board, old_unum); 572 } 573 574 int 575 plat_get_cpu_unum(int cpuid, char *buf, int buflen, int *lenp) 576 { 577 char board = CHERRYSTONE_GETSLOT_LABEL(cpuid); 578 579 if (snprintf(buf, buflen, "Slot %c", board) >= buflen) { 580 return (ENOSPC); 581 } else { 582 *lenp = strlen(buf); 583 return (0); 584 } 585 } 586 587 /* 588 * Cherrystone's BBC pcf8584 controller is used by both OBP and the OS's i2c 589 * drivers. The 'eeprom' command executes OBP code to handle property requests. 590 * If eeprom didn't do this, or if the controllers were partitioned so that all 591 * devices on a given controller were driven by either OBP or the OS, this 592 * wouldn't be necessary. 593 * 594 * Note that getprop doesn't have the same issue as it reads from cached 595 * memory in OBP. 596 */ 597 598 /* 599 * Common locking enter code 600 */ 601 void 602 plat_setprop_enter(void) 603 { 604 mutex_enter(&cherry_pcf8584_mutex); 605 } 606 607 /* 608 * Common locking exit code 609 */ 610 void 611 plat_setprop_exit(void) 612 { 613 mutex_exit(&cherry_pcf8584_mutex); 614 } 615 616 /* 617 * Called by pcf8584 driver 618 */ 619 void 620 plat_shared_i2c_enter(dev_info_t *i2cnexus_dip) 621 { 622 if (i2cnexus_dip == shared_pcf8584_dip) { 623 plat_setprop_enter(); 624 } 625 } 626 627 /* 628 * Called by pcf8584 driver 629 */ 630 void 631 plat_shared_i2c_exit(dev_info_t *i2cnexus_dip) 632 { 633 if (i2cnexus_dip == shared_pcf8584_dip) { 634 plat_setprop_exit(); 635 } 636 } 637