1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_IVINTR_H 27 #define _SYS_IVINTR_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /* Software interrupt and other bit flags */ 36 #define IV_SOFTINT_PEND 0x1 /* Software interrupt is pending */ 37 #define IV_SOFTINT_MT 0x2 /* Multi target software interrupt */ 38 #define IV_CACHE_ALLOC 0x4 /* Allocated using kmem_cache_alloc() */ 39 40 /* 41 * Reserve some interrupt vector data structures for the hardware and software 42 * interrupts. 43 * 44 * NOTE: Need two single target software interrupts per cpu for cyclics. 45 * Need one single target software interrupt per cpu for tick accounting. 46 */ 47 #define MAX_RSVD_IV ((NCPU * 3) + 256) /* HW and Single target SW intrs */ 48 #define MAX_RSVD_IVX 32 /* Multi target software intrs */ 49 50 #ifndef _ASM 51 52 typedef uint_t (*intrfunc)(caddr_t, caddr_t); 53 typedef uint_t (*softintrfunc)(caddr_t, caddr_t); 54 typedef struct intr_vec intr_vec_t; 55 typedef struct intr_vecx intr_vecx_t; 56 57 /* Software interrupt type */ 58 typedef enum softint_type { 59 SOFTINT_ST = (ushort_t)0, /* Single target */ 60 SOFTINT_MT = (ushort_t)1 /* Multi target */ 61 } softint_type_t; 62 63 /* 64 * Interrupt Vector Structure. 65 * 66 * Interrupt vector structure is allocated either from the reserved pool or 67 * dynamically using kmem cache method. For the hardware interrupts, one per 68 * vector with unique pil basis, i.e, interrupts sharing the same ino and the 69 * same pil do share the same structure. 70 * 71 * Used by Hardware and Single target Software interrupts. 72 */ 73 struct intr_vec { 74 ushort_t iv_inum; /* MDB: interrupt mondo number */ 75 ushort_t iv_pil; /* Interrupt priority level */ 76 ushort_t iv_flags; /* SW interrupt and other bit flags */ 77 uint8_t iv_pad[10]; /* Align on cache line boundary */ 78 79 intrfunc iv_handler; /* ISR */ 80 caddr_t iv_arg1; /* ISR arg1 */ 81 caddr_t iv_arg2; /* ISR arg2 */ 82 caddr_t iv_payload_buf; /* Sun4v: mondo payload, epkt */ 83 84 intr_vec_t *iv_vec_next; /* Per vector list */ 85 intr_vec_t *iv_pil_next; /* Per PIL list */ 86 }; 87 88 /* 89 * Extended version of Interrupt Vector Structure. 90 * 91 * Used by Multi target Software interrupts. 92 */ 93 struct intr_vecx { 94 intr_vec_t iv_vec; /* CPU0 uses iv_pil_next */ 95 intr_vec_t *iv_pil_xnext[NCPU -1]; /* For CPU1 through N-1 */ 96 }; 97 98 #define IV_GET_PIL_NEXT(iv_p, cpu_id) \ 99 (((iv_p->iv_flags & IV_SOFTINT_MT) && (cpu_id != 0)) ? \ 100 ((intr_vecx_t *)iv_p)->iv_pil_xnext[cpu_id - 1] : iv_p->iv_pil_next) 101 #define IV_SET_PIL_NEXT(iv_p, cpu_id, next) \ 102 (((iv_p->iv_flags & IV_SOFTINT_MT) && (cpu_id != 0)) ? \ 103 (((intr_vecx_t *)iv_p)->iv_pil_xnext[cpu_id - 1] = next) : \ 104 (iv_p->iv_pil_next = next)) 105 106 extern uint64_t intr_vec_table[]; 107 108 extern void init_ivintr(void); 109 extern void fini_ivintr(void); 110 111 extern int add_ivintr(uint_t inum, uint_t pil, intrfunc intr_handler, 112 caddr_t intr_arg1, caddr_t intr_arg2, caddr_t intr_payload); 113 extern int rem_ivintr(uint_t inum, uint_t pil); 114 115 extern uint64_t add_softintr(uint_t pil, softintrfunc intr_handler, 116 caddr_t intr_arg1, softint_type_t type); 117 extern int rem_softintr(uint64_t softint_id); 118 extern int update_softint_arg2(uint64_t softint_id, caddr_t intr_arg2); 119 extern int update_softint_pri(uint64_t softint_id, uint_t pil); 120 121 #endif /* !_ASM */ 122 123 #ifdef __cplusplus 124 } 125 #endif 126 127 #endif /* _SYS_IVINTR_H */ 128