1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_INTREG_H 27 #define _SYS_INTREG_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #include <sys/machintreg.h> 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 #define INO_SIZE 6 /* Interrupt Number Offset bit size */ 38 #define INR_SIZE (IGN_SIZE + INO_SIZE) /* Interrupt Number bit size */ 39 #define MAX_IGN (1 << IGN_SIZE) /* Max Interrupt Group Number size */ 40 #define MAX_INO (1 << INO_SIZE) /* Max Interrupt Number per group */ 41 #define MAXIVNUM (MAX_IGN * MAX_INO) /* Max hardware intrs allowed */ 42 43 /* 44 * Interrupt State Machine 45 * Each interrupt source has a 2-bit state machine which ensures that 46 * software sees exactly one interrupt packet per assertion of the 47 * interrupt signal. 48 */ 49 #define ISM_IDLE 0x0 /* not asserted or pending */ 50 #define ISM_TRANSMIT 0x1 /* asserted but is not dispatched */ 51 #define ISM_PENDING 0x2 /* dispatched to a processor or is in transit */ 52 53 /* 54 * Per-Processor Soft Interrupt Register 55 * XXX use %asr when the new assembler supports them 56 */ 57 #define SET_SOFTINT %asr20 /* ASR 0x14 */ 58 #define CLEAR_SOFTINT %asr21 /* ASR 0x15 */ 59 #define SOFTINT %asr22 /* ASR 0x16 */ 60 #define SOFTINT_MASK 0xFFFE /* <15:1> */ 61 #define TICK_INT_MASK 0x1 /* <0> */ 62 #define STICK_INT_MASK 0x10000 /* <0> */ 63 64 /* 65 * Per-Processor TICK Register and TICK_Compare registers 66 * 67 */ 68 #define TICK_COMPARE %asr23 /* ASR 0x17 */ 69 #define STICK %asr24 /* ASR 0x18 */ 70 #define STICK_COMPARE %asr25 /* ASR 0x19 */ 71 #define TICKINT_DIS_SHFT 0x3f 72 73 #ifndef _ASM 74 75 /* 76 * Interrupt Packet (mondo) 77 */ 78 struct intr_packet { 79 uint64_t intr_data0; /* can be an interrupt number or a pc */ 80 uint64_t intr_data1; 81 uint64_t intr_data2; 82 }; 83 84 /* 85 * Leftover bogus stuff; removed them later 86 */ 87 struct cpu_intreg { 88 uint_t pend; 89 uint_t clr_pend; 90 uint_t set_pend; 91 uchar_t filler[0x1000 - 0xc]; 92 }; 93 94 struct sys_intreg { 95 uint_t sys_pend; 96 uint_t sys_m; 97 uint_t sys_mclear; 98 uint_t sys_mset; 99 uint_t itr; 100 }; 101 102 #endif /* _ASM */ 103 104 #ifdef __cplusplus 105 } 106 #endif 107 108 #endif /* _SYS_INTREG_H */ 109