1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_INTREG_H 27 #define _SYS_INTREG_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #include <sys/machintreg.h> 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 #define INO_SIZE 6 /* Interrupt Number Offset bit size */ 38 #define INR_SIZE (IGN_SIZE + INO_SIZE) /* Interrupt Number bit size */ 39 #define MAX_IGN (1 << IGN_SIZE) /* Max Interrupt Group Number size */ 40 #define MAX_INO (1 << INO_SIZE) /* Max Interrupt Number per group */ 41 #define MAXDEVINTRS (MAX_IGN * MAX_INO) /* Max hardware intrs allowed */ 42 43 /* 44 * A platform may require use of the system interrupt table beyond 45 * the maximum hardware interrupts specified above for virtual device 46 * interrupts. If the platform does not specify MAXVINTRS we default to 0. 47 */ 48 #ifndef MAXVINTRS 49 #define MAXVINTRS 0 50 #endif 51 52 /* 53 * maximum system interrupts allowed 54 */ 55 #define MAXIVNUM (MAXDEVINTRS + MAXVINTRS) 56 57 /* 58 * Interrupt State Machine 59 * Each interrupt source has a 2-bit state machine which ensures that 60 * software sees exactly one interrupt packet per assertion of the 61 * interrupt signal. 62 */ 63 #define ISM_IDLE 0x0 /* not asserted or pending */ 64 #define ISM_TRANSMIT 0x1 /* asserted but is not dispatched */ 65 #define ISM_PENDING 0x2 /* dispatched to a processor or is in transit */ 66 67 /* 68 * Per-Processor Soft Interrupt Register 69 * XXX use %asr when the new assembler supports them 70 */ 71 #define SET_SOFTINT %asr20 /* ASR 0x14 */ 72 #define CLEAR_SOFTINT %asr21 /* ASR 0x15 */ 73 #define SOFTINT %asr22 /* ASR 0x16 */ 74 #define SOFTINT_MASK 0xFFFE /* <15:1> */ 75 #define TICK_INT_MASK 0x1 /* <0> */ 76 #define STICK_INT_MASK 0x10000 /* <0> */ 77 78 /* 79 * Per-Processor TICK Register and TICK_Compare registers 80 * 81 */ 82 #define TICK_COMPARE %asr23 /* ASR 0x17 */ 83 #define STICK %asr24 /* ASR 0x18 */ 84 #define STICK_COMPARE %asr25 /* ASR 0x19 */ 85 #define TICKINT_DIS_SHFT 0x3f 86 87 #ifndef _ASM 88 89 /* 90 * Interrupt Packet (mondo) 91 */ 92 struct intr_packet { 93 uint64_t intr_data0; /* can be an interrupt number or a pc */ 94 uint64_t intr_data1; 95 uint64_t intr_data2; 96 }; 97 98 /* 99 * Leftover bogus stuff; removed them later 100 */ 101 struct cpu_intreg { 102 uint_t pend; 103 uint_t clr_pend; 104 uint_t set_pend; 105 uchar_t filler[0x1000 - 0xc]; 106 }; 107 108 struct sys_intreg { 109 uint_t sys_pend; 110 uint_t sys_m; 111 uint_t sys_mclear; 112 uint_t sys_mset; 113 uint_t itr; 114 }; 115 116 #endif /* _ASM */ 117 118 #ifdef __cplusplus 119 } 120 #endif 121 122 #endif /* _SYS_INTREG_H */ 123