1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PX_VAR_H 27 #define _SYS_PX_VAR_H 28 29 #include <sys/callb.h> 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /* 36 * offsets of PCI address spaces from base address: 37 */ 38 #define PX_CONFIG 0x001000000ull 39 #define PX_A_IO 0x002000000ull 40 #define PX_B_IO 0x002010000ull 41 #define PX_A_MEMORY 0x100000000ull 42 #define PX_B_MEMORY 0x180000000ull 43 #define PX_IO_SIZE 0x000010000ull 44 #define PX_MEM_SIZE 0x080000000ull 45 46 /* 47 * The following typedef is used to represent a 48 * 1275 "reg" property of a PCI nexus. 49 */ 50 typedef struct px_nexus_regspec { 51 uint64_t phys_addr; 52 uint64_t size; 53 } px_nexus_regspec_t; 54 55 typedef enum { 56 PX_ATTACHED = 1, 57 PX_DETACHED, 58 PX_SUSPENDED 59 } px_state_t; 60 61 enum { PX_INTR_XBC, PX_INTR_PEC, PX_INTR_HOTPLUG }; 62 63 #define PX_ATTACH_RETCODE(obj, op, err) \ 64 ((err) ? (obj) << 8 | (op) << 4 | (err) & 0xf : DDI_SUCCESS) 65 66 /* 67 * px soft state structure: 68 * 69 * Each px node has a px soft state structure. 70 */ 71 struct px { 72 /* 73 * State flags and mutex: 74 */ 75 px_state_t px_state; 76 uint_t px_soft_state; 77 kmutex_t px_mutex; 78 79 /* 80 * Links to other state structures: 81 */ 82 dev_info_t *px_dip; /* devinfo structure */ 83 devhandle_t px_dev_hdl; /* device handle */ 84 px_ib_t *px_ib_p; /* interrupt block */ 85 px_pec_t *px_pec_p; /* PEC block */ 86 px_mmu_t *px_mmu_p; /* IOMMU block */ 87 88 /* 89 * px device node properties: 90 */ 91 pcie_req_id_t px_bdf; 92 pci_bus_range_t px_bus_range; /* "bus-range" */ 93 pci_ranges_t *px_ranges_p; /* "ranges" data & length */ 94 int px_ranges_length; 95 devino_t *px_inos; /* inos from "interrupts" prop */ 96 int px_inos_len; /* "interrupts" length */ 97 98 /* Error handling */ 99 px_fault_t px_fault; 100 px_fault_t px_cb_fault; 101 102 /* FMA */ 103 int px_fm_cap; 104 kmutex_t px_fm_mutex; 105 kthread_t *px_fm_mutex_owner; 106 ddi_iblock_cookie_t px_fm_ibc; 107 pf_data_t px_pfd_arr[5]; 108 int px_pfd_idx; 109 110 uint32_t px_dev_caps; 111 112 /* Platform specific information */ 113 void *px_plat_p; 114 115 /* Power Management fields */ 116 kmutex_t px_l23ready_lock; /* used in PME_To_ACK interrupt */ 117 kcondvar_t px_l23ready_cv; /* used in PME_TO_ACK timeout */ 118 volatile uint32_t px_lup_pending; 119 int px_pm_flags; 120 msiqid_t px_pm_msiq_id; /* EQ id for PCIE_PME_ACK_MSG Message */ 121 uint32_t px_pmetoack_ignored; /* count of PME_To_ACKs ignored */ 122 123 /* CPR callback id */ 124 callb_id_t px_cprcb_id; 125 uint32_t px_dma_sync_opt; /* DMA syncing req. of hw */ 126 127 /* Handle for soft intr */ 128 ddi_softint_handle_t px_dbg_hdl; /* HDL for dbg printing */ 129 }; 130 131 /* px_dev_caps definition */ 132 #define PX_BYPASS_DMA_ALLOWED 1 133 #define PX_DMA_SYNC_REQUIRED 4 134 135 /* px_pm_flags definitions used with interrupts and FMA code */ 136 #define PX_PMETOACK_RECVD 0x01 /* With PME_To_ACK interrupt */ 137 #define PX_PME_TURNOFF_PENDING 0x02 /* With PME_To_ACK interrupt */ 138 #define PX_LDN_EXPECTED 0x04 /* With FMA code */ 139 140 #define DIP_TO_INST(dip) ddi_get_instance(dip) 141 #define INST_TO_STATE(inst) ddi_get_soft_state(px_state_p, inst) 142 #define DIP_TO_STATE(dip) INST_TO_STATE(DIP_TO_INST(dip)) 143 144 #define PX_DEV_TO_SOFTSTATE(dev) ((px_t *)ddi_get_soft_state( \ 145 px_state_p, PCI_MINOR_NUM_TO_INSTANCE(getminor(dev)))) 146 147 extern void *px_state_p; 148 149 /* 150 * function prototypes for bus ops routines: 151 */ 152 extern int 153 px_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp, 154 off_t offset, off_t len, caddr_t *addrp); 155 extern int 156 px_dma_setup(dev_info_t *dip, dev_info_t *rdip, 157 ddi_dma_req_t *dmareq, ddi_dma_handle_t *handlep); 158 extern int 159 px_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_attr_t *attrp, 160 int (*waitfp)(caddr_t), caddr_t arg, ddi_dma_handle_t *handlep); 161 extern int 162 px_dma_bindhdl(dev_info_t *dip, dev_info_t *rdip, 163 ddi_dma_handle_t handle, ddi_dma_req_t *dmareq, 164 ddi_dma_cookie_t *cookiep, uint_t *ccountp); 165 extern int 166 px_dma_unbindhdl(dev_info_t *dip, dev_info_t *rdip, 167 ddi_dma_handle_t handle); 168 extern int 169 px_dma_ctlops(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 170 enum ddi_dma_ctlops cmd, off_t *offp, size_t *lenp, caddr_t *objp, 171 uint_t cache_flags); 172 extern int 173 px_ctlops(dev_info_t *dip, dev_info_t *rdip, 174 ddi_ctl_enum_t op, void *arg, void *result); 175 extern int 176 px_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 177 ddi_intr_handle_impl_t *handle, void *result); 178 179 #ifdef __cplusplus 180 } 181 #endif 182 183 #endif /* _SYS_PX_VAR_H */ 184