1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PX_MMU_H 27 #define _SYS_PX_MMU_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <sys/vmem.h> 36 37 typedef uint64_t px_dvma_addr_t; 38 typedef uint64_t px_dma_bypass_addr_t; 39 typedef uint64_t px_dma_peer_addr_t; 40 typedef uint16_t px_dvma_context_t; 41 typedef uint64_t px_window_t; 42 43 /* 44 * boiler plate for tte (everything except the pfn) 45 */ 46 #define PX_GET_TTE_ATTR(flags, attr)\ 47 (((flags & DDI_DMA_READ) ? PCI_MAP_ATTR_WRITE : 0) | \ 48 ((flags & DDI_DMA_WRITE) ? PCI_MAP_ATTR_READ : 0) | \ 49 ((attr & DDI_DMA_RELAXED_ORDERING) ? PCI_MAP_ATTR_RO : 0)) 50 51 /* 52 * mmu block soft state structure: 53 * 54 * Each px node may share an mmu block structure with its peer 55 * node of have its own private mmu block structure. 56 */ 57 typedef struct px_mmu { 58 px_t *mmu_px_p; /* link back to px soft state */ 59 int mmu_inst; 60 61 /* 62 * address ranges of dvma space: 63 */ 64 px_dvma_addr_t mmu_dvma_base; 65 px_dvma_addr_t mmu_dvma_end; 66 px_dvma_addr_t mmu_dvma_fast_end; 67 px_dvma_addr_t dvma_base_pg; /* = MMU_BTOP(mmu_dvma_base) */ 68 px_dvma_addr_t dvma_end_pg; /* = MMU_BTOP(mmu_dvma_end) */ 69 70 /* 71 * virtual memory map and callback id for dvma space: 72 */ 73 vmem_t *mmu_dvma_map; 74 uintptr_t mmu_dvma_clid; 75 76 /* 77 * fields for fast dvma interfaces: 78 */ 79 ulong_t mmu_dvma_reserve; 80 81 /* 82 * dvma fast track page cache byte map 83 */ 84 uint8_t *mmu_dvma_cache_locks; 85 uint_t mmu_dvma_addr_scan_start; 86 87 /* dvma debug */ 88 kmutex_t dvma_debug_lock; 89 uint32_t dvma_alloc_rec_index; 90 uint32_t dvma_free_rec_index; 91 uint32_t dvma_active_count; 92 93 struct px_dvma_rec *dvma_alloc_rec; 94 struct px_dvma_rec *dvma_free_rec; 95 struct px_dvma_rec *dvma_active_list; 96 } px_mmu_t; 97 98 typedef struct px_dvma_range_prop { 99 uint32_t dvma_base; 100 uint32_t dvma_len; 101 } px_dvma_range_prop_t; 102 103 #define MMU_PAGE_INDEX(mmu_p, dvma_pg) ((dvma_pg) - (mmu_p)->dvma_base_pg) 104 105 /* dvma debug */ 106 #define PX_DVMA_DBG_ON(mmu_p) \ 107 ((1ull << (mmu_p)->mmu_inst) & px_dvma_debug_on) 108 #define PX_DVMA_DBG_OFF(mmu_p) \ 109 ((1ull << (mmu_p)->mmu_inst) & px_dvma_debug_off) 110 111 extern void px_dvma_debug_fini(px_mmu_t *mmu_p); 112 extern void px_dvma_alloc_debug(px_mmu_t *mmu_p, char *address, uint_t len, 113 ddi_dma_impl_t *mp); 114 extern void px_dvma_free_debug(px_mmu_t *mmu_p, char *address, uint_t len, 115 ddi_dma_impl_t *mp); 116 117 /* DVMA routines */ 118 extern int px_mmu_map_pages(px_mmu_t *mmu_p, ddi_dma_impl_t *mp, 119 px_dvma_addr_t dvma_pg, size_t npages, size_t pfn_index); 120 extern int px_mmu_map_window(px_mmu_t *mmu_p, ddi_dma_impl_t *mp, 121 px_window_t window); 122 extern void px_mmu_unmap_pages(px_mmu_t *mmu_p, ddi_dma_impl_t *mp, 123 px_dvma_addr_t dvma_pg, uint_t npages); 124 extern void px_mmu_unmap_window(px_mmu_t *mmu_p, ddi_dma_impl_t *mp); 125 126 /* MMU initialization routines */ 127 extern int px_mmu_attach(px_t *px_p); 128 extern void px_mmu_detach(px_t *px_p); 129 130 #ifdef __cplusplus 131 } 132 #endif 133 134 #endif /* _SYS_PX_MMU_H */ 135