1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PX_IOAPI_H 27 #define _SYS_PX_IOAPI_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #ifndef _ASM 34 35 /* 36 * SUN4V IO Data Definitions 37 * 38 * cpuid - A unique opaque value which represents a target cpu. 39 * 40 * devhandle - Device handle. The device handle uniquely 41 * identifies a SUN4V device. It consists of the 42 * the lower 28-bits of the hi-cell of the first 43 * entry of the SUN4V device's "reg" property as defined 44 * by the SUN4V Bus Binding to Open Firmware. 45 * 46 * devino - Device Interrupt Number. An unsigned integer representing 47 * an interrupt within a specific device. 48 * 49 * sysino - System Interrupt Number. A 64-bit unsigned integer 50 * representing a unique interrupt within a "system". 51 * 52 * intr_state - A flag representing the interrupt state for a 53 * a given sysino. The state values are defined as: 54 * 55 * INTR_IDLE 0 56 * INTR_RECEIVED 1 57 * INTR_DELIVERED 2 58 * 59 * intr_valid_state - A flag representing the 'valid' state for 60 * a given sysino. The state values are defined as: 61 * 62 * INTR_NOTVALID 0 sysino not enabled 63 * INTR_VALID 1 sysino enabled 64 */ 65 66 typedef uint64_t devhandle_t; 67 68 typedef uint32_t cpuid_t; 69 typedef uint32_t devino_t; 70 typedef uint64_t sysino_t; 71 72 typedef enum intr_state { 73 INTR_IDLE_STATE = (uint32_t)0, 74 INTR_RECEIVED_STATE = (uint32_t)1, 75 INTR_DELIVERED_STATE = (uint32_t)2 76 } intr_state_t; 77 78 typedef enum intr_valid_state { 79 INTR_NOTVALID = (uint32_t)0, 80 INTR_VALID = (uint32_t)1 81 } intr_valid_state_t; 82 83 /* 84 * PCI IO Data Definitions 85 * 86 * tsbnum - TSB Number. Identifies which io-tsb is used. 87 * For this version of the spec, tsbnum must be zero. 88 * 89 * tsbindex - TSB Index. Identifies which entry in the tsb is 90 * is used. The first entry is zero. 91 * 92 * tsbid - A 64-bit aligned data structure which contains 93 * a tsbnum and a tsbindex. 94 * bits 63:32 contain the tsbnum. 95 * bits 31:00 contain the tsbindex. 96 * 97 * io_attributes - IO Attributes for iommu mappings. 98 * Attributes for iommu mappings. One or more of the 99 * following attribute bits stored in a 64-bit unsigned int. 100 * 101 * 6 3 0 102 * 3 1 0 103 * 00000000 00000000 00000000 00000000 BBBBBBBB DDDDDFFF 00000000 00PP0LWR 104 * 105 * R: DMA data is transferred from main memory to device. 106 * W: DMA data is transferred from device to main memory. 107 * L: Requested DMA transaction can be relaxed ordered within RC. 108 * P: Value of PCI Express and PCI-X phantom function 109 * configuration. Its encoding is identical to the 110 * "Phantom Function Supported" field of the 111 * "Device Capabilities Register (offset 0x4)" 112 * in the "PCI Express Capability Structure". 113 * The structure is part of a device's config space. 114 * BDF: Bus, device and function number of the device 115 * that is going to issue DMA transactions. 116 * The BDF values are used to guarantee the mapping 117 * only be accessed by the specified device. 118 * If the BDF is set to all 0, RID based protection 119 * will be turned off. 120 * 121 * Relaxed Ordering (L) is advisory. Not all hardware implements a 122 * relaxed ordering attribute. If L attribute is not implemented in 123 * hardware, the implementation is permitted to ignore the L bit. 124 * 125 * Bits 3, 15:6 and 63:32 are unused and must be set to zero for 126 * this version of the specification. 127 * 128 * Note: For compatibility with future versions of this 129 * specification, the caller must set bits 3, 15:6 and 63:32 to 130 * zero. The implementation shall ignore these bits. 131 * 132 * r_addr - 64-bit Real Address. 133 * 134 * io_addr - 64-bit IO Address. 135 * 136 * pci_device - PCI device address. A PCI device address 137 * identifies a specific device on a specific PCI 138 * bus segment. A PCI device address is a 32-bit unsigned 139 * integer with the following format: 140 * 141 * 00000000.bbbbbbbb.dddddfff.00000000 142 * 143 * Where: 144 * 145 * bbbbbbbb is the 8-bit pci bus number 146 * ddddd is the 5-bit pci device number 147 * fff is the 3-bit pci function number 148 * 149 * 00000000 is the 8-bit literal zero. 150 * 151 * pci_config_offset - PCI Configuration Space offset. 152 * 153 * For conventional PCI, an unsigned integer in the range 154 * 0 .. 255 representing the offset of the field in pci config 155 * space. 156 * 157 * For PCI implementations with extended configuration space, 158 * an unsigned integer in the range 0 .. 4095, representing 159 * the offset of the field in configuration space. Conventional 160 * PCI config space is offset 0 .. 255. Extended config space 161 * is offset 256 .. 4095 162 * 163 * Note: For pci config space accesses, the offset must be 'size' 164 * aligned. 165 * 166 * error_flag - Error flag 167 * 168 * A return value specifies if the action succeeded 169 * or failed, where: 170 * 171 * 0 - No error occurred while performing the service. 172 * non-zero - Error occurred while performing the service. 173 * 174 * io_sync_direction - "direction" definition for pci_dma_sync 175 * 176 * A value specifying the direction for a memory/io sync 177 * operation, The direction value is a flag, one or both 178 * directions may be specified by the caller. 179 * 180 * 0x01 - For device (device read from memory) 181 * 0x02 - For cpu (device write to memory) 182 * 183 * io_page_list - A list of io_page_addresses. An io_page_address 184 * is an r_addr. 185 * 186 * io_page_list_p - A pointer to an io_page_list. 187 */ 188 typedef uint32_t tsbnum_t; 189 typedef uint32_t tsbindex_t; 190 typedef uint64_t tsbid_t; 191 typedef uint64_t r_addr_t; 192 typedef uint64_t io_addr_t; 193 typedef uint64_t io_page_list_t; 194 typedef uint32_t pages_t; 195 typedef uint32_t error_flag_t; 196 197 typedef uint32_t pci_config_offset_t; 198 typedef uint64_t pci_device_t; 199 200 #define PCI_TSB_INDEX 0 201 #define PCI_TSB_INDEX_MASK 0xFFFFFFFF 202 #define PCI_TSB_NUM 32 203 #define PCI_TSB_NUM_MASK 0xFFFFFFFF 204 205 #define PCI_TSBID(tsbnum, tsbindex) \ 206 ((((tsbid_t)tsbnum & PCI_TSB_NUM_MASK) << PCI_TSB_NUM) | \ 207 (((tsbid_t)tsbindex & PCI_TSB_INDEX_MASK) << PCI_TSB_INDEX)) 208 209 #define PCI_TSBID_TO_TSBNUM(tsbid) \ 210 ((tsbid >> PCI_TSB_NUM) & PCI_TSB_NUM_MASK) 211 212 #define PCI_TSBID_TO_TSBINDEX(tsbid) \ 213 ((tsbid >> PCI_TSB_INDEX) & PCI_TSB_INDEX_MASK) 214 215 typedef uint64_t io_attributes_t; 216 217 #define PCI_MAP_ATTR_READ 0x1ull 218 #define PCI_MAP_ATTR_WRITE 0x2ull 219 #define PCI_MAP_ATTR_RO 0x4ull 220 221 #define PCI_MAP_ATTR_PHFUN 4 222 #define PCI_MAP_ATTR_BDF 16 223 224 #define PCI_MAP_ATTR_PHFUN_MASK 0x30 225 #define PCI_MAP_ATTR_BDF_MASK 0xffff0000 226 227 #define PX_ADD_ATTR_EXTNS(attr, bdf) \ 228 (attr | (bdf << PCI_MAP_ATTR_BDF)) 229 230 typedef enum io_sync_direction { 231 IO_SYNC_DEVICE = (uint32_t)0x01, 232 IO_SYNC_CPU = (uint32_t)0x02 233 } io_sync_direction_t; 234 235 typedef enum pci_config_size { 236 PCI_CFG_SIZE_BYTE = 0, 237 PCI_CFG_SIZE_WORD, 238 PCI_CFG_SIZE_DWORD 239 } pci_config_size_t; 240 241 typedef union pci_cfg_data { 242 uint8_t b; 243 uint16_t w; 244 uint32_t dw; 245 uint64_t qw; 246 } pci_cfg_data_t; 247 248 /* 249 * MSI Definitions 250 * 251 * MSI - Message Signaled Interrupt 252 * 253 * Message Signaled Interrupt as defined in the PCI Local Bus 254 * Specification and the PCI Express Base Specification. 255 * A device signals an interrupt via MSI using a posted 256 * write cycle to an address specified by system software 257 * using a data value specified by system software. 258 * The MSI capability data structure contains fields for 259 * the PCI address and data values the device uses when 260 * sending an MSI message on the bus. MSI-X is an extended 261 * form of MSI, but uses the same mechanism for signaling 262 * the interrupt as MSI. For the purposes of this document, 263 * the term "MSI" refers to MSI or MSI-X. 264 * 265 * Root complexes that support MSI define an address range 266 * and set of data values that can be used to signal MSIs. 267 * 268 * SUN4V/pci requirements for MSI: 269 * 270 * The root complex defines two address ranges. One in 271 * the 32-bit pci memory space and one in the 64-bit 272 * pci memory address space used as the target of a posted 273 * write to signal an MSI. 274 * 275 * The root complex treats any write to these address 276 * ranges as signaling an MSI, however, only the data 277 * value used in the posted write signals the MSI. 278 * 279 * 280 * MSI EQ - MSI Event Queue 281 * 282 * The MSI Event Queue is a page-aligned main memory data 283 * structure used to store MSI data records. 284 * 285 * Each root port supports several MSI EQs, and each EQ has a 286 * system interrupt associated with it, and can be targeted 287 * (individually) to any cpu. The number of MSI EQs supported 288 * by a root complex is described by a property defined in [3]. 289 * Each MSI EQ must be large enough to contain all possible MSI 290 * data records generated by any one PCI root port. The number 291 * of entries in each MSI EQ is described by a property defined 292 * in [3]. 293 * 294 * Each MSI EQ is compliant with the definition of interrupt 295 * queues described in [5], however, instead of accessing the 296 * queue head/tail registers via ASI-based registers, an API 297 * is provided to access the head/tail registers. 298 * 299 * The SUN4V/pci compliant root complex has the ability to 300 * generate a system interrupt when the MSI EQ is non-empty. 301 * 302 * MSI/Message/INTx Data Record format 303 * 304 * Each data record consists of 64 bytes of data, aligned 305 * on a 64-byte boundary. 306 * 307 * The data record is defined as follows: 308 * 309 * 310 * 6666555555555544444444443333333333222222222211111111110000000000 311 * 3210987654321098765432109876543210987654321098765432109876543210 312 * 313 * 0x00: VVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVxxxxxxxxxxxxxxxxxxxxxxxxTTTTTTTT 314 * 0x08: IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII 315 * 0x10: xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 316 * 0x18: SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS 317 * 0x20: xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxRRRRRRRRRRRRRRRR 318 * 0x28: AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 319 * 0x30: DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 320 * 0x38: xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 321 * 322 * Where, 323 * 324 * xx..xx are unused bits and must be ignored by sw. 325 * 326 * VV..VV is the version number of this data record 327 * 328 * For this release of the spec, the version number 329 * field must be zero. 330 * 331 * TTTTTTTT is the data record type: 332 * 333 * Upper 4 bits are reserved, and must be zero 334 * 335 * 0000 - Not an MSI data record - reserved for sw use. 336 * 0001 - MSG 337 * 0010 - MSI32 338 * 0011 - MSI64 339 * 0010 - Reserved 340 * ... 341 * 0111 - Reserved 342 * 1000 - INTx 343 * 1001 - Reserved 344 * ... 345 * 1110 - Reserved 346 * 1111 - Not an MSI data record - reserved for sw use. 347 * 348 * All other encodings are reserved. 349 * 350 * II..II is the sysino for INTx (sw defined value), 351 * otherwise zero. 352 * 353 * SS..SS is the message timestamp if available. 354 * If supported by the implementation, a non-zero 355 * value in this field is a copy of the %stick register 356 * at the time the message is created. 357 * 358 * If unsupported, this field will contain zero. 359 * 360 * RR..RR is the requester ID of the device that initiated the MSI/MSG 361 * and has the following format: 362 * 363 * bbbbbbbb.dddddfff 364 * 365 * Where bb..bb is the bus number, 366 * dd..dd is the device number 367 * and fff is the function number. 368 * 369 * Note that for PCI devices or any message where 370 * the requester is unknown, this may be zero, 371 * or the device-id of an intermediate bridge. 372 * 373 * For intx messages, this field should be ignored. 374 * 375 * AA..AA is the MSI address. For MSI32, the upper 32-bits must be zero. 376 * (for data record type MSG or INTx, this field is ignored) 377 * 378 * DD..DD is the MSI/MSG data or INTx number 379 * 380 * For MSI-X, bits 31..0 contain the data from the MSI packet 381 * which is the msi-number. bits 63..32 shall be zero. 382 * 383 * For MSI, bits 15..0 contain the data from the MSI message 384 * which is the msi-number. bits 63..16 shall be zero 385 * 386 * For MSG data, the message code and message routing code 387 * are encoded as follows: 388 * 389 * 63:32 - 0000.0000.0000.0000.0000.0000.GGGG.GGGG 390 * 32:00 - 0000.0000.0000.0CCC.0000.0000.MMMM.MMMM 391 * 392 * Where, 393 * 394 * GG..GG is the target-id of the message in the 395 * following form: 396 * 397 * bbbbbbbb.dddddfff 398 * 399 * where bb..bb is the target bus number. 400 * ddddd is the target deviceid 401 * fff is the target function number. 402 * 403 * CCC is the message routing code as defined by [4] 404 * 405 * MM..MM is the message code as defined by [4] 406 * 407 * For INTx data, bits 63:2 must be zero and 408 * the low order 2 bits are defined as follows: 409 * 410 * 00 - INTA 411 * 01 - INTB 412 * 10 - INTC 413 * 11 - INTD 414 * 415 * cpuid - A unique opaque value which represents a target cpu. 416 * 417 * devhandle - Device handle. The device handle uniquely identifies a 418 * SUN4V device. It consists of the the lower 28-bits of the hi-cell 419 * of the first entry of the SUN4V device's "reg" property as defined 420 * by the SUN4V Bus Binding to Open Firmware. 421 * 422 * msinum - A value defining which MSI is being used. 423 * 424 * msiqhead - The index value of the current head index for a given 425 * MSI-EQ. 426 * 427 * msiqtail - The index value of the current tail index for a given 428 * MSI-EQ. 429 * 430 * msitype - Type specifier for MSI32 or MSI64 431 * 0 - type is MSI32 432 * 1 - type is MSI64 433 * 434 * msiqid - A number from 0 .. 'number of MSI-EQs - 1', defining 435 * which MSI EQ within the device is being used. 436 * 437 * msiqstate - An unsigned integer containing one of the 438 * following values: 439 * 440 * PCI_MSIQSTATE_IDLE 0 # idle (non-error) state 441 * PCI_MSIQSTATE_ERROR 1 # error state 442 * 443 * msiqvalid - An unsigned integer containing one of the 444 * following values: 445 * 446 * PCI_MSIQ_INVALID 0 # disabled/invalid 447 * PCI_MSIQ_VALID 1 # enabled/valid 448 * 449 * msistate - An unsigned integer containing one of the following 450 * values: 451 * 452 * PCI_MSISTATE_IDLE 0 # idle/not enabled 453 * PCI_MSISTATE_DELIVERED 1 # MSI Delivered 454 * 455 * msivalid - An unsigned integer containing one of the 456 * following values: 457 * 458 * PCI_MSI_INVALID 0 # disabled/invalid 459 * PCI_MSI_VALID 1 # enabled/valid 460 * 461 * msgtype - A value defining which MSG type is being used. An unsigned 462 * integer containing one of the following values: 463 * (as per PCIe spec 1.0a) 464 * 465 * PCIE_PME_MSG 0x18 PME message 466 * PCIE_PME_ACK_MSG 0x1b PME ACK message 467 * PCIE_CORR_MSG 0x30 Correctable message 468 * PCIE_NONFATAL_MSG 0x31 Non fatal message 469 * PCIE_FATAL_MSG 0x33 Fatal message 470 */ 471 472 typedef uint32_t msinum_t; 473 typedef uint32_t msiqid_t; 474 typedef uint32_t msgcode_t; 475 typedef uint64_t msiqhead_t; 476 typedef uint64_t msiqtail_t; 477 478 /* MSIQ state */ 479 typedef enum pci_msiq_state { 480 PCI_MSIQ_STATE_IDLE = (uint32_t)0, /* idle (non-error) state */ 481 PCI_MSIQ_STATE_ERROR = (uint32_t)1 /* error state */ 482 } pci_msiq_state_t; 483 484 /* MSIQ valid */ 485 typedef enum pci_msiq_valid_state { 486 PCI_MSIQ_INVALID = (uint32_t)0, /* disabled/invalid */ 487 PCI_MSIQ_VALID = (uint32_t)1 /* enabled/valid */ 488 } pci_msiq_valid_state_t; 489 490 /* MSIQ Record data structure */ 491 typedef struct msiq_rec { 492 uint64_t msiq_rec_version : 32, /* DW 0 - 63:32 */ 493 msiq_rec_rsvd0 : 24, /* DW 0 - 31:09 */ 494 msiq_rec_type : 8; /* DW 0 - 07:00 */ 495 uint64_t msiq_rec_intx; /* DW 1 */ 496 uint64_t msiq_rec_rsvd1; /* DW 2 */ 497 uint64_t msiq_rec_timestamp; /* DW 3 */ 498 uint64_t msiq_rec_rsvd2 : 48, /* DW 4 - 63:16 */ 499 msiq_rec_rid : 16; /* DW 4 - 15:00 */ 500 uint64_t msiq_rec_msi_addr; /* DW 5 - 63:00 */ 501 union { 502 struct { 503 uint64_t msix_rsvd0 : 32, /* DW 6 - 63:32 */ 504 msix_data : 32; /* DW 6 - 31:00 */ 505 } msix; 506 struct { 507 uint64_t msi_rsvd0 : 48, /* DW 6 - 63:16 */ 508 msi_data: 16; /* DW 6 - 15:00 */ 509 } msi; 510 struct { 511 uint64_t msg_rsvd0: 24, /* DW 6 - 63:40 */ 512 msg_targ: 8, /* DW 6 - 39:32 */ 513 msg_rsvd1: 13, /* DW 6 - 31:19 */ 514 msg_route: 3, /* DW 6 - 18:16 */ 515 msg_rsvd2: 8, /* DW 6 - 15:08 */ 516 msg_code: 8; /* DW 6 - 07:00 */ 517 } msg; 518 } msiq_rec_data; 519 uint64_t msiq_rec_rsvd3; /* DW 7 */ 520 } msiq_rec_t; 521 522 /* MSIQ Record type */ 523 typedef enum msiq_rec_type { 524 MSG_REC = (uint32_t)1, /* PCIe message record */ 525 MSI32_REC = (uint32_t)2, /* MSI32 record */ 526 MSI64_REC = (uint32_t)3, /* MSI64 record */ 527 INTX_REC = (uint32_t)8 /* INTx record */ 528 } msiq_rec_type_t; 529 530 /* MSIQ Record type */ 531 typedef enum msi_type { 532 MSI32_TYPE = (uint32_t)0, /* MSI32 type */ 533 MSI64_TYPE = (uint32_t)1 /* MSI64 type */ 534 } msi_type_t; 535 536 /* MSI state */ 537 typedef enum pci_msi_state { 538 PCI_MSI_STATE_IDLE = (uint32_t)0, /* idle/not enabled */ 539 PCI_MSI_STATE_DELIVERED = (uint32_t)1 /* MSI delivered */ 540 } pci_msi_state_t; 541 542 /* MSI valid */ 543 typedef enum pci_msi_valid_state { 544 PCI_MSI_INVALID = (uint32_t)0, /* disabled/invalid */ 545 PCI_MSI_VALID = (uint32_t)1 /* enabled/valid */ 546 } pci_msi_valid_state_t; 547 548 /* MSG valid */ 549 typedef enum pcie_msg_valid_state { 550 PCIE_MSG_INVALID = (uint32_t)0, /* disabled/invalid */ 551 PCIE_MSG_VALID = (uint32_t)1 /* enabled/valid */ 552 } pcie_msg_valid_state_t; 553 554 /* PCIe MSG types */ 555 typedef enum pcie_msg_type { 556 PCIE_PME_MSG = (uint64_t)0x18, /* PME message */ 557 PCIE_PME_ACK_MSG = (uint64_t)0x1b, /* PME ACK message */ 558 PCIE_CORR_MSG = (uint64_t)0x30, /* Correctable message */ 559 PCIE_NONFATAL_MSG = (uint64_t)0x31, /* Non fatal message */ 560 PCIE_FATAL_MSG = (uint64_t)0x33 /* Fatal message */ 561 } pcie_msg_type_t; 562 563 #endif /* _ASM */ 564 565 #ifdef __cplusplus 566 } 567 #endif 568 569 #endif /* _SYS_PX_IOAPI_H */ 570