xref: /titanic_41/usr/src/uts/sun4/io/px/px_ib.h (revision 7801e5e8b5bc4af34929c54a02cfb78398da08dd)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef	_SYS_PX_IB_H
27 #define	_SYS_PX_IB_H
28 
29 #ifdef	__cplusplus
30 extern "C" {
31 #endif
32 
33 #include <sys/ddi_subrdefs.h>
34 #include <sys/pci_tools.h>
35 
36 typedef struct px_ib		px_ib_t;
37 typedef struct px_ino		px_ino_t;
38 typedef struct px_ino_pil	px_ino_pil_t;
39 typedef struct px_ih		px_ih_t;
40 
41 /*
42  * interrupt block soft state structure:
43  *
44  * Each px node may share an interrupt block structure with its peer
45  * node or have its own private interrupt block structure.
46  */
47 struct px_ib {
48 	px_t		*ib_px_p;	/* link back to px soft state */
49 	px_ino_t	*ib_ino_lst;	/* ino link list */
50 	kmutex_t	ib_ino_lst_mutex; /* mutex for ino link list */
51 	kmutex_t	ib_intr_lock;	/* lock for internal intr  */
52 
53 	px_msiq_state_t	ib_msiq_state;	/* MSIQ soft state */
54 	px_msi_state_t	ib_msi_state;	/* MSI soft state */
55 };
56 
57 /*
58  * ih structure: one per every consumer of each ino and pil pair with interrupt
59  * registered.
60  */
61 struct px_ih {
62 	dev_info_t	*ih_dip;	/* devinfo structure */
63 	uint32_t	ih_inum;	/* interrupt number for this device */
64 	uint_t		(*ih_handler)(); /* interrupt handler */
65 	caddr_t		ih_handler_arg1; /* interrupt handler argument #1 */
66 	caddr_t		ih_handler_arg2; /* interrupt handler argument #2 */
67 	ddi_acc_handle_t ih_config_handle; /* config space reg map handle */
68 	uint_t		ih_intr_state;	/* only used for fixed interrupts */
69 	msiq_rec_type_t	ih_rec_type;	/* MSI or PCIe record type */
70 	msgcode_t	ih_msg_code;	/* MSI number or PCIe message code */
71 	boolean_t	ih_retarget_flag; /* MSI/X retarget flag */
72 	px_ih_t		*ih_next;	/* Next entry in list */
73 	uint64_t	ih_ticks;	/* ticks spent in this handler */
74 	uint64_t	ih_nsec;	/* nsec spent in this handler */
75 	kstat_t		*ih_ksp;	/* pointer to kstat information */
76 	px_ino_pil_t	*ih_ipil_p;	/* only for use by kstat */
77 };
78 
79 /* Only used for fixed or legacy interrupts */
80 #define	PX_INTR_STATE_DISABLE	0	/* disabled */
81 #define	PX_INTR_STATE_ENABLE	1	/* enabled */
82 
83 /*
84  * ino_pil structure: one per each ino and pil pair with interrupt registered
85  */
86 struct px_ino_pil {
87 	ushort_t	ipil_pil;	/* pil for this ino */
88 	ushort_t	ipil_ih_size;	/* size of px_ih_t list */
89 	px_ih_t		*ipil_ih_head;	/* px_ih_t list head */
90 	px_ih_t		*ipil_ih_tail;	/* px_ih_t list tail */
91 	px_ih_t		*ipil_ih_start;	/* starting point in px_ih_t list  */
92 	px_ino_t	*ipil_ino_p;	/* pointer to px_ino_t structure */
93 	px_ino_pil_t	*ipil_next_p;	/* pointer to next px_ino_pil_t */
94 };
95 
96 /*
97  * ino structure: one per each ino with interrupt registered
98  */
99 struct px_ino {
100 	devino_t	ino_ino;	/* INO number - 8 bit */
101 	sysino_t	ino_sysino;	/* Virtual inumber */
102 	px_ib_t		*ino_ib_p;	/* link back to interrupt block state */
103 	uint_t		ino_unclaimed_intrs; /* number of unclaimed intrs */
104 	clock_t		ino_spurintr_begin; /* begin time of spurious intr */
105 	cpuid_t		ino_cpuid;	/* current cpu for this ino */
106 	cpuid_t		ino_default_cpuid; /* default cpu for this ino */
107 	int32_t		ino_intr_weight; /* intr wt of devices sharing ino */
108 	ushort_t	ino_ipil_size;	/* no of px_ino_pil_t sharing ino */
109 	ushort_t	ino_lopil;	/* lowest pil sharing ino */
110 	ushort_t	ino_claimed;	/* pil bit masks, who claimed intr */
111 	px_msiq_t	*ino_msiq_p;	/* pointer to MSIQ used */
112 	px_ino_pil_t	*ino_ipil_p;	/* pointer to first px_ino_pil_t */
113 	px_ino_t	*ino_next_p;	/* pointer to next px_ino_t */
114 	ushort_t	ino_ipil_cntr;	/* counter for pil sharing ino */
115 };
116 
117 #define	IB_INTR_WAIT	1		/* wait for interrupt completion */
118 #define	IB_INTR_NOWAIT	0		/* already handling intr, no wait */
119 
120 #define	PX_INTR_ENABLE(dip, sysino, cpuid) \
121 	(void) px_lib_intr_settarget(dip, sysino, cpuid); \
122 	(void) px_lib_intr_setvalid(dip, sysino, INTR_VALID);
123 
124 #define	PX_INTR_DISABLE(dip, sysino) \
125 	(void) px_lib_intr_setvalid(dip, sysino, INTR_NOTVALID);
126 
127 extern int px_ib_attach(px_t *px_p);
128 extern void px_ib_detach(px_t *px_p);
129 extern void px_ib_intr_enable(px_t *px_p, cpuid_t cpuid, devino_t ino);
130 extern void px_ib_intr_disable(px_ib_t *ib_p, devino_t ino, int wait);
131 extern void px_ib_intr_dist_en(dev_info_t *dip, cpuid_t cpu_id, devino_t ino,
132     boolean_t wait_flag);
133 
134 extern px_ino_t *px_ib_locate_ino(px_ib_t *ib_p, devino_t ino_num);
135 extern void px_ib_free_ino_all(px_ib_t *ib_p);
136 
137 extern px_ino_pil_t *px_ib_ino_locate_ipil(px_ino_t *ino_p, uint_t pil);
138 extern px_ino_t *px_ib_alloc_ino(px_ib_t *ib_p, devino_t ino_num);
139 extern px_ino_pil_t *px_ib_new_ino_pil(px_ib_t *ib_p, devino_t ino_num,
140     uint_t pil, px_ih_t *ih_p);
141 extern void px_ib_delete_ino_pil(px_ib_t *ib_p, px_ino_pil_t *ipil_p);
142 extern int px_ib_ino_add_intr(px_t *px_p, px_ino_pil_t *ipil_p, px_ih_t *ih_p);
143 extern int px_ib_ino_rem_intr(px_t *px_p, px_ino_pil_t *ipil_p, px_ih_t *ih_p);
144 
145 extern px_ih_t *px_ib_intr_locate_ih(px_ino_pil_t *ipil_p, dev_info_t *dip,
146 	uint32_t inum, msiq_rec_type_t rec_type, msgcode_t msg_code);
147 extern px_ih_t *px_ib_alloc_ih(dev_info_t *rdip, uint32_t inum,
148 	uint_t (*int_handler)(caddr_t int_handler_arg1,
149 	caddr_t int_handler_arg2), caddr_t int_handler_arg1,
150 	caddr_t int_handler_arg2, msiq_rec_type_t rec_type, msgcode_t msg_code);
151 extern void px_ib_free_ih(px_ih_t *ih_p);
152 extern int px_ib_update_intr_state(px_t *px_p, dev_info_t *rdip, uint_t inum,
153 	devino_t ino, uint_t pil, uint_t new_intr_state,
154 	msiq_rec_type_t rec_type, msgcode_t msg_code);
155 extern int px_ib_get_intr_target(px_t *px_p, devino_t ino, cpuid_t *cpu_id_p);
156 extern int px_ib_set_intr_target(px_t *px_p, devino_t ino, cpuid_t cpu_id);
157 extern int px_ib_set_msix_target(px_t *px_p, ddi_intr_handle_impl_t *hdlp,
158 	msinum_t msi_num, cpuid_t cpuid);
159 extern uint8_t pxtool_ib_get_ino_devs(px_t *px_p, uint32_t ino,
160 	uint32_t msi_num, uint8_t *devs_ret, pcitool_intr_dev_t *devs);
161 extern int pxtool_ib_get_msi_info(px_t *px_p, devino_t ino, msinum_t msi_num,
162 	ddi_intr_handle_impl_t *hdlp);
163 extern void px_ib_log_new_cpu(px_ib_t *ib_p, cpuid_t old_cpu_id,
164 	cpuid_t new_cpu_id, uint32_t ino);
165 
166 #ifdef	__cplusplus
167 }
168 #endif
169 
170 #endif	/* _SYS_PX_IB_H */
171