1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * PX Fault Management Architecture 30 */ 31 #include <sys/types.h> 32 #include <sys/sunndi.h> 33 #include <sys/sunddi.h> 34 #include <sys/fm/protocol.h> 35 #include <sys/fm/util.h> 36 #include <sys/membar.h> 37 #include "px_obj.h" 38 39 #define PX_PCIE_PANIC_BITS \ 40 (PCIE_AER_UCE_DLP | PCIE_AER_UCE_FCP | PCIE_AER_UCE_TO | \ 41 PCIE_AER_UCE_RO | PCIE_AER_UCE_MTLP | PCIE_AER_UCE_ECRC) 42 #define PX_PCIE_NO_PANIC_BITS \ 43 (PCIE_AER_UCE_TRAINING | PCIE_AER_UCE_SD | PCIE_AER_UCE_CA | \ 44 PCIE_AER_UCE_UC | PCIE_AER_UCE_UR) 45 46 static void px_err_fill_pfd(dev_info_t *rpdip, px_err_pcie_t *regs); 47 static int px_pcie_ptlp(dev_info_t *dip, ddi_fm_error_t *derr, 48 px_err_pcie_t *regs); 49 50 #if defined(DEBUG) 51 static void px_pcie_log(dev_info_t *dip, px_err_pcie_t *regs, int severity); 52 #else /* DEBUG */ 53 #define px_pcie_log 0 && 54 #endif /* DEBUG */ 55 56 /* external functions */ 57 extern int pci_xcap_locate(ddi_acc_handle_t h, uint16_t id, uint16_t *base_p); 58 extern int pci_lcap_locate(ddi_acc_handle_t h, uint8_t id, uint16_t *base_p); 59 60 /* 61 * Initialize px FMA support 62 */ 63 int 64 px_fm_attach(px_t *px_p) 65 { 66 px_p->px_fm_cap = DDI_FM_EREPORT_CAPABLE | DDI_FM_ERRCB_CAPABLE | 67 DDI_FM_ACCCHK_CAPABLE | DDI_FM_DMACHK_CAPABLE; 68 69 /* 70 * Initialize pci_target_queue for FMA handling of 71 * pci errors. 72 */ 73 pci_targetq_init(); 74 75 /* 76 * check parents' capability 77 */ 78 ddi_fm_init(px_p->px_dip, &px_p->px_fm_cap, &px_p->px_fm_ibc); 79 80 /* 81 * parents need to be ereport and error handling capable 82 */ 83 ASSERT(px_p->px_fm_cap && 84 (DDI_FM_ERRCB_CAPABLE | DDI_FM_EREPORT_CAPABLE)); 85 86 /* 87 * Initialize lock to synchronize fabric error handling 88 */ 89 mutex_init(&px_p->px_fm_mutex, NULL, MUTEX_DRIVER, 90 (void *)px_p->px_fm_ibc); 91 92 /* 93 * register error callback in parent 94 */ 95 ddi_fm_handler_register(px_p->px_dip, px_fm_callback, px_p); 96 97 return (DDI_SUCCESS); 98 } 99 100 /* 101 * Deregister FMA 102 */ 103 void 104 px_fm_detach(px_t *px_p) 105 { 106 ddi_fm_handler_unregister(px_p->px_dip); 107 mutex_destroy(&px_p->px_fm_mutex); 108 ddi_fm_fini(px_p->px_dip); 109 } 110 111 /* 112 * Function used to setup access functions depending on level of desired 113 * protection. 114 */ 115 void 116 px_fm_acc_setup(ddi_map_req_t *mp, dev_info_t *rdip) 117 { 118 uchar_t fflag; 119 ddi_acc_hdl_t *hp; 120 ddi_acc_impl_t *ap; 121 122 hp = mp->map_handlep; 123 ap = (ddi_acc_impl_t *)hp->ah_platform_private; 124 fflag = ap->ahi_common.ah_acc.devacc_attr_access; 125 126 if (mp->map_op == DDI_MO_MAP_LOCKED) { 127 ndi_fmc_insert(rdip, ACC_HANDLE, (void *)hp, NULL); 128 switch (fflag) { 129 case DDI_FLAGERR_ACC: 130 ap->ahi_get8 = i_ddi_prot_get8; 131 ap->ahi_get16 = i_ddi_prot_get16; 132 ap->ahi_get32 = i_ddi_prot_get32; 133 ap->ahi_get64 = i_ddi_prot_get64; 134 ap->ahi_put8 = i_ddi_prot_put8; 135 ap->ahi_put16 = i_ddi_prot_put16; 136 ap->ahi_put32 = i_ddi_prot_put32; 137 ap->ahi_put64 = i_ddi_prot_put64; 138 ap->ahi_rep_get8 = i_ddi_prot_rep_get8; 139 ap->ahi_rep_get16 = i_ddi_prot_rep_get16; 140 ap->ahi_rep_get32 = i_ddi_prot_rep_get32; 141 ap->ahi_rep_get64 = i_ddi_prot_rep_get64; 142 ap->ahi_rep_put8 = i_ddi_prot_rep_put8; 143 ap->ahi_rep_put16 = i_ddi_prot_rep_put16; 144 ap->ahi_rep_put32 = i_ddi_prot_rep_put32; 145 ap->ahi_rep_put64 = i_ddi_prot_rep_put64; 146 break; 147 case DDI_CAUTIOUS_ACC : 148 ap->ahi_get8 = i_ddi_caut_get8; 149 ap->ahi_get16 = i_ddi_caut_get16; 150 ap->ahi_get32 = i_ddi_caut_get32; 151 ap->ahi_get64 = i_ddi_caut_get64; 152 ap->ahi_put8 = i_ddi_caut_put8; 153 ap->ahi_put16 = i_ddi_caut_put16; 154 ap->ahi_put32 = i_ddi_caut_put32; 155 ap->ahi_put64 = i_ddi_caut_put64; 156 ap->ahi_rep_get8 = i_ddi_caut_rep_get8; 157 ap->ahi_rep_get16 = i_ddi_caut_rep_get16; 158 ap->ahi_rep_get32 = i_ddi_caut_rep_get32; 159 ap->ahi_rep_get64 = i_ddi_caut_rep_get64; 160 ap->ahi_rep_put8 = i_ddi_caut_rep_put8; 161 ap->ahi_rep_put16 = i_ddi_caut_rep_put16; 162 ap->ahi_rep_put32 = i_ddi_caut_rep_put32; 163 ap->ahi_rep_put64 = i_ddi_caut_rep_put64; 164 break; 165 default: 166 break; 167 } 168 } else if (mp->map_op == DDI_MO_UNMAP) { 169 ndi_fmc_remove(rdip, ACC_HANDLE, (void *)hp); 170 } 171 } 172 173 /* 174 * Function used to initialize FMA for our children nodes. Called 175 * through pci busops when child node calls ddi_fm_init. 176 */ 177 /*ARGSUSED*/ 178 int 179 px_fm_init_child(dev_info_t *dip, dev_info_t *cdip, int cap, 180 ddi_iblock_cookie_t *ibc_p) 181 { 182 px_t *px_p = DIP_TO_STATE(dip); 183 184 ASSERT(ibc_p != NULL); 185 *ibc_p = px_p->px_fm_ibc; 186 187 return (px_p->px_fm_cap); 188 } 189 190 /* 191 * lock access for exclusive PCIe access 192 */ 193 void 194 px_bus_enter(dev_info_t *dip, ddi_acc_handle_t handle) 195 { 196 px_pec_t *pec_p = ((px_t *)DIP_TO_STATE(dip))->px_pec_p; 197 198 /* 199 * Exclusive access has been used for cautious put/get, 200 * Both utilize i_ddi_ontrap which, on sparcv9, implements 201 * similar protection as what on_trap() does, and which calls 202 * membar #Sync to flush out all cpu deferred errors 203 * prior to get/put operation, so here we're not calling 204 * membar #Sync - a difference from what's in pci_bus_enter(). 205 */ 206 mutex_enter(&pec_p->pec_pokefault_mutex); 207 pec_p->pec_acc_hdl = handle; 208 } 209 210 /* 211 * unlock access for exclusive PCIe access 212 */ 213 /* ARGSUSED */ 214 void 215 px_bus_exit(dev_info_t *dip, ddi_acc_handle_t handle) 216 { 217 px_t *px_p = DIP_TO_STATE(dip); 218 px_pec_t *pec_p = px_p->px_pec_p; 219 220 pec_p->pec_acc_hdl = NULL; 221 mutex_exit(&pec_p->pec_pokefault_mutex); 222 } 223 224 225 /* 226 * PCI error callback which is registered with our parent to call 227 * for PCIe logging when the CPU traps due to PCIe Uncorrectable Errors 228 * and PCI BERR/TO/UE on IO Loads. 229 */ 230 /*ARGSUSED*/ 231 int 232 px_fm_callback(dev_info_t *dip, ddi_fm_error_t *derr, const void *impl_data) 233 { 234 dev_info_t *pdip = ddi_get_parent(dip); 235 px_t *px_p = (px_t *)impl_data; 236 int i, acc_type = 0; 237 int lookup, rc_err, fab_err = PF_NO_PANIC; 238 uint32_t addr, addr_high, addr_low; 239 pcie_req_id_t bdf; 240 px_ranges_t *ranges_p; 241 int range_len; 242 243 /* 244 * If the current thread already owns the px_fm_mutex, then we 245 * have encountered an error while processing a previous 246 * error. Attempting to take the mutex again will cause the 247 * system to deadlock. 248 */ 249 if (px_p->px_fm_mutex_owner == curthread) 250 return (DDI_FM_FATAL); 251 252 i_ddi_fm_handler_exit(pdip); 253 mutex_enter(&px_p->px_fm_mutex); 254 px_p->px_fm_mutex_owner = curthread; 255 256 addr_high = (uint32_t)((uint64_t)derr->fme_bus_specific >> 32); 257 addr_low = (uint32_t)((uint64_t)derr->fme_bus_specific); 258 259 /* 260 * Make sure this failed load came from this PCIe port. Check by 261 * matching the upper 32 bits of the address with the ranges property. 262 */ 263 range_len = px_p->px_ranges_length / sizeof (px_ranges_t); 264 i = 0; 265 for (ranges_p = px_p->px_ranges_p; i < range_len; i++, ranges_p++) { 266 if (ranges_p->parent_high == addr_high) { 267 switch (ranges_p->child_high & PCI_ADDR_MASK) { 268 case PCI_ADDR_CONFIG: 269 acc_type = PF_CFG_ADDR; 270 addr = NULL; 271 bdf = (pcie_req_id_t)(addr_low >> 12); 272 break; 273 case PCI_ADDR_IO: 274 acc_type = PF_IO_ADDR; 275 addr = addr_low; 276 bdf = NULL; 277 break; 278 case PCI_ADDR_MEM32: 279 acc_type = PF_DMA_ADDR; 280 addr = addr_low; 281 bdf = NULL; 282 break; 283 } 284 break; 285 } 286 } 287 288 /* This address doesn't belong to this leaf, just return with OK */ 289 if (!acc_type) { 290 px_p->px_fm_mutex_owner = NULL; 291 mutex_exit(&px_p->px_fm_mutex); 292 i_ddi_fm_handler_enter(pdip); 293 return (DDI_FM_OK); 294 } else if (acc_type == PF_IO_ADDR) { 295 px_p->px_fm_mutex_owner = NULL; 296 mutex_exit(&px_p->px_fm_mutex); 297 i_ddi_fm_handler_enter(pdip); 298 return (DDI_FM_FATAL); 299 } 300 301 rc_err = px_err_cmn_intr(px_p, derr, PX_TRAP_CALL, PX_FM_BLOCK_ALL); 302 lookup = pf_hdl_lookup(dip, derr->fme_ena, acc_type, addr, bdf); 303 304 if (!px_lib_is_in_drain_state(px_p)) { 305 /* 306 * This is to ensure that device corresponding to the addr of 307 * the failed PIO/CFG load gets scanned. 308 */ 309 px_rp_en_q(px_p, bdf, addr, 310 (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)); 311 fab_err = pf_scan_fabric(dip, derr, px_p->px_dq_p, 312 &px_p->px_dq_tail); 313 } 314 315 px_p->px_fm_mutex_owner = NULL; 316 mutex_exit(&px_p->px_fm_mutex); 317 i_ddi_fm_handler_enter(pdip); 318 319 if ((rc_err & (PX_PANIC | PX_PROTECTED)) || (fab_err & PF_PANIC) || 320 (lookup == PF_HDL_NOTFOUND)) 321 return (DDI_FM_FATAL); 322 else if ((rc_err == PX_NO_ERROR) && (fab_err == PF_NO_ERROR)) 323 return (DDI_FM_OK); 324 325 return (DDI_FM_NONFATAL); 326 } 327 328 /* 329 * px_err_fabric_intr: 330 * Interrupt handler for PCIE fabric block. 331 * o lock 332 * o create derr 333 * o px_err_cmn_intr(leaf, with jbc) 334 * o send ereport(fire fmri, derr, payload = BDF) 335 * o dispatch (leaf) 336 * o unlock 337 * o handle error: fatal? fm_panic() : return INTR_CLAIMED) 338 */ 339 /* ARGSUSED */ 340 uint_t 341 px_err_fabric_intr(px_t *px_p, msgcode_t msg_code, pcie_req_id_t rid) 342 { 343 dev_info_t *rpdip = px_p->px_dip; 344 int rc_err, fab_err = PF_NO_PANIC; 345 ddi_fm_error_t derr; 346 347 mutex_enter(&px_p->px_fm_mutex); 348 px_p->px_fm_mutex_owner = curthread; 349 350 /* Create the derr */ 351 bzero(&derr, sizeof (ddi_fm_error_t)); 352 derr.fme_version = DDI_FME_VERSION; 353 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 354 derr.fme_flag = DDI_FM_ERR_UNEXPECTED; 355 356 /* Ensure that the rid of the fabric message will get scanned. */ 357 px_rp_en_q(px_p, rid, NULL, NULL); 358 359 rc_err = px_err_cmn_intr(px_p, &derr, PX_INTR_CALL, PX_FM_BLOCK_PCIE); 360 361 /* call rootport dispatch */ 362 if (!px_lib_is_in_drain_state(px_p)) { 363 fab_err = pf_scan_fabric(rpdip, &derr, px_p->px_dq_p, 364 &px_p->px_dq_tail); 365 } 366 367 px_p->px_fm_mutex_owner = NULL; 368 mutex_exit(&px_p->px_fm_mutex); 369 370 px_err_panic(rc_err, PX_RC, fab_err); 371 372 return (DDI_INTR_CLAIMED); 373 } 374 375 /* 376 * px_err_safeacc_check: 377 * Check to see if a peek/poke and cautious access is currently being 378 * done on a particular leaf. 379 * 380 * Safe access reads induced fire errors will be handled by cpu trap handler 381 * which will call px_fm_callback() which calls this function. In that 382 * case, the derr fields will be set by trap handler with the correct values. 383 * 384 * Safe access writes induced errors will be handled by px interrupt 385 * handlers, this function will fill in the derr fields. 386 * 387 * If a cpu trap does occur, it will quiesce all other interrupts allowing 388 * the cpu trap error handling to finish before Fire receives an interrupt. 389 * 390 * If fire does indeed have an error when a cpu trap occurs as a result of 391 * a safe access, a trap followed by a Mondo/Fabric interrupt will occur. 392 * In which case derr will be initialized as "UNEXPECTED" by the interrupt 393 * handler and this function will need to find if this error occured in the 394 * middle of a safe access operation. 395 * 396 * @param px_p leaf in which to check access 397 * @param derr fm err data structure to be updated 398 */ 399 void 400 px_err_safeacc_check(px_t *px_p, ddi_fm_error_t *derr) 401 { 402 px_pec_t *pec_p = px_p->px_pec_p; 403 int acctype = pec_p->pec_safeacc_type; 404 405 ASSERT(MUTEX_HELD(&px_p->px_fm_mutex)); 406 407 if (derr->fme_flag != DDI_FM_ERR_UNEXPECTED) { 408 return; 409 } 410 411 /* safe access checking */ 412 switch (acctype) { 413 case DDI_FM_ERR_EXPECTED: 414 /* 415 * cautious access protection, protected from all err. 416 */ 417 ddi_fm_acc_err_get(pec_p->pec_acc_hdl, derr, 418 DDI_FME_VERSION); 419 derr->fme_flag = acctype; 420 derr->fme_acc_handle = pec_p->pec_acc_hdl; 421 break; 422 case DDI_FM_ERR_POKE: 423 /* 424 * ddi_poke protection, check nexus and children for 425 * expected errors. 426 */ 427 membar_sync(); 428 derr->fme_flag = acctype; 429 break; 430 case DDI_FM_ERR_PEEK: 431 derr->fme_flag = acctype; 432 break; 433 } 434 } 435 436 /* 437 * Suggest panic if any EQ (except CE q) has overflown. 438 */ 439 int 440 px_err_check_eq(dev_info_t *dip) 441 { 442 px_t *px_p = DIP_TO_STATE(dip); 443 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 444 px_pec_t *pec_p = px_p->px_pec_p; 445 msiqid_t eq_no = msiq_state_p->msiq_1st_msiq_id; 446 pci_msiq_state_t msiq_state; 447 int i; 448 449 for (i = 0; i < msiq_state_p->msiq_cnt; i++) { 450 if (i + eq_no == pec_p->pec_corr_msg_msiq_id) /* skip CE q */ 451 continue; 452 if ((px_lib_msiq_getstate(dip, i + eq_no, &msiq_state) != 453 DDI_SUCCESS) || msiq_state == PCI_MSIQ_STATE_ERROR) 454 return (PX_PANIC); 455 } 456 return (PX_NO_PANIC); 457 } 458 459 static void 460 px_err_fill_pfd(dev_info_t *rpdip, px_err_pcie_t *regs) 461 { 462 px_t *px_p = DIP_TO_STATE(rpdip); 463 pf_data_t pf_data = {0}; 464 pcie_req_id_t fault_bdf = 0; 465 uint32_t fault_addr = 0; 466 uint16_t s_status = 0; 467 468 pf_data.rp_bdf = px_p->px_bdf; 469 470 /* 471 * set RC s_status in PCI term to coordinate with downstream fabric 472 * errors ananlysis. 473 */ 474 if (regs->primary_ue & PCIE_AER_UCE_UR) 475 s_status = PCI_STAT_R_MAST_AB; 476 if (regs->primary_ue & PCIE_AER_UCE_CA) 477 s_status = PCI_STAT_R_TARG_AB; 478 if (regs->primary_ue & (PCIE_AER_UCE_PTLP | PCIE_AER_UCE_ECRC)) 479 s_status = PCI_STAT_PERROR; 480 481 if (regs->primary_ue & (PCIE_AER_UCE_UR | PCIE_AER_UCE_CA)) { 482 pf_data.aer_h0 = regs->rx_hdr1; 483 pf_data.aer_h1 = regs->rx_hdr2; 484 pf_data.aer_h2 = regs->rx_hdr3; 485 pf_data.aer_h3 = regs->rx_hdr4; 486 487 pf_tlp_decode(rpdip, &pf_data, &fault_bdf, NULL, NULL); 488 } else if (regs->primary_ue & PCIE_AER_UCE_PTLP) { 489 pcie_tlp_hdr_t *tlp_p; 490 491 pf_data.aer_h0 = regs->rx_hdr1; 492 pf_data.aer_h1 = regs->rx_hdr2; 493 pf_data.aer_h2 = regs->rx_hdr3; 494 pf_data.aer_h3 = regs->rx_hdr4; 495 496 tlp_p = (pcie_tlp_hdr_t *)&pf_data.aer_h0; 497 if (tlp_p->type == PCIE_TLP_TYPE_CPL) 498 pf_tlp_decode(rpdip, &pf_data, &fault_bdf, NULL, NULL); 499 500 pf_data.aer_h0 = regs->tx_hdr1; 501 pf_data.aer_h1 = regs->tx_hdr2; 502 pf_data.aer_h2 = regs->tx_hdr3; 503 pf_data.aer_h3 = regs->tx_hdr4; 504 505 pf_tlp_decode(rpdip, &pf_data, NULL, &fault_addr, NULL); 506 } 507 508 px_rp_en_q(px_p, fault_bdf, fault_addr, s_status); 509 } 510 511 int 512 px_err_check_pcie(dev_info_t *dip, ddi_fm_error_t *derr, px_err_pcie_t *regs) 513 { 514 uint32_t ce_reg, ue_reg; 515 int err = PX_NO_ERROR; 516 517 ce_reg = regs->ce_reg; 518 if (ce_reg) 519 err |= (ce_reg & px_fabric_die_rc_ce) ? PX_PANIC : PX_NO_ERROR; 520 521 ue_reg = regs->ue_reg; 522 if (!ue_reg) 523 goto done; 524 525 if (ue_reg & PCIE_AER_UCE_PTLP) 526 err |= px_pcie_ptlp(dip, derr, regs); 527 528 if (ue_reg & PX_PCIE_PANIC_BITS) 529 err |= PX_PANIC; 530 531 if (ue_reg & PX_PCIE_NO_PANIC_BITS) 532 err |= PX_NO_PANIC; 533 534 /* Scan the fabric to clean up error bits, for the following errors. */ 535 if (ue_reg & (PCIE_AER_UCE_PTLP | PCIE_AER_UCE_CA | PCIE_AER_UCE_UR)) 536 px_err_fill_pfd(dip, regs); 537 done: 538 px_pcie_log(dip, regs, err); 539 return (err); 540 } 541 542 #if defined(DEBUG) 543 static void 544 px_pcie_log(dev_info_t *dip, px_err_pcie_t *regs, int severity) 545 { 546 DBG(DBG_ERR_INTR, dip, 547 "A PCIe RC error has occured with a severity of \"%s\"\n" 548 "\tCE: 0x%x UE: 0x%x Primary UE: 0x%x\n" 549 "\tTX Hdr: 0x%x 0x%x 0x%x 0x%x\n\tRX Hdr: 0x%x 0x%x 0x%x 0x%x\n", 550 (severity & PX_PANIC) ? "PANIC" : "NO PANIC", regs->ce_reg, 551 regs->ue_reg, regs->primary_ue, regs->tx_hdr1, regs->tx_hdr2, 552 regs->tx_hdr3, regs->tx_hdr4, regs->rx_hdr1, regs->rx_hdr2, 553 regs->rx_hdr3, regs->rx_hdr4); 554 } 555 #endif /* DEBUG */ 556 557 /* 558 * look through poisoned TLP cases and suggest panic/no panic depend on 559 * handle lookup. 560 */ 561 static int 562 px_pcie_ptlp(dev_info_t *dip, ddi_fm_error_t *derr, px_err_pcie_t *regs) 563 { 564 px_t *px_p = DIP_TO_STATE(dip); 565 pf_data_t pf_data; 566 pcie_req_id_t bdf; 567 uint32_t addr, trans_type; 568 int tlp_sts, tlp_cmd; 569 int sts = PF_HDL_NOTFOUND; 570 571 if (regs->primary_ue != PCIE_AER_UCE_PTLP) 572 return (PX_PANIC); 573 574 if (!regs->rx_hdr1) 575 goto done; 576 577 pf_data.rp_bdf = px_p->px_bdf; 578 pf_data.aer_h0 = regs->rx_hdr1; 579 pf_data.aer_h1 = regs->rx_hdr2; 580 pf_data.aer_h2 = regs->rx_hdr3; 581 pf_data.aer_h3 = regs->rx_hdr4; 582 583 tlp_sts = pf_tlp_decode(dip, &pf_data, &bdf, &addr, &trans_type); 584 tlp_cmd = ((pcie_tlp_hdr_t *)(&pf_data.aer_h0))->type; 585 586 if (tlp_sts == DDI_FAILURE) 587 goto done; 588 589 switch (tlp_cmd) { 590 case PCIE_TLP_TYPE_CPL: 591 case PCIE_TLP_TYPE_CPLLK: 592 /* 593 * Usually a PTLP is a CPL with data. Grab the completer BDF 594 * from the RX TLP, and the original address from the TX TLP. 595 */ 596 if (regs->tx_hdr1) { 597 pf_data.aer_h0 = regs->tx_hdr1; 598 pf_data.aer_h1 = regs->tx_hdr2; 599 pf_data.aer_h2 = regs->tx_hdr3; 600 pf_data.aer_h3 = regs->tx_hdr4; 601 602 sts = pf_tlp_decode(dip, &pf_data, NULL, &addr, 603 &trans_type); 604 } /* FALLTHRU */ 605 case PCIE_TLP_TYPE_IO: 606 case PCIE_TLP_TYPE_MEM: 607 case PCIE_TLP_TYPE_MEMLK: 608 sts = pf_hdl_lookup(dip, derr->fme_ena, trans_type, addr, bdf); 609 break; 610 default: 611 sts = PF_HDL_NOTFOUND; 612 } 613 done: 614 return (sts == PF_HDL_NOTFOUND ? PX_PANIC : PX_NO_PANIC); 615 } 616 617 /* 618 * This function appends a pf_data structure to the error q which is used later 619 * during PCIe fabric scan. It signifies: 620 * o errs rcvd in RC, that may have been propagated to/from the fabric 621 * o the fabric scan code should scan the device path of fault bdf/addr 622 * 623 * fault_bdf: The bdf that caused the fault, which may have error bits set. 624 * fault_addr: The PIO addr that caused the fault, such as failed PIO, but not 625 * failed DMAs. 626 * s_status: Secondary Status equivalent to why the fault occured. 627 * (ie S-TA/MA, R-TA) 628 * Either the fault bdf or addr may be NULL, but not both. 629 */ 630 int px_foo = 0; 631 void 632 px_rp_en_q(px_t *px_p, pcie_req_id_t fault_bdf, uint32_t fault_addr, 633 uint16_t s_status) 634 { 635 pf_data_t pf_data = {0}; 636 637 if (!fault_bdf && !fault_addr) 638 return; 639 640 pf_data.dev_type = PCIE_PCIECAP_DEV_TYPE_ROOT; 641 if (px_foo) { 642 pf_data.fault_bdf = px_foo; 643 px_foo = 0; 644 } else 645 pf_data.fault_bdf = fault_bdf; 646 647 pf_data.bdf = px_p->px_bdf; 648 pf_data.rp_bdf = px_p->px_bdf; 649 pf_data.fault_addr = fault_addr; 650 pf_data.s_status = s_status; 651 pf_data.send_erpt = PF_SEND_ERPT_NO; 652 653 (void) pf_en_dq(&pf_data, px_p->px_dq_p, &px_p->px_dq_tail, -1); 654 } 655 656 /* 657 * Panic if the err tunable is set and that we are not already in the middle 658 * of panic'ing. 659 */ 660 #define MSZ (sizeof (fm_msg) -strlen(fm_msg) - 1) 661 void 662 px_err_panic(int err, int msg, int fab_err) 663 { 664 char fm_msg[96] = ""; 665 int ferr = PX_NO_ERROR; 666 667 if (panicstr) 668 return; 669 670 if (!(err & px_die)) 671 goto fabric; 672 if (msg & PX_RC) 673 (void) strncat(fm_msg, px_panic_rc_msg, MSZ); 674 if (msg & PX_RP) 675 (void) strncat(fm_msg, px_panic_rp_msg, MSZ); 676 if (msg & PX_HB) 677 (void) strncat(fm_msg, px_panic_hb_msg, MSZ); 678 679 fabric: 680 if (fab_err & PF_PANIC) 681 ferr = PX_PANIC; 682 else if (fab_err & ~(PF_PANIC | PF_NO_ERROR)) 683 ferr = PX_NO_PANIC; 684 685 if (ferr & px_die) { 686 if (strlen(fm_msg)) 687 (void) strncat(fm_msg, " and", MSZ); 688 (void) strncat(fm_msg, px_panic_fab_msg, MSZ); 689 } 690 691 if (strlen(fm_msg)) 692 fm_panic("Fatal error has occured in:%s.", fm_msg); 693 } 694