xref: /titanic_41/usr/src/uts/sun4/io/px/px_devctl.c (revision 355b4669e025ff377602b6fc7caaf30dbc218371)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #pragma ident	"%Z%%M%	%I%	%E% SMI"
27 
28 /*
29  * PCI nexus HotPlug devctl interface
30  */
31 #include <sys/types.h>
32 #include <sys/conf.h>
33 #include <sys/kmem.h>
34 #include <sys/async.h>
35 #include <sys/sysmacros.h>
36 #include <sys/sunddi.h>
37 #include <sys/sunndi.h>
38 #include <sys/ddi_impldefs.h>
39 #include <sys/open.h>
40 #include <sys/errno.h>
41 #include <sys/file.h>
42 #include <sys/policy.h>
43 #include <sys/hotplug/pci/pcihp.h>
44 #include "px_obj.h"
45 #include <sys/pci_tools.h>
46 #include "px_tools_ext.h"
47 #include "pcie_pwr.h"
48 
49 /*LINTLIBRARY*/
50 
51 static int px_open(dev_t *devp, int flags, int otyp, cred_t *credp);
52 static int px_close(dev_t dev, int flags, int otyp, cred_t *credp);
53 static int px_ioctl(dev_t dev, int cmd, intptr_t arg, int mode,
54 						cred_t *credp, int *rvalp);
55 static int px_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op,
56     int flags, char *name, caddr_t valuep, int *lengthp);
57 
58 struct cb_ops px_cb_ops = {
59 	px_open,			/* open */
60 	px_close,			/* close */
61 	nodev,				/* strategy */
62 	nodev,				/* print */
63 	nodev,				/* dump */
64 	nodev,				/* read */
65 	nodev,				/* write */
66 	px_ioctl,			/* ioctl */
67 	nodev,				/* devmap */
68 	nodev,				/* mmap */
69 	nodev,				/* segmap */
70 	nochpoll,			/* poll */
71 	px_prop_op,			/* cb_prop_op */
72 	NULL,				/* streamtab */
73 	D_NEW | D_MP | D_HOTPLUG,	/* Driver compatibility flag */
74 	CB_REV,				/* rev */
75 	nodev,				/* int (*cb_aread)() */
76 	nodev				/* int (*cb_awrite)() */
77 };
78 
79 /* ARGSUSED3 */
80 static int
81 px_open(dev_t *devp, int flags, int otyp, cred_t *credp)
82 {
83 	px_t *px_p;
84 	int rval;
85 	uint_t orig_px_soft_state;
86 
87 	/*
88 	 * Make sure the open is for the right file type.
89 	 */
90 	if (otyp != OTYP_CHR)
91 		return (EINVAL);
92 
93 	/*
94 	 * Get the soft state structure for the device.
95 	 */
96 	px_p = PX_DEV_TO_SOFTSTATE(*devp);
97 	if (px_p == NULL)
98 		return (ENXIO);
99 
100 	/*
101 	 * Handle the open by tracking the device state.
102 	 */
103 	DBG(DBG_OPEN, px_p->px_dip, "devp=%x: flags=%x\n", devp, flags);
104 	mutex_enter(&px_p->px_mutex);
105 	orig_px_soft_state = px_p->px_soft_state;
106 	if (flags & FEXCL) {
107 		if (px_p->px_soft_state != PX_SOFT_STATE_CLOSED) {
108 			mutex_exit(&px_p->px_mutex);
109 			DBG(DBG_OPEN, px_p->px_dip, "busy\n");
110 			return (EBUSY);
111 		}
112 		px_p->px_soft_state = PX_SOFT_STATE_OPEN_EXCL;
113 	} else {
114 		if (px_p->px_soft_state == PX_SOFT_STATE_OPEN_EXCL) {
115 			mutex_exit(&px_p->px_mutex);
116 			DBG(DBG_OPEN, px_p->px_dip, "busy\n");
117 			return (EBUSY);
118 		}
119 		px_p->px_soft_state = PX_SOFT_STATE_OPEN;
120 	}
121 
122 	if (px_p->px_dev_caps & PX_HOTPLUG_CAPABLE)
123 		if (rval = (pcihp_get_cb_ops())->cb_open(devp, flags,
124 		    otyp, credp)) {
125 			px_p->px_soft_state = orig_px_soft_state;
126 			mutex_exit(&px_p->px_mutex);
127 			return (rval);
128 		}
129 
130 	px_p->px_open_count++;
131 	mutex_exit(&px_p->px_mutex);
132 	return (0);
133 }
134 
135 
136 /* ARGSUSED */
137 static int
138 px_close(dev_t dev, int flags, int otyp, cred_t *credp)
139 {
140 	px_t *px_p;
141 	int rval;
142 
143 	if (otyp != OTYP_CHR)
144 		return (EINVAL);
145 
146 	px_p = PX_DEV_TO_SOFTSTATE(dev);
147 	if (px_p == NULL)
148 		return (ENXIO);
149 
150 	DBG(DBG_CLOSE, px_p->px_dip, "dev=%x: flags=%x\n", dev, flags);
151 	mutex_enter(&px_p->px_mutex);
152 
153 	if (px_p->px_dev_caps & PX_HOTPLUG_CAPABLE)
154 		if (rval = (pcihp_get_cb_ops())->cb_close(dev, flags,
155 		    otyp, credp)) {
156 			mutex_exit(&px_p->px_mutex);
157 			return (rval);
158 		}
159 
160 	px_p->px_soft_state = PX_SOFT_STATE_CLOSED;
161 	px_p->px_open_count = 0;
162 	mutex_exit(&px_p->px_mutex);
163 	return (0);
164 }
165 
166 /* ARGSUSED */
167 static int
168 px_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp, int *rvalp)
169 {
170 	px_t *px_p;
171 	dev_info_t *dip;
172 	struct devctl_iocdata *dcp;
173 	uint_t bus_state;
174 	int rv = DDI_SUCCESS;
175 	int minor = getminor(dev);
176 
177 	px_p = PX_DEV_TO_SOFTSTATE(dev);
178 	if (px_p == NULL)
179 		return (ENXIO);
180 
181 	dip = px_p->px_dip;
182 	DBG(DBG_IOCTL, dip, "dev=%x: cmd=%x\n", dev, cmd);
183 
184 #ifdef	PX_DMA_TEST
185 	if (IS_DMATEST(cmd)) {
186 		*rvalp = px_dma_test(cmd, dip, px_p, arg);
187 		return (0);
188 	}
189 #endif	/* PX_DMA_TEST */
190 
191 	switch (PCIHP_AP_MINOR_NUM_TO_PCI_DEVNUM(minor)) {
192 
193 	/*
194 	 * PCI tools.
195 	 */
196 	case PCI_TOOL_REG_MINOR_NUM:
197 
198 		switch (cmd) {
199 		case PCITOOL_DEVICE_SET_REG:
200 		case PCITOOL_DEVICE_GET_REG:
201 
202 			/* Require full privileges. */
203 			if (secpolicy_kmdb(credp))
204 				rv = EPERM;
205 			else
206 				rv = pxtool_dev_reg_ops(dip,
207 				    (void *)arg, cmd, mode);
208 			break;
209 
210 		case PCITOOL_NEXUS_SET_REG:
211 		case PCITOOL_NEXUS_GET_REG:
212 
213 			/* Require full privileges. */
214 			if (secpolicy_kmdb(credp))
215 				rv = EPERM;
216 			else
217 				rv = pxtool_bus_reg_ops(dip,
218 				    (void *)arg, cmd, mode);
219 			break;
220 
221 		default:
222 			rv = ENOTTY;
223 		}
224 		return (rv);
225 
226 	case PCI_TOOL_INTR_MINOR_NUM:
227 
228 		switch (cmd) {
229 		case PCITOOL_DEVICE_SET_INTR:
230 
231 		/*
232 		 * Require PRIV_SYS_RES_CONFIG,
233 		 * same as psradm
234 		 */
235 		if (secpolicy_ponline(credp)) {
236 			rv = EPERM;
237 			break;
238 		}
239 
240 		/*FALLTHRU*/
241 		/* These require no special privileges. */
242 		case PCITOOL_DEVICE_GET_INTR:
243 		case PCITOOL_DEVICE_NUM_INTR:
244 			rv = pxtool_intr(dip, (void *)arg, cmd, mode);
245 			break;
246 
247 		default:
248 			rv = ENOTTY;
249 		}
250 		return (rv);
251 
252 	default:
253 		if (px_p->px_dev_caps & PX_HOTPLUG_CAPABLE)
254 			return ((pcihp_get_cb_ops())->cb_ioctl(dev, cmd,
255 			    arg, mode, credp, rvalp));
256 		break;
257 	}
258 
259 	if ((cmd & ~PPMREQ_MASK) == PPMREQ) {
260 
261 		/* Need privileges to use these ioctls. */
262 		if (drv_priv(credp)) {
263 			DBG(DBG_TOOLS, dip,
264 			    "px_tools: Insufficient privileges\n");
265 
266 			return (EPERM);
267 		}
268 		return (px_lib_pmctl(cmd, px_p));
269 	}
270 
271 	/*
272 	 * We can use the generic implementation for these ioctls
273 	 */
274 	switch (cmd) {
275 	case DEVCTL_DEVICE_GETSTATE:
276 	case DEVCTL_DEVICE_ONLINE:
277 	case DEVCTL_DEVICE_OFFLINE:
278 	case DEVCTL_BUS_GETSTATE:
279 		return (ndi_devctl_ioctl(dip, cmd, arg, mode, 0));
280 	}
281 
282 	/*
283 	 * read devctl ioctl data
284 	 */
285 	if (ndi_dc_allochdl((void *)arg, &dcp) != NDI_SUCCESS)
286 		return (EFAULT);
287 
288 	switch (cmd) {
289 
290 	case DEVCTL_DEVICE_RESET:
291 		DBG(DBG_IOCTL, dip, "DEVCTL_DEVICE_RESET\n");
292 		rv = ENOTSUP;
293 		break;
294 
295 
296 	case DEVCTL_BUS_QUIESCE:
297 		DBG(DBG_IOCTL, dip, "DEVCTL_BUS_QUIESCE\n");
298 		if (ndi_get_bus_state(dip, &bus_state) == NDI_SUCCESS)
299 			if (bus_state == BUS_QUIESCED)
300 				break;
301 		(void) ndi_set_bus_state(dip, BUS_QUIESCED);
302 		break;
303 
304 	case DEVCTL_BUS_UNQUIESCE:
305 		DBG(DBG_IOCTL, dip, "DEVCTL_BUS_UNQUIESCE\n");
306 		if (ndi_get_bus_state(dip, &bus_state) == NDI_SUCCESS)
307 			if (bus_state == BUS_ACTIVE)
308 				break;
309 		(void) ndi_set_bus_state(dip, BUS_ACTIVE);
310 		break;
311 
312 	case DEVCTL_BUS_RESET:
313 		DBG(DBG_IOCTL, dip, "DEVCTL_BUS_RESET\n");
314 		rv = ENOTSUP;
315 		break;
316 
317 	case DEVCTL_BUS_RESETALL:
318 		DBG(DBG_IOCTL, dip, "DEVCTL_BUS_RESETALL\n");
319 		rv = ENOTSUP;
320 		break;
321 
322 	default:
323 		rv = ENOTTY;
324 	}
325 
326 	ndi_dc_freehdl(dcp);
327 	return (rv);
328 }
329 
330 static int px_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op,
331     int flags, char *name, caddr_t valuep, int *lengthp)
332 {
333 	if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
334 	    "hotplug-capable"))
335 		return ((pcihp_get_cb_ops())->cb_prop_op(dev, dip,
336 		    prop_op, flags, name, valuep, lengthp));
337 
338 	return (ddi_prop_op(dev, dip, prop_op, flags, name, valuep, lengthp));
339 }
340