1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_PRIVREGS_H 28 #define _SYS_PRIVREGS_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" /* from SunOS psl.h 1.2 */ 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* 37 * This file is kernel isa dependent. 38 */ 39 40 #include <sys/fsr.h> 41 #include <v9/sys/asi.h> 42 43 /* 44 * This file describes the cpu's privileged register set, and 45 * how the machine state is saved on the stack when a trap occurs. 46 */ 47 48 #ifndef _ASM 49 50 struct regs { 51 long long r_tstate; 52 long long r_g1; /* user global regs */ 53 long long r_g2; 54 long long r_g3; 55 long long r_g4; 56 long long r_g5; 57 long long r_g6; 58 long long r_g7; 59 long long r_o0; 60 long long r_o1; 61 long long r_o2; 62 long long r_o3; 63 long long r_o4; 64 long long r_o5; 65 long long r_o6; 66 long long r_o7; 67 /* 68 * These are still 32b in 4u's v8/v9 hybrid 69 */ 70 long r_pc; /* program counter */ 71 long r_npc; /* next program counter */ 72 int r_y; /* the y register */ 73 }; 74 75 #define r_ps r_tstate 76 #define r_sp r_o6 77 78 #endif /* _ASM */ 79 80 #ifdef _KERNEL 81 82 #define lwptoregs(lwp) ((struct regs *)((lwp)->lwp_regs)) 83 #define lwptofpu(lwp) ((kfpu_t *)((lwp)->lwp_fpu)) 84 85 /* 86 * Macros for saving/restoring registers. 87 */ 88 89 #define SAVE_GLOBALS(RP) \ 90 stx %g1, [RP + G1_OFF]; \ 91 stx %g2, [RP + G2_OFF]; \ 92 stx %g3, [RP + G3_OFF]; \ 93 stx %g4, [RP + G4_OFF]; \ 94 stx %g5, [RP + G5_OFF]; \ 95 stx %g6, [RP + G6_OFF]; \ 96 stx %g7, [RP + G7_OFF]; \ 97 mov %y, %g1; \ 98 st %g1, [RP + Y_OFF]; 99 100 #define RESTORE_GLOBALS(RP) \ 101 ld [RP + Y_OFF], %g1; \ 102 mov %g1, %y; \ 103 ldx [RP + G1_OFF], %g1; \ 104 ldx [RP + G2_OFF], %g2; \ 105 ldx [RP + G3_OFF], %g3; \ 106 ldx [RP + G4_OFF], %g4; \ 107 ldx [RP + G5_OFF], %g5; \ 108 ldx [RP + G6_OFF], %g6; \ 109 ldx [RP + G7_OFF], %g7; 110 111 #define SAVE_OUTS(RP) \ 112 stx %i0, [RP + O0_OFF]; \ 113 stx %i1, [RP + O1_OFF]; \ 114 stx %i2, [RP + O2_OFF]; \ 115 stx %i3, [RP + O3_OFF]; \ 116 stx %i4, [RP + O4_OFF]; \ 117 stx %i5, [RP + O5_OFF]; \ 118 stx %i6, [RP + O6_OFF]; \ 119 stx %i7, [RP + O7_OFF]; 120 121 #define RESTORE_OUTS(RP) \ 122 ldx [RP + O0_OFF], %i0; \ 123 ldx [RP + O1_OFF], %i1; \ 124 ldx [RP + O2_OFF], %i2; \ 125 ldx [RP + O3_OFF], %i3; \ 126 ldx [RP + O4_OFF], %i4; \ 127 ldx [RP + O5_OFF], %i5; \ 128 ldx [RP + O6_OFF], %i6; \ 129 ldx [RP + O7_OFF], %i7; 130 131 #define SAVE_V8WINDOW(SBP) \ 132 st %l0, [SBP + (0*4)]; \ 133 st %l1, [SBP + (1*4)]; \ 134 st %l2, [SBP + (2*4)]; \ 135 st %l3, [SBP + (3*4)]; \ 136 st %l4, [SBP + (4*4)]; \ 137 st %l5, [SBP + (5*4)]; \ 138 st %l6, [SBP + (6*4)]; \ 139 st %l7, [SBP + (7*4)]; \ 140 st %i0, [SBP + (8*4)]; \ 141 st %i1, [SBP + (9*4)]; \ 142 st %i2, [SBP + (10*4)]; \ 143 st %i3, [SBP + (11*4)]; \ 144 st %i4, [SBP + (12*4)]; \ 145 st %i5, [SBP + (13*4)]; \ 146 st %i6, [SBP + (14*4)]; \ 147 st %i7, [SBP + (15*4)]; 148 149 #define SAVE_V8WINDOW_ASI(SBP) \ 150 sta %l0, [SBP + (0*4)]%asi; \ 151 sta %l1, [SBP + (1*4)]%asi; \ 152 sta %l2, [SBP + (2*4)]%asi; \ 153 sta %l3, [SBP + (3*4)]%asi; \ 154 sta %l4, [SBP + (4*4)]%asi; \ 155 sta %l5, [SBP + (5*4)]%asi; \ 156 sta %l6, [SBP + (6*4)]%asi; \ 157 sta %l7, [SBP + (7*4)]%asi; \ 158 sta %i0, [SBP + (8*4)]%asi; \ 159 sta %i1, [SBP + (9*4)]%asi; \ 160 sta %i2, [SBP + (10*4)]%asi; \ 161 sta %i3, [SBP + (11*4)]%asi; \ 162 sta %i4, [SBP + (12*4)]%asi; \ 163 sta %i5, [SBP + (13*4)]%asi; \ 164 sta %i6, [SBP + (14*4)]%asi; \ 165 sta %i7, [SBP + (15*4)]%asi; 166 167 #define RESTORE_V8WINDOW(SBP) \ 168 ld [SBP + (0*4)], %l0; \ 169 ld [SBP + (1*4)], %l1; \ 170 ld [SBP + (2*4)], %l2; \ 171 ld [SBP + (3*4)], %l3; \ 172 ld [SBP + (4*4)], %l4; \ 173 ld [SBP + (5*4)], %l5; \ 174 ld [SBP + (6*4)], %l6; \ 175 ld [SBP + (7*4)], %l7; \ 176 ld [SBP + (8*4)], %i0; \ 177 ld [SBP + (9*4)], %i1; \ 178 ld [SBP + (10*4)], %i2; \ 179 ld [SBP + (11*4)], %i3; \ 180 ld [SBP + (12*4)], %i4; \ 181 ld [SBP + (13*4)], %i5; \ 182 ld [SBP + (14*4)], %i6; \ 183 ld [SBP + (15*4)], %i7; 184 185 #define SAVE_V9WINDOW(SBP) \ 186 stx %l0, [SBP + (0*8)]; \ 187 stx %l1, [SBP + (1*8)]; \ 188 stx %l2, [SBP + (2*8)]; \ 189 stx %l3, [SBP + (3*8)]; \ 190 stx %l4, [SBP + (4*8)]; \ 191 stx %l5, [SBP + (5*8)]; \ 192 stx %l6, [SBP + (6*8)]; \ 193 stx %l7, [SBP + (7*8)]; \ 194 stx %i0, [SBP + (8*8)]; \ 195 stx %i1, [SBP + (9*8)]; \ 196 stx %i2, [SBP + (10*8)]; \ 197 stx %i3, [SBP + (11*8)]; \ 198 stx %i4, [SBP + (12*8)]; \ 199 stx %i5, [SBP + (13*8)]; \ 200 stx %i6, [SBP + (14*8)]; \ 201 stx %i7, [SBP + (15*8)]; 202 203 #define SAVE_V9WINDOW_ASI(SBP) \ 204 stxa %l0, [SBP + (0*8)]%asi; \ 205 stxa %l1, [SBP + (1*8)]%asi; \ 206 stxa %l2, [SBP + (2*8)]%asi; \ 207 stxa %l3, [SBP + (3*8)]%asi; \ 208 stxa %l4, [SBP + (4*8)]%asi; \ 209 stxa %l5, [SBP + (5*8)]%asi; \ 210 stxa %l6, [SBP + (6*8)]%asi; \ 211 stxa %l7, [SBP + (7*8)]%asi; \ 212 stxa %i0, [SBP + (8*8)]%asi; \ 213 stxa %i1, [SBP + (9*8)]%asi; \ 214 stxa %i2, [SBP + (10*8)]%asi; \ 215 stxa %i3, [SBP + (11*8)]%asi; \ 216 stxa %i4, [SBP + (12*8)]%asi; \ 217 stxa %i5, [SBP + (13*8)]%asi; \ 218 stxa %i6, [SBP + (14*8)]%asi; \ 219 stxa %i7, [SBP + (15*8)]%asi; 220 221 #define RESTORE_V9WINDOW(SBP) \ 222 ldx [SBP + (0*8)], %l0; \ 223 ldx [SBP + (1*8)], %l1; \ 224 ldx [SBP + (2*8)], %l2; \ 225 ldx [SBP + (3*8)], %l3; \ 226 ldx [SBP + (4*8)], %l4; \ 227 ldx [SBP + (5*8)], %l5; \ 228 ldx [SBP + (6*8)], %l6; \ 229 ldx [SBP + (7*8)], %l7; \ 230 ldx [SBP + (8*8)], %i0; \ 231 ldx [SBP + (9*8)], %i1; \ 232 ldx [SBP + (10*8)], %i2; \ 233 ldx [SBP + (11*8)], %i3; \ 234 ldx [SBP + (12*8)], %i4; \ 235 ldx [SBP + (13*8)], %i5; \ 236 ldx [SBP + (14*8)], %i6; \ 237 ldx [SBP + (15*8)], %i7; 238 239 #define STORE_FPREGS(FP) \ 240 std %f0, [FP]; \ 241 std %f2, [FP + 8]; \ 242 std %f4, [FP + 16]; \ 243 std %f6, [FP + 24]; \ 244 std %f8, [FP + 32]; \ 245 std %f10, [FP + 40]; \ 246 std %f12, [FP + 48]; \ 247 std %f14, [FP + 56]; \ 248 std %f16, [FP + 64]; \ 249 std %f18, [FP + 72]; \ 250 std %f20, [FP + 80]; \ 251 std %f22, [FP + 88]; \ 252 std %f24, [FP + 96]; \ 253 std %f26, [FP + 104]; \ 254 std %f28, [FP + 112]; \ 255 std %f30, [FP + 120]; \ 256 std %d32, [FP + 128]; \ 257 std %d34, [FP + 136]; \ 258 std %d36, [FP + 144]; \ 259 std %d38, [FP + 152]; \ 260 std %d40, [FP + 160]; \ 261 std %d42, [FP + 168]; \ 262 std %d44, [FP + 176]; \ 263 std %d46, [FP + 184]; \ 264 std %d48, [FP + 192]; \ 265 std %d50, [FP + 200]; \ 266 std %d52, [FP + 208]; \ 267 std %d54, [FP + 216]; \ 268 std %d56, [FP + 224]; \ 269 std %d58, [FP + 232]; \ 270 std %d60, [FP + 240]; \ 271 std %d62, [FP + 248]; 272 273 #define LOAD_FPREGS(FP) \ 274 ldd [FP], %f0; \ 275 ldd [FP + 8], %f2; \ 276 ldd [FP + 16], %f4; \ 277 ldd [FP + 24], %f6; \ 278 ldd [FP + 32], %f8; \ 279 ldd [FP + 40], %f10; \ 280 ldd [FP + 48], %f12; \ 281 ldd [FP + 56], %f14; \ 282 ldd [FP + 64], %f16; \ 283 ldd [FP + 72], %f18; \ 284 ldd [FP + 80], %f20; \ 285 ldd [FP + 88], %f22; \ 286 ldd [FP + 96], %f24; \ 287 ldd [FP + 104], %f26; \ 288 ldd [FP + 112], %f28; \ 289 ldd [FP + 120], %f30; \ 290 ldd [FP + 128], %d32; \ 291 ldd [FP + 136], %d34; \ 292 ldd [FP + 144], %d36; \ 293 ldd [FP + 152], %d38; \ 294 ldd [FP + 160], %d40; \ 295 ldd [FP + 168], %d42; \ 296 ldd [FP + 176], %d44; \ 297 ldd [FP + 184], %d46; \ 298 ldd [FP + 192], %d48; \ 299 ldd [FP + 200], %d50; \ 300 ldd [FP + 208], %d52; \ 301 ldd [FP + 216], %d54; \ 302 ldd [FP + 224], %d56; \ 303 ldd [FP + 232], %d58; \ 304 ldd [FP + 240], %d60; \ 305 ldd [FP + 248], %d62; 306 307 #define STORE_DL_FPREGS(FP) \ 308 std %f0, [FP]; \ 309 std %f2, [FP + 8]; \ 310 std %f4, [FP + 16]; \ 311 std %f6, [FP + 24]; \ 312 std %f8, [FP + 32]; \ 313 std %f10, [FP + 40]; \ 314 std %f12, [FP + 48]; \ 315 std %f14, [FP + 56]; \ 316 std %f16, [FP + 64]; \ 317 std %f18, [FP + 72]; \ 318 std %f20, [FP + 80]; \ 319 std %f22, [FP + 88]; \ 320 std %f24, [FP + 96]; \ 321 std %f26, [FP + 104]; \ 322 std %f28, [FP + 112]; \ 323 std %f30, [FP + 120]; 324 325 #define STORE_DU_FPREGS(FP) \ 326 std %d32, [FP + 128]; \ 327 std %d34, [FP + 136]; \ 328 std %d36, [FP + 144]; \ 329 std %d38, [FP + 152]; \ 330 std %d40, [FP + 160]; \ 331 std %d42, [FP + 168]; \ 332 std %d44, [FP + 176]; \ 333 std %d46, [FP + 184]; \ 334 std %d48, [FP + 192]; \ 335 std %d50, [FP + 200]; \ 336 std %d52, [FP + 208]; \ 337 std %d54, [FP + 216]; \ 338 std %d56, [FP + 224]; \ 339 std %d58, [FP + 232]; \ 340 std %d60, [FP + 240]; \ 341 std %d62, [FP + 248]; 342 343 #define LOAD_DL_FPREGS(FP) \ 344 ldd [FP], %f0; \ 345 ldd [FP + 8], %f2; \ 346 ldd [FP + 16], %f4; \ 347 ldd [FP + 24], %f6; \ 348 ldd [FP + 32], %f8; \ 349 ldd [FP + 40], %f10; \ 350 ldd [FP + 48], %f12; \ 351 ldd [FP + 56], %f14; \ 352 ldd [FP + 64], %f16; \ 353 ldd [FP + 72], %f18; \ 354 ldd [FP + 80], %f20; \ 355 ldd [FP + 88], %f22; \ 356 ldd [FP + 96], %f24; \ 357 ldd [FP + 104], %f26; \ 358 ldd [FP + 112], %f28; \ 359 ldd [FP + 120], %f30; 360 361 #define LOAD_DU_FPREGS(FP) \ 362 ldd [FP + 128], %d32; \ 363 ldd [FP + 136], %d34; \ 364 ldd [FP + 144], %d36; \ 365 ldd [FP + 152], %d38; \ 366 ldd [FP + 160], %d40; \ 367 ldd [FP + 168], %d42; \ 368 ldd [FP + 176], %d44; \ 369 ldd [FP + 184], %d46; \ 370 ldd [FP + 192], %d48; \ 371 ldd [FP + 200], %d50; \ 372 ldd [FP + 208], %d52; \ 373 ldd [FP + 216], %d54; \ 374 ldd [FP + 224], %d56; \ 375 ldd [FP + 232], %d58; \ 376 ldd [FP + 240], %d60; \ 377 ldd [FP + 248], %d62; 378 379 #endif /* _KERNEL */ 380 381 /* 382 * V9 privileged registers 383 */ 384 385 /* 386 * Condition Codes Register (CCR) 387 * 388 * |-------------------------------| 389 * | XCC | ICC | 390 * | N | Z | V | C | N | Z | V | C | 391 * |---|---|---|---|---|---|---|---| 392 * 7 6 5 4 3 2 1 0 393 */ 394 #define CCR_IC 0x01 /* 32b carry */ 395 #define CCR_IV 0x02 /* 32b overflow */ 396 #define CCR_IZ 0x04 /* 32b zero */ 397 #define CCR_IN 0x08 /* 32b negative */ 398 #define CCR_XC 0x10 /* 64b carry */ 399 #define CCR_XV 0x20 /* 64b overflow */ 400 #define CCR_XZ 0x40 /* 64b zero */ 401 #define CCR_XN 0x80 /* 64b negative */ 402 #define CCR_ICC 0x0F 403 #define CCR_XCC 0xF0 404 405 406 /* 407 * Processor State Register (PSTATE) 408 * 409 * |-------------------------------------------------------------| 410 * | IG | MG | CLE | TLE | MM | RED | PEF | AM | PRIV | IE | AG | 411 * |-----|----|-----|-----|----|-----|-----|----|------|----|----| 412 * 11 10 9 8 7 6 5 4 3 2 1 0 413 * 414 * Note that the IG, MG, RED and AG fields are not applicable to sun4v 415 * compliant processors. 416 */ 417 #ifndef GLREG 418 #define PSTATE_AG 0x001 /* alternate globals */ 419 #endif /* GLREG */ 420 421 #define PSTATE_IE 0x002 /* interrupt enable */ 422 #define PSTATE_PRIV 0x004 /* privileged mode */ 423 #define PSTATE_AM 0x008 /* use 32b address mask */ 424 #define PSTATE_PEF 0x010 /* fp enable */ 425 426 #ifndef GLREG 427 #define PSTATE_RED 0x020 /* red mode */ 428 #endif /* GLREG */ 429 430 #define PSTATE_MM 0x0C0 /* memory model */ 431 #define PSTATE_TLE 0x100 /* trap little endian */ 432 #define PSTATE_CLE 0x200 /* current little endian */ 433 434 #ifndef GLREG 435 #define PSTATE_MG 0x400 /* MMU globals */ 436 #define PSTATE_IG 0x800 /* interrupt globals */ 437 #endif /* GLREG */ 438 439 #define PSTATE_BITS \ 440 "\020\014IG\013MG\012CLE\011TLE\010MM-RMO\ 441 \07MM-PSO\06RED\05PEF\04AM\03PRIV\02IE\01AG" 442 443 /* 444 * Definition of MM (Memory Mode) bit field of pstate. 445 */ 446 #define PSTATE_MM_TSO 0x00 /* total store odering */ 447 #define PSTATE_MM_PSO 0x40 /* partial store odering */ 448 #define PSTATE_MM_RMO 0x80 /* relaxed memory ordering */ 449 450 451 /* 452 * Trap State Register (TSTATE) 453 * 454 * |------------------------------------------| 455 * | GL | CCR | ASI | --- | PSTATE | -- | CWP | 456 * |----|-----|-----|-----|--------|----|-----| 457 * 42 40 39 32 31 24 23 20 19 8 7 5 4 0 458 * 459 * Note that the GL field is applicable to sun4v compliant processors only. 460 */ 461 #define TSTATE_CWP_MASK 0x01F 462 #define TSTATE_CWP_SHIFT 0 463 #define TSTATE_PSTATE_MASK 0xFFF 464 #define TSTATE_PSTATE_SHIFT 8 465 #define TSTATE_ASI_MASK 0x0FF 466 #define TSTATE_ASI_SHIFT 24 467 #define TSTATE_CCR_MASK 0x0FF 468 #define TSTATE_CCR_SHIFT 32 469 470 #ifdef GLREG 471 #define TSTATE_GL_MASK 0x7 472 #define TSTATE_GL_SHIFT 40 473 #endif /* GLREG */ 474 475 /* 476 * Some handy tstate macros 477 */ 478 #define TSTATE_AG (PSTATE_AG << TSTATE_PSTATE_SHIFT) 479 #define TSTATE_IE (PSTATE_IE << TSTATE_PSTATE_SHIFT) 480 #define TSTATE_PRIV (PSTATE_PRIV << TSTATE_PSTATE_SHIFT) 481 #define TSTATE_AM (PSTATE_AM << TSTATE_PSTATE_SHIFT) 482 #define TSTATE_PEF (PSTATE_PEF << TSTATE_PSTATE_SHIFT) 483 #define TSTATE_MG (PSTATE_MG << TSTATE_PSTATE_SHIFT) 484 #define TSTATE_IG (PSTATE_IG << TSTATE_PSTATE_SHIFT) 485 #define TSTATE_CWP TSTATE_CWP_MASK 486 487 /* 488 * as is 64b, but cc is 32b, so we need this hack. 489 */ 490 #ifndef _ASM 491 #define TSTATE_ICC ((long long)CCR_ICC << TSTATE_CCR_SHIFT) 492 #define TSTATE_IC ((long long)CCR_IC << TSTATE_CCR_SHIFT) 493 #define TSTATE_IV ((long long)CCR_IV << TSTATE_CCR_SHIFT) 494 #define TSTATE_XV ((long long)CCR_XV << TSTATE_CCR_SHIFT) 495 #else 496 #define TSTATE_ICC (CCR_ICC << TSTATE_CCR_SHIFT) 497 #define TSTATE_IC (CCR_IC << TSTATE_CCR_SHIFT) 498 #define TSTATE_IV (CCR_IV << TSTATE_CCR_SHIFT) 499 #define TSTATE_XV (CCR_XV << TSTATE_CCR_SHIFT) 500 #endif 501 #define TSTATE_V8_UBITS (TSTATE_ICC | TSTATE_PEF) 502 503 /* 504 * Initial kernel and user %tstate. 505 */ 506 #define PTSTATE_KERN_COMMON \ 507 (PSTATE_PRIV | PSTATE_PEF | PSTATE_MM_TSO) 508 509 #define TSTATE_USER_COMMON \ 510 (PSTATE_IE | PSTATE_PEF | PSTATE_MM_TSO) 511 512 #define TSTATE_KERN \ 513 (PTSTATE_KERN_COMMON << TSTATE_PSTATE_SHIFT) 514 515 #define PSTATE_KERN \ 516 (PTSTATE_KERN_COMMON | PSTATE_PRIV | PSTATE_IE) 517 518 #define TSTATE_USER32 \ 519 (((TSTATE_USER_COMMON | PSTATE_AM) << TSTATE_PSTATE_SHIFT) | \ 520 ((long long)ASI_PNF << TSTATE_ASI_SHIFT)) 521 522 #define TSTATE_USER64 \ 523 ((TSTATE_USER_COMMON << TSTATE_PSTATE_SHIFT) | \ 524 ((long long)ASI_PNF << TSTATE_ASI_SHIFT)) 525 526 #define USERMODE(x) (!((x) & TSTATE_PRIV)) 527 528 /* 529 * Window State Register (WSTATE) 530 * 531 * |------------| 532 * |OTHER|NORMAL| 533 * |-----|------| 534 * 5 3 2 0 535 */ 536 #define WSTATE_BAD 0 /* unused */ 537 #define WSTATE_U32 1 /* 32b stack */ 538 #define WSTATE_U64 2 /* 64b stack */ 539 #define WSTATE_CLEAN32 3 /* cleanwin workaround, 32b stack */ 540 #define WSTATE_CLEAN64 4 /* cleanwin workaround, 64b stack */ 541 #define WSTATE_K32 5 /* priv 32b stack */ 542 #define WSTATE_K64 6 /* priv 64b stack */ 543 #define WSTATE_KMIX 7 /* priv mixed stack */ 544 545 #define WSTATE_CLEAN_OFFSET 2 546 #define WSTATE_SHIFT 3 /* normal-to-other shift */ 547 #define WSTATE_MASK 7 /* mask for each set */ 548 #define WSTATE(o, n) (((o) << WSTATE_SHIFT) | (n)) 549 550 #define WSTATE_USER32 WSTATE(WSTATE_BAD, WSTATE_U32) 551 #define WSTATE_USER64 WSTATE(WSTATE_BAD, WSTATE_U64) 552 #define WSTATE_KERN WSTATE(WSTATE_U32, WSTATE_K64) 553 554 /* 555 * Processor Interrupt Level Register (PIL) 556 * 557 * |-----| 558 * | PIL | 559 * |-----| 560 * 3 0 561 */ 562 563 /* 564 * Version Register (VER) 565 * 566 * |-------------------------------------------------| 567 * | manuf | impl | mask | ---- | maxtl | - | maxwin | 568 * |-------|------|------|------|-------|---|--------| 569 * 63 48 47 32 31 24 23 16 15 8 7 5 4 0 570 */ 571 #define VER_MANUF 0xFFFF000000000000 572 #define VER_IMPL 0x0000FFFF00000000 573 #define VER_MASK 0x00000000FF000000 574 #define VER_MAXTL 0x000000000000FF00 575 #define VER_MAXWIN 0x000000000000001F 576 #define VER_MAXTL_SHIFT 8 577 #define VER_MAXTL_MASK (VER_MAXTL >> VER_MAXTL_SHIFT) 578 579 /* 580 * Tick Register (TICK) 581 * 582 * |---------------| 583 * | npt | counter | 584 * |-----|---------| 585 * 63 62 0 586 * 587 * Note: UltraSparc III Stick register has the same layout. When 588 * present, we clear it too. 589 */ 590 591 #define TICK_NPT 0x8000000000000000 592 #define TICK_COUNTER 0x7FFFFFFFFFFFFFFF 593 594 #ifdef __cplusplus 595 } 596 #endif 597 598 #endif /* _SYS_PRIVREGS_H */ 599