1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_CPU_H 27 #define _SYS_CPU_H 28 29 /* 30 * Include generic bustype cookies. 31 */ 32 #include <sys/bustypes.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 /* 39 * Global kernel variables of interest 40 */ 41 42 #if defined(_KERNEL) && !defined(_ASM) 43 44 extern int dvmasize; /* usable dvma size in pages */ 45 46 /* 47 * Cache defines 48 * 49 * Each bit represents an attribute of the system's caches that 50 * the OS must handle. For example, VAC caches must have virtual 51 * alias detection, VTAG caches must be flushed on every demap, etc. 52 */ 53 #define CACHE_NONE 0 /* No caches of any type */ 54 #define CACHE_VAC 0x01 /* Virtual addressed cache */ 55 #define CACHE_VTAG 0x02 /* Virtual tagged cache */ 56 #define CACHE_PAC 0x04 /* Physical addressed cache */ 57 #define CACHE_PTAG 0x08 /* Physical tagged cache */ 58 #define CACHE_WRITEBACK 0x10 /* Writeback cache */ 59 #define CACHE_IOCOHERENT 0x20 /* I/O coherent cache */ 60 61 extern int cache; 62 63 /* set this to zero if no vac */ 64 extern int vac; 65 66 /* 67 * Use to insert cpu-dependent instructions into spin loops 68 */ 69 #pragma weak cpu_smt_pause 70 extern void cpu_smt_pause(); 71 #define SMT_PAUSE() { if (&cpu_smt_pause) cpu_smt_pause(); } 72 73 /* 74 * used to preload L2 cache 75 */ 76 #if !defined(__lint) && defined(__GNUC__) 77 78 extern __inline__ void 79 prefetch64(caddr_t addr) 80 { 81 __asm__ __volatile__( 82 "prefetch [%0], #n_writes\n\t" 83 : "=r" (addr) 84 : "0" (addr)); 85 } 86 87 #endif /* !__lint && __GNUC__ */ 88 89 #endif /* defined(_KERNEL) && !defined(_ASM) */ 90 91 #ifdef __cplusplus 92 } 93 #endif 94 95 #endif /* _SYS_CPU_H */ 96