1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved. 23 */ 24 /* 25 * Copyright (c) 2010, Intel Corporation. 26 * All rights reserved. 27 */ 28 29 #ifndef _SYS_X86_ARCHEXT_H 30 #define _SYS_X86_ARCHEXT_H 31 32 #if !defined(_ASM) 33 #include <sys/regset.h> 34 #include <sys/processor.h> 35 #include <vm/seg_enum.h> 36 #include <vm/page.h> 37 #endif /* _ASM */ 38 39 #ifdef __cplusplus 40 extern "C" { 41 #endif 42 43 /* 44 * cpuid instruction feature flags in %edx (standard function 1) 45 */ 46 47 #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */ 48 #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */ 49 #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */ 50 #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */ 51 #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */ 52 #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 53 #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */ 54 #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */ 55 #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 56 #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */ 57 /* 0x400 - reserved */ 58 #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */ 59 #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */ 60 #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */ 61 #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */ 62 #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */ 63 #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */ 64 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 65 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */ 66 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */ 67 /* 0x100000 - reserved */ 68 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */ 69 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */ 70 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */ 71 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 72 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */ 73 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */ 74 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */ 75 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */ 76 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */ 77 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */ 78 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */ 79 80 #define FMT_CPUID_INTC_EDX \ 81 "\20" \ 82 "\40pbe\37ia64\36tm\35htt\34ss\33sse2\32sse\31fxsr" \ 83 "\30mmx\27acpi\26ds\24clfsh\23psn\22pse36\21pat" \ 84 "\20cmov\17mca\16pge\15mtrr\14sep\12apic\11cx8" \ 85 "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu" 86 87 /* 88 * cpuid instruction feature flags in %ecx (standard function 1) 89 */ 90 91 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */ 92 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */ 93 /* 0x00000004 - reserved */ 94 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */ 95 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */ 96 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */ 97 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */ 98 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */ 99 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */ 100 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */ 101 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */ 102 /* 0x00000800 - reserved */ 103 /* 0x00001000 - reserved */ 104 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */ 105 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */ 106 /* 0x00008000 - reserved */ 107 /* 0x00010000 - reserved */ 108 /* 0x00020000 - reserved */ 109 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */ 110 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */ 111 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */ 112 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */ 113 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */ 114 #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */ 115 #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */ 116 #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */ 117 #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */ 118 119 #define FMT_CPUID_INTC_ECX \ 120 "\20" \ 121 "\35avx\34osxsav\33xsave" \ 122 "\32aes" \ 123 "\30popcnt\27movbe\25sse4.2\24sse4.1\23dca" \ 124 "\20\17etprd\16cx16\13cid\12ssse3\11tm2" \ 125 "\10est\7smx\6vmx\5dscpl\4mon\2pclmulqdq\1sse3" 126 127 /* 128 * cpuid instruction feature flags in %edx (extended function 0x80000001) 129 */ 130 131 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */ 132 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */ 133 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */ 134 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */ 135 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */ 136 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 137 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */ 138 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */ 139 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 140 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */ 141 /* 0x00000400 - sysc on K6m6 */ 142 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */ 143 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */ 144 #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */ 145 #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */ 146 #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */ 147 #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */ 148 #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */ 149 #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 150 /* 0x00040000 - reserved */ 151 /* 0x00080000 - reserved */ 152 #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */ 153 /* 0x00200000 - reserved */ 154 #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */ 155 #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */ 156 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 157 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */ 158 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */ 159 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */ 160 /* 0x10000000 - reserved */ 161 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */ 162 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */ 163 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */ 164 165 #define FMT_CPUID_AMD_EDX \ 166 "\20" \ 167 "\40a3d\37a3d+\36lm\34tscp\32ffxsr\31fxsr" \ 168 "\30mmx\27mmxext\25nx\22pse\21pat" \ 169 "\20cmov\17mca\16pge\15mtrr\14syscall\12apic\11cx8" \ 170 "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu" 171 172 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */ 173 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */ 174 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */ 175 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */ 176 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */ 177 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */ 178 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */ 179 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */ 180 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */ 181 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */ 182 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */ 183 #define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: SSE5 */ 184 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */ 185 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */ 186 187 #define FMT_CPUID_AMD_ECX \ 188 "\20" \ 189 "\14wdt\13skinit\12sse5\11ibs\10osvw\93dnp\8mas" \ 190 "\7sse4a\6lzcnt\5cr8d\3svm\2lcmplgcy\1ahf64" 191 192 /* 193 * Intel now seems to have claimed part of the "extended" function 194 * space that we previously for non-Intel implementors to use. 195 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF 196 * is available in long mode i.e. what AMD indicate using bit 0. 197 * On the other hand, everything else is labelled as reserved. 198 */ 199 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */ 200 201 202 #define P5_MCHADDR 0x0 203 #define P5_CESR 0x11 204 #define P5_CTR0 0x12 205 #define P5_CTR1 0x13 206 207 #define K5_MCHADDR 0x0 208 #define K5_MCHTYPE 0x01 209 #define K5_TSC 0x10 210 #define K5_TR12 0x12 211 212 #define REG_PAT 0x277 213 214 #define REG_MC0_CTL 0x400 215 #define REG_MC5_MISC 0x417 216 #define REG_PERFCTR0 0xc1 217 #define REG_PERFCTR1 0xc2 218 219 #define REG_PERFEVNT0 0x186 220 #define REG_PERFEVNT1 0x187 221 222 #define REG_TSC 0x10 /* timestamp counter */ 223 #define REG_APIC_BASE_MSR 0x1b 224 #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */ 225 226 #if !defined(__xpv) 227 /* 228 * AMD C1E 229 */ 230 #define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055 231 #define AMD_ACTONCMPHALT_SHIFT 27 232 #define AMD_ACTONCMPHALT_MASK 3 233 #endif 234 235 #define MSR_DEBUGCTL 0x1d9 236 237 #define DEBUGCTL_LBR 0x01 238 #define DEBUGCTL_BTF 0x02 239 240 /* Intel P6, AMD */ 241 #define MSR_LBR_FROM 0x1db 242 #define MSR_LBR_TO 0x1dc 243 #define MSR_LEX_FROM 0x1dd 244 #define MSR_LEX_TO 0x1de 245 246 /* Intel P4 (pre-Prescott, non P4 M) */ 247 #define MSR_P4_LBSTK_TOS 0x1da 248 #define MSR_P4_LBSTK_0 0x1db 249 #define MSR_P4_LBSTK_1 0x1dc 250 #define MSR_P4_LBSTK_2 0x1dd 251 #define MSR_P4_LBSTK_3 0x1de 252 253 /* Intel Pentium M */ 254 #define MSR_P6M_LBSTK_TOS 0x1c9 255 #define MSR_P6M_LBSTK_0 0x040 256 #define MSR_P6M_LBSTK_1 0x041 257 #define MSR_P6M_LBSTK_2 0x042 258 #define MSR_P6M_LBSTK_3 0x043 259 #define MSR_P6M_LBSTK_4 0x044 260 #define MSR_P6M_LBSTK_5 0x045 261 #define MSR_P6M_LBSTK_6 0x046 262 #define MSR_P6M_LBSTK_7 0x047 263 264 /* Intel P4 (Prescott) */ 265 #define MSR_PRP4_LBSTK_TOS 0x1da 266 #define MSR_PRP4_LBSTK_FROM_0 0x680 267 #define MSR_PRP4_LBSTK_FROM_1 0x681 268 #define MSR_PRP4_LBSTK_FROM_2 0x682 269 #define MSR_PRP4_LBSTK_FROM_3 0x683 270 #define MSR_PRP4_LBSTK_FROM_4 0x684 271 #define MSR_PRP4_LBSTK_FROM_5 0x685 272 #define MSR_PRP4_LBSTK_FROM_6 0x686 273 #define MSR_PRP4_LBSTK_FROM_7 0x687 274 #define MSR_PRP4_LBSTK_FROM_8 0x688 275 #define MSR_PRP4_LBSTK_FROM_9 0x689 276 #define MSR_PRP4_LBSTK_FROM_10 0x68a 277 #define MSR_PRP4_LBSTK_FROM_11 0x68b 278 #define MSR_PRP4_LBSTK_FROM_12 0x68c 279 #define MSR_PRP4_LBSTK_FROM_13 0x68d 280 #define MSR_PRP4_LBSTK_FROM_14 0x68e 281 #define MSR_PRP4_LBSTK_FROM_15 0x68f 282 #define MSR_PRP4_LBSTK_TO_0 0x6c0 283 #define MSR_PRP4_LBSTK_TO_1 0x6c1 284 #define MSR_PRP4_LBSTK_TO_2 0x6c2 285 #define MSR_PRP4_LBSTK_TO_3 0x6c3 286 #define MSR_PRP4_LBSTK_TO_4 0x6c4 287 #define MSR_PRP4_LBSTK_TO_5 0x6c5 288 #define MSR_PRP4_LBSTK_TO_6 0x6c6 289 #define MSR_PRP4_LBSTK_TO_7 0x6c7 290 #define MSR_PRP4_LBSTK_TO_8 0x6c8 291 #define MSR_PRP4_LBSTK_TO_9 0x6c9 292 #define MSR_PRP4_LBSTK_TO_10 0x6ca 293 #define MSR_PRP4_LBSTK_TO_11 0x6cb 294 #define MSR_PRP4_LBSTK_TO_12 0x6cc 295 #define MSR_PRP4_LBSTK_TO_13 0x6cd 296 #define MSR_PRP4_LBSTK_TO_14 0x6ce 297 #define MSR_PRP4_LBSTK_TO_15 0x6cf 298 299 #define MCI_CTL_VALUE 0xffffffff 300 301 #define MTRR_TYPE_UC 0 302 #define MTRR_TYPE_WC 1 303 #define MTRR_TYPE_WT 4 304 #define MTRR_TYPE_WP 5 305 #define MTRR_TYPE_WB 6 306 #define MTRR_TYPE_UC_ 7 307 308 /* 309 * For Solaris we set up the page attritubute table in the following way: 310 * PAT0 Write-Back 311 * PAT1 Write-Through 312 * PAT2 Unchacheable- 313 * PAT3 Uncacheable 314 * PAT4 Write-Back 315 * PAT5 Write-Through 316 * PAT6 Write-Combine 317 * PAT7 Uncacheable 318 * The only difference from h/w default is entry 6. 319 */ 320 #define PAT_DEFAULT_ATTRIBUTE \ 321 ((uint64_t)MTRR_TYPE_WB | \ 322 ((uint64_t)MTRR_TYPE_WT << 8) | \ 323 ((uint64_t)MTRR_TYPE_UC_ << 16) | \ 324 ((uint64_t)MTRR_TYPE_UC << 24) | \ 325 ((uint64_t)MTRR_TYPE_WB << 32) | \ 326 ((uint64_t)MTRR_TYPE_WT << 40) | \ 327 ((uint64_t)MTRR_TYPE_WC << 48) | \ 328 ((uint64_t)MTRR_TYPE_UC << 56)) 329 330 #define X86FSET_LARGEPAGE 0 331 #define X86FSET_TSC 1 332 #define X86FSET_MSR 2 333 #define X86FSET_MTRR 3 334 #define X86FSET_PGE 4 335 #define X86FSET_DE 5 336 #define X86FSET_CMOV 6 337 #define X86FSET_MMX 7 338 #define X86FSET_MCA 8 339 #define X86FSET_PAE 9 340 #define X86FSET_CX8 10 341 #define X86FSET_PAT 11 342 #define X86FSET_SEP 12 343 #define X86FSET_SSE 13 344 #define X86FSET_SSE2 14 345 #define X86FSET_HTT 15 346 #define X86FSET_ASYSC 16 347 #define X86FSET_NX 17 348 #define X86FSET_SSE3 18 349 #define X86FSET_CX16 19 350 #define X86FSET_CMP 20 351 #define X86FSET_TSCP 21 352 #define X86FSET_MWAIT 22 353 #define X86FSET_SSE4A 23 354 #define X86FSET_CPUID 24 355 #define X86FSET_SSSE3 25 356 #define X86FSET_SSE4_1 26 357 #define X86FSET_SSE4_2 27 358 #define X86FSET_1GPG 28 359 #define X86FSET_CLFSH 29 360 #define X86FSET_64 30 361 #define X86FSET_AES 31 362 #define X86FSET_PCLMULQDQ 32 363 #define X86FSET_XSAVE 33 364 #define X86FSET_AVX 34 365 366 /* 367 * flags to patch tsc_read routine. 368 */ 369 #define X86_NO_TSC 0x0 370 #define X86_HAVE_TSCP 0x1 371 #define X86_TSC_MFENCE 0x2 372 #define X86_TSC_LFENCE 0x4 373 374 /* 375 * Intel Deep C-State invariant TSC in leaf 0x80000007. 376 */ 377 #define CPUID_TSC_CSTATE_INVARIANCE (0x100) 378 379 /* 380 * Intel Deep C-state always-running local APIC timer 381 */ 382 #define CPUID_CSTATE_ARAT (0x4) 383 384 /* 385 * Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3]. 386 */ 387 #define CPUID_EPB_SUPPORT (1 << 3) 388 389 /* 390 * Intel TSC deadline timer 391 */ 392 #define CPUID_DEADLINE_TSC (1 << 24) 393 394 /* 395 * x86_type is a legacy concept; this is supplanted 396 * for most purposes by x86_featureset; modern CPUs 397 * should be X86_TYPE_OTHER 398 */ 399 #define X86_TYPE_OTHER 0 400 #define X86_TYPE_486 1 401 #define X86_TYPE_P5 2 402 #define X86_TYPE_P6 3 403 #define X86_TYPE_CYRIX_486 4 404 #define X86_TYPE_CYRIX_6x86L 5 405 #define X86_TYPE_CYRIX_6x86 6 406 #define X86_TYPE_CYRIX_GXm 7 407 #define X86_TYPE_CYRIX_6x86MX 8 408 #define X86_TYPE_CYRIX_MediaGX 9 409 #define X86_TYPE_CYRIX_MII 10 410 #define X86_TYPE_VIA_CYRIX_III 11 411 #define X86_TYPE_P4 12 412 413 /* 414 * x86_vendor allows us to select between 415 * implementation features and helps guide 416 * the interpretation of the cpuid instruction. 417 */ 418 #define X86_VENDOR_Intel 0 419 #define X86_VENDORSTR_Intel "GenuineIntel" 420 421 #define X86_VENDOR_IntelClone 1 422 423 #define X86_VENDOR_AMD 2 424 #define X86_VENDORSTR_AMD "AuthenticAMD" 425 426 #define X86_VENDOR_Cyrix 3 427 #define X86_VENDORSTR_CYRIX "CyrixInstead" 428 429 #define X86_VENDOR_UMC 4 430 #define X86_VENDORSTR_UMC "UMC UMC UMC " 431 432 #define X86_VENDOR_NexGen 5 433 #define X86_VENDORSTR_NexGen "NexGenDriven" 434 435 #define X86_VENDOR_Centaur 6 436 #define X86_VENDORSTR_Centaur "CentaurHauls" 437 438 #define X86_VENDOR_Rise 7 439 #define X86_VENDORSTR_Rise "RiseRiseRise" 440 441 #define X86_VENDOR_SiS 8 442 #define X86_VENDORSTR_SiS "SiS SiS SiS " 443 444 #define X86_VENDOR_TM 9 445 #define X86_VENDORSTR_TM "GenuineTMx86" 446 447 #define X86_VENDOR_NSC 10 448 #define X86_VENDORSTR_NSC "Geode by NSC" 449 450 /* 451 * Vendor string max len + \0 452 */ 453 #define X86_VENDOR_STRLEN 13 454 455 /* 456 * Some vendor/family/model/stepping ranges are commonly grouped under 457 * a single identifying banner by the vendor. The following encode 458 * that "revision" in a uint32_t with the 8 most significant bits 459 * identifying the vendor with X86_VENDOR_*, the next 8 identifying the 460 * family, and the remaining 16 typically forming a bitmask of revisions 461 * within that family with more significant bits indicating "later" revisions. 462 */ 463 464 #define _X86_CHIPREV_VENDOR_MASK 0xff000000u 465 #define _X86_CHIPREV_VENDOR_SHIFT 24 466 #define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u 467 #define _X86_CHIPREV_FAMILY_SHIFT 16 468 #define _X86_CHIPREV_REV_MASK 0x0000ffffu 469 470 #define _X86_CHIPREV_VENDOR(x) \ 471 (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT) 472 #define _X86_CHIPREV_FAMILY(x) \ 473 (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT) 474 #define _X86_CHIPREV_REV(x) \ 475 ((x) & _X86_CHIPREV_REV_MASK) 476 477 /* True if x matches in vendor and family and if x matches the given rev mask */ 478 #define X86_CHIPREV_MATCH(x, mask) \ 479 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \ 480 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \ 481 ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0)) 482 483 /* True if x matches in vendor and family, and rev is at least minx */ 484 #define X86_CHIPREV_ATLEAST(x, minx) \ 485 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 486 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \ 487 _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx)) 488 489 #define _X86_CHIPREV_MKREV(vendor, family, rev) \ 490 ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \ 491 (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev)) 492 493 /* True if x matches in vendor, and family is at least minx */ 494 #define X86_CHIPFAM_ATLEAST(x, minx) \ 495 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 496 _X86_CHIPREV_FAMILY(x) >= _X86_CHIPREV_FAMILY(minx)) 497 498 /* Revision default */ 499 #define X86_CHIPREV_UNKNOWN 0x0 500 501 /* 502 * Definitions for AMD Family 0xf. Minor revisions C0 and CG are 503 * sufficiently different that we will distinguish them; in all other 504 * case we will identify the major revision. 505 */ 506 #define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001) 507 #define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002) 508 #define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004) 509 #define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008) 510 #define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010) 511 #define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020) 512 #define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040) 513 514 /* 515 * Definitions for AMD Family 0x10. Rev A was Engineering Samples only. 516 */ 517 #define X86_CHIPREV_AMD_10_REV_A \ 518 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001) 519 #define X86_CHIPREV_AMD_10_REV_B \ 520 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002) 521 #define X86_CHIPREV_AMD_10_REV_C \ 522 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004) 523 #define X86_CHIPREV_AMD_10_REV_D \ 524 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0008) 525 526 /* 527 * Definitions for AMD Family 0x11. 528 */ 529 #define X86_CHIPREV_AMD_11 \ 530 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0001) 531 532 533 /* 534 * Various socket/package types, extended as the need to distinguish 535 * a new type arises. The top 8 byte identfies the vendor and the 536 * remaining 24 bits describe 24 socket types. 537 */ 538 539 #define _X86_SOCKET_VENDOR_SHIFT 24 540 #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT) 541 #define _X86_SOCKET_TYPE_MASK 0x00ffffff 542 #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK) 543 544 #define _X86_SOCKET_MKVAL(vendor, bitval) \ 545 ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval)) 546 547 #define X86_SOCKET_MATCH(s, mask) \ 548 (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \ 549 (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0) 550 551 #define X86_SOCKET_UNKNOWN 0x0 552 /* 553 * AMD socket types 554 */ 555 #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000001) 556 #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000002) 557 #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000004) 558 #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000008) 559 #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000010) 560 #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000020) 561 #define X86_SOCKET_S1g2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000040) 562 #define X86_SOCKET_S1g3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000080) 563 #define X86_SOCKET_AM _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000100) 564 #define X86_SOCKET_AM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000200) 565 #define X86_SOCKET_AM3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000400) 566 #define X86_SOCKET_G34 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000800) 567 #define X86_SOCKET_ASB2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x001000) 568 #define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x002000) 569 570 /* 571 * xgetbv/xsetbv support 572 */ 573 574 #define XFEATURE_ENABLED_MASK 0x0 575 /* 576 * XFEATURE_ENABLED_MASK values (eax) 577 */ 578 #define XFEATURE_LEGACY_FP 0x1 579 #define XFEATURE_SSE 0x2 580 #define XFEATURE_AVX 0x4 581 #define XFEATURE_MAX XFEATURE_AVX 582 #define XFEATURE_FP_ALL (XFEATURE_LEGACY_FP|XFEATURE_SSE|XFEATURE_AVX) 583 584 #if !defined(_ASM) 585 586 #if defined(_KERNEL) || defined(_KMEMUSER) 587 588 #define NUM_X86_FEATURES 35 589 extern uchar_t x86_featureset[]; 590 591 extern void free_x86_featureset(void *featureset); 592 extern boolean_t is_x86_feature(void *featureset, uint_t feature); 593 extern void add_x86_feature(void *featureset, uint_t feature); 594 extern void remove_x86_feature(void *featureset, uint_t feature); 595 extern boolean_t compare_x86_featureset(void *setA, void *setB); 596 extern void print_x86_featureset(void *featureset); 597 598 599 extern uint_t x86_type; 600 extern uint_t x86_vendor; 601 extern uint_t x86_clflush_size; 602 603 extern uint_t pentiumpro_bug4046376; 604 extern uint_t pentiumpro_bug4064495; 605 606 extern uint_t enable486; 607 608 extern const char CyrixInstead[]; 609 610 #endif 611 612 #if defined(_KERNEL) 613 614 /* 615 * This structure is used to pass arguments and get return values back 616 * from the CPUID instruction in __cpuid_insn() routine. 617 */ 618 struct cpuid_regs { 619 uint32_t cp_eax; 620 uint32_t cp_ebx; 621 uint32_t cp_ecx; 622 uint32_t cp_edx; 623 }; 624 625 /* 626 * Utility functions to get/set extended control registers (XCR) 627 * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK. 628 */ 629 extern uint64_t get_xcr(uint_t); 630 extern void set_xcr(uint_t, uint64_t); 631 632 extern uint64_t rdmsr(uint_t); 633 extern void wrmsr(uint_t, const uint64_t); 634 extern uint64_t xrdmsr(uint_t); 635 extern void xwrmsr(uint_t, const uint64_t); 636 extern int checked_rdmsr(uint_t, uint64_t *); 637 extern int checked_wrmsr(uint_t, uint64_t); 638 639 extern void invalidate_cache(void); 640 extern ulong_t getcr4(void); 641 extern void setcr4(ulong_t); 642 643 extern void mtrr_sync(void); 644 645 extern void cpu_fast_syscall_enable(void *); 646 extern void cpu_fast_syscall_disable(void *); 647 648 struct cpu; 649 650 extern int cpuid_checkpass(struct cpu *, int); 651 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *); 652 extern uint32_t __cpuid_insn(struct cpuid_regs *); 653 extern int cpuid_getbrandstr(struct cpu *, char *, size_t); 654 extern int cpuid_getidstr(struct cpu *, char *, size_t); 655 extern const char *cpuid_getvendorstr(struct cpu *); 656 extern uint_t cpuid_getvendor(struct cpu *); 657 extern uint_t cpuid_getfamily(struct cpu *); 658 extern uint_t cpuid_getmodel(struct cpu *); 659 extern uint_t cpuid_getstep(struct cpu *); 660 extern uint_t cpuid_getsig(struct cpu *); 661 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *); 662 extern uint_t cpuid_get_ncore_per_chip(struct cpu *); 663 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *); 664 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *); 665 extern int cpuid_get_chipid(struct cpu *); 666 extern id_t cpuid_get_coreid(struct cpu *); 667 extern int cpuid_get_pkgcoreid(struct cpu *); 668 extern int cpuid_get_clogid(struct cpu *); 669 extern int cpuid_get_cacheid(struct cpu *); 670 extern uint32_t cpuid_get_apicid(struct cpu *); 671 extern uint_t cpuid_get_procnodeid(struct cpu *cpu); 672 extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu); 673 extern int cpuid_is_cmt(struct cpu *); 674 extern int cpuid_syscall32_insn(struct cpu *); 675 extern int getl2cacheinfo(struct cpu *, int *, int *, int *); 676 677 extern uint32_t cpuid_getchiprev(struct cpu *); 678 extern const char *cpuid_getchiprevstr(struct cpu *); 679 extern uint32_t cpuid_getsockettype(struct cpu *); 680 extern const char *cpuid_getsocketstr(struct cpu *); 681 682 extern int cpuid_have_cr8access(struct cpu *); 683 684 extern int cpuid_opteron_erratum(struct cpu *, uint_t); 685 686 struct cpuid_info; 687 688 extern void setx86isalist(void); 689 extern void cpuid_alloc_space(struct cpu *); 690 extern void cpuid_free_space(struct cpu *); 691 extern void cpuid_pass1(struct cpu *, uchar_t *); 692 extern void cpuid_pass2(struct cpu *); 693 extern void cpuid_pass3(struct cpu *); 694 extern uint_t cpuid_pass4(struct cpu *); 695 extern void cpuid_set_cpu_properties(void *, processorid_t, 696 struct cpuid_info *); 697 698 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *); 699 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t); 700 701 #if !defined(__xpv) 702 extern uint32_t *cpuid_mwait_alloc(struct cpu *); 703 extern void cpuid_mwait_free(struct cpu *); 704 extern int cpuid_deep_cstates_supported(void); 705 extern int cpuid_arat_supported(void); 706 extern int cpuid_iepb_supported(struct cpu *); 707 extern int cpuid_deadline_tsc_supported(void); 708 extern int vmware_platform(void); 709 #endif 710 711 struct cpu_ucode_info; 712 713 extern void ucode_alloc_space(struct cpu *); 714 extern void ucode_free_space(struct cpu *); 715 extern void ucode_check(struct cpu *); 716 extern void ucode_cleanup(); 717 718 #if !defined(__xpv) 719 extern char _tsc_mfence_start; 720 extern char _tsc_mfence_end; 721 extern char _tscp_start; 722 extern char _tscp_end; 723 extern char _no_rdtsc_start; 724 extern char _no_rdtsc_end; 725 extern char _tsc_lfence_start; 726 extern char _tsc_lfence_end; 727 #endif 728 729 #if !defined(__xpv) 730 extern char bcopy_patch_start; 731 extern char bcopy_patch_end; 732 extern char bcopy_ck_size; 733 #endif 734 735 extern void post_startup_cpu_fixups(void); 736 737 extern uint_t workaround_errata(struct cpu *); 738 739 #if defined(OPTERON_ERRATUM_93) 740 extern int opteron_erratum_93; 741 #endif 742 743 #if defined(OPTERON_ERRATUM_91) 744 extern int opteron_erratum_91; 745 #endif 746 747 #if defined(OPTERON_ERRATUM_100) 748 extern int opteron_erratum_100; 749 #endif 750 751 #if defined(OPTERON_ERRATUM_121) 752 extern int opteron_erratum_121; 753 #endif 754 755 #if defined(OPTERON_WORKAROUND_6323525) 756 extern int opteron_workaround_6323525; 757 extern void patch_workaround_6323525(void); 758 #endif 759 760 extern int get_hwenv(void); 761 extern int is_controldom(void); 762 763 extern void xsave_setup_msr(struct cpu *); 764 765 /* 766 * Defined hardware environments 767 */ 768 #define HW_NATIVE 0x00 /* Running on bare metal */ 769 #define HW_XEN_PV 0x01 /* Running on Xen Hypervisor paravirutualized */ 770 #define HW_XEN_HVM 0x02 /* Running on Xen hypervisor HVM */ 771 #define HW_VMWARE 0x03 /* Running on VMware hypervisor */ 772 773 #endif /* _KERNEL */ 774 775 #endif 776 777 #ifdef __cplusplus 778 } 779 #endif 780 781 #endif /* _SYS_X86_ARCHEXT_H */ 782