17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 57712e92cSsudheer * Common Development and Distribution License (the "License"). 67712e92cSsudheer * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 2107a48826SRoger A. Faulkner 227c478bd9Sstevel@tonic-gate /* 23*7af88ac7SKuriakose Kuruvilla * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved. 247c478bd9Sstevel@tonic-gate */ 257c478bd9Sstevel@tonic-gate 267c478bd9Sstevel@tonic-gate #ifndef _SYS_PCB_H 277c478bd9Sstevel@tonic-gate #define _SYS_PCB_H 287c478bd9Sstevel@tonic-gate 297c478bd9Sstevel@tonic-gate #include <sys/regset.h> 307c478bd9Sstevel@tonic-gate #include <sys/segments.h> 317c478bd9Sstevel@tonic-gate 327c478bd9Sstevel@tonic-gate #ifdef __cplusplus 337c478bd9Sstevel@tonic-gate extern "C" { 347c478bd9Sstevel@tonic-gate #endif 357c478bd9Sstevel@tonic-gate 367c478bd9Sstevel@tonic-gate #ifndef _ASM 377c478bd9Sstevel@tonic-gate typedef struct fpu_ctx { 387c478bd9Sstevel@tonic-gate kfpu_t fpu_regs; /* kernel save area for FPU */ 39*7af88ac7SKuriakose Kuruvilla uint64_t fpu_xsave_mask; /* xsave mask for FPU/SSE/AVX */ 40*7af88ac7SKuriakose Kuruvilla #if defined(__i386) 41*7af88ac7SKuriakose Kuruvilla uint64_t fpu_padding; /* fix 32bit libmicro regression */ 42*7af88ac7SKuriakose Kuruvilla #endif 437c478bd9Sstevel@tonic-gate uint_t fpu_flags; /* FPU state flags */ 447c478bd9Sstevel@tonic-gate } fpu_ctx_t; 457c478bd9Sstevel@tonic-gate 467c478bd9Sstevel@tonic-gate typedef struct pcb { 477c478bd9Sstevel@tonic-gate fpu_ctx_t pcb_fpu; /* fpu state */ 487c478bd9Sstevel@tonic-gate uint_t pcb_flags; /* state flags; cleared on fork */ 497c478bd9Sstevel@tonic-gate greg_t pcb_drstat; /* status debug register (%dr6) */ 507c478bd9Sstevel@tonic-gate unsigned char pcb_instr; /* /proc: instruction at stop */ 517c478bd9Sstevel@tonic-gate #if defined(__amd64) 527712e92cSsudheer unsigned char pcb_rupdate; /* new register values in pcb -> regs */ 537c478bd9Sstevel@tonic-gate uintptr_t pcb_fsbase; 547c478bd9Sstevel@tonic-gate uintptr_t pcb_gsbase; 557c478bd9Sstevel@tonic-gate selector_t pcb_ds; 567c478bd9Sstevel@tonic-gate selector_t pcb_es; 577c478bd9Sstevel@tonic-gate selector_t pcb_fs; 587c478bd9Sstevel@tonic-gate selector_t pcb_gs; 597c478bd9Sstevel@tonic-gate #endif /* __amd64 */ 607c478bd9Sstevel@tonic-gate user_desc_t pcb_fsdesc; /* private per-lwp %fs descriptors */ 617c478bd9Sstevel@tonic-gate user_desc_t pcb_gsdesc; /* private per-lwp %gs descriptors */ 627c478bd9Sstevel@tonic-gate } pcb_t; 637c478bd9Sstevel@tonic-gate 647c478bd9Sstevel@tonic-gate #endif /* ! _ASM */ 657c478bd9Sstevel@tonic-gate 667c478bd9Sstevel@tonic-gate /* pcb_flags */ 677c478bd9Sstevel@tonic-gate #define DEBUG_PENDING 0x02 /* single-step of lcall for a sys call */ 6807a48826SRoger A. Faulkner #define PRSTOP_CALLED 0x04 /* prstop() has been called for this lwp */ 697c478bd9Sstevel@tonic-gate #define INSTR_VALID 0x08 /* value in pcb_instr is valid (/proc) */ 707c478bd9Sstevel@tonic-gate #define NORMAL_STEP 0x10 /* normal debugger-requested single-step */ 717c478bd9Sstevel@tonic-gate #define WATCH_STEP 0x20 /* single-stepping in watchpoint emulation */ 727c478bd9Sstevel@tonic-gate #define CPC_OVERFLOW 0x40 /* performance counters overflowed */ 7365a89a64Smarx #define REQUEST_STEP 0x100 /* request pending to single-step this lwp */ 7465a89a64Smarx #define REQUEST_NOSTEP 0x200 /* request pending to disable single-step */ 7520c794b3Sgavinm #define ASYNC_HWERR 0x400 /* hardware error has corrupted context */ 767c478bd9Sstevel@tonic-gate 777c478bd9Sstevel@tonic-gate /* fpu_flags */ 787c478bd9Sstevel@tonic-gate #define FPU_EN 0x1 /* flag signifying fpu in use */ 797c478bd9Sstevel@tonic-gate #define FPU_VALID 0x2 /* fpu_regs has valid fpu state */ 807c478bd9Sstevel@tonic-gate #define FPU_MODIFIED 0x4 /* fpu_regs is modified (/proc) */ 817c478bd9Sstevel@tonic-gate 827c478bd9Sstevel@tonic-gate #define FPU_INVALID 0x0 /* fpu context is not in use */ 837c478bd9Sstevel@tonic-gate 847c478bd9Sstevel@tonic-gate /* fpu_flags */ 857c478bd9Sstevel@tonic-gate 867c478bd9Sstevel@tonic-gate #ifdef __cplusplus 877c478bd9Sstevel@tonic-gate } 887c478bd9Sstevel@tonic-gate #endif 897c478bd9Sstevel@tonic-gate 907c478bd9Sstevel@tonic-gate #endif /* _SYS_PCB_H */ 91