1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 * 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _MC_AMD_H 27 #define _MC_AMD_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 /* 32 * Definitions describing various memory controller constant properties and 33 * the structure of configuration registers. 34 */ 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 /* 41 * Configuration constants 42 */ 43 #define MC_CHIP_NDIMM 8 /* max dimms per MC */ 44 #define MC_CHIP_NCS 8 /* number of chip-selects per MC */ 45 #define MC_CHIP_DIMMRANKMAX 4 /* largest number of ranks per dimm */ 46 #define MC_CHIP_DIMMPERCS 2 /* max number of dimms per cs */ 47 #define MC_CHIP_DIMMPAIR(csnum) (csnum / MC_CHIP_DIMMPERCS) 48 49 /* 50 * Encoding of chip version variations that we need to distinguish 51 */ 52 #define MC_REV_UNKNOWN -1u /* unknown AMD revision */ 53 #define MC_REV_PRE_D 0 /* B/C/CG */ 54 #define MC_REV_D_E 1 /* D or E */ 55 #define MC_REV_F 2 /* F */ 56 57 /* 58 * BKDG 3.29 section 3.4.4.1 - DRAM base i registers 59 */ 60 #define MC_AM_DB_DRAMBASE_MASK 0xffff0000 61 #define MC_AM_DB_DRAMBASE_LSHFT 8 62 #define MC_AM_DB_DRAMBASE(regval) \ 63 (((uint64_t)(regval) & MC_AM_DB_DRAMBASE_MASK) << \ 64 MC_AM_DB_DRAMBASE_LSHFT) 65 #define MC_AM_DB_INTLVEN_MASK 0x00000700 66 #define MC_AM_DB_INTLVEN_SHIFT 8 67 #define MC_AM_DB_WE 0x00000002 68 #define MC_AM_DB_RE 0x00000001 69 70 /* 71 * BKDG 3.29 section 3.4.4.2 - DRAM limit i registers 72 */ 73 #define MC_AM_DL_DRAMLIM_MASK 0xffff0000 74 #define MC_AM_DL_DRAMLIM_SHIFT 16 75 #define MC_AM_DL_DRAMLIM_LSHFT 8 76 #define MC_AM_DL_DRAMLIM(regval) \ 77 ((((uint64_t)(regval) & MC_AM_DL_DRAMLIM_MASK) << \ 78 MC_AM_DL_DRAMLIM_LSHFT) | ((regval) ? \ 79 ((1 << (MC_AM_DL_DRAMLIM_SHIFT + MC_AM_DL_DRAMLIM_LSHFT)) - 1) : 0)) 80 #define MC_AM_DL_INTLVSEL_MASK 0x00000700 81 #define MC_AM_DL_INTLVSEL_SHIFT 8 82 #define MC_AM_DL_DSTNODE_MASK 0x00000007 83 84 /* 85 * BKDG 3.29 section 3.5.4 - DRAM CS Base Address Registers. 86 * 87 * MC_DC_CSB_CSBASE combines the BaseAddrHi and BaseAddrLo into a single 88 * uint64_t, shifting them into the dram address bits they describe. 89 */ 90 #define MC_DC_CSB_BASEHI_MASK 0xffe00000 91 #define MC_DC_CSB_BASEHI_LSHFT 4 92 93 #define MC_DC_CSB_BASELO_MASK 0x0000fe00 94 #define MC_DC_CSB_BASELO_LSHFT 4 95 96 #define MC_DC_CSB_CSBASE(regval) \ 97 ((((uint64_t)(regval) & MC_DC_CSB_BASEHI_MASK) << \ 98 MC_DC_CSB_BASEHI_LSHFT) | (((uint64_t)(regval) & \ 99 MC_DC_CSB_BASELO_MASK) << MC_DC_CSB_BASELO_LSHFT)) 100 101 #define MC_DC_CSB_CSBE 0x00000001 102 103 /* 104 * BKDG 3.29 section 3.5.5 - DRAM CS Mask Registers. 105 * 106 * MC_DC_CSM_CSMASK combines the AddrMaskHi and AddrMaskLo into a single 107 * uint64_t, shifting them into the dram address bit positions they mask. 108 * It also fills the gaps between high and low mask and below the low mask. 109 * MC_DC_CSM_UNMASKED_BITS indicates the number of high dram address bits 110 * above MC_DC_CSM_MASKHI_HIBIT that cannot be masked. 111 */ 112 #define MC_DC_CSM_MASKHI_MASK 0x3fe00000 113 #define MC_DC_CSM_MASKHI_LSHFT 4 114 #define MC_DC_CSM_MASKHI_LOBIT 25 115 #define MC_DC_CSM_MASKHI_HIBIT 33 116 117 #define MC_DC_CSM_MASKLO_MASK 0x0000fe00 118 #define MC_DC_CSM_MASKLO_LOBIT 13 119 #define MC_DC_CSM_MASKLO_HIBIT 19 120 #define MC_DC_CSM_MASKLO_LSHFT 4 121 122 #define MC_DC_CSM_MASKFILL 0x1f01fff /* [24:20] and [12:0] */ 123 124 #define MC_DC_CSM_UNMASKED_BITS 2 125 126 #define MC_DC_CSM_CSMASK(regval) \ 127 ((((uint64_t)(regval) & MC_DC_CSM_MASKHI_MASK) << \ 128 MC_DC_CSM_MASKHI_LSHFT) | (((uint64_t)(regval) & \ 129 MC_DC_CSM_MASKLO_MASK) << MC_DC_CSM_MASKLO_LSHFT) | \ 130 MC_DC_CSM_MASKFILL) 131 132 /* 133 * BKDG 3.29 section 3.5.6 - DRAM Bank Address Mapping Register 134 */ 135 #define MC_DC_BAM_CSBANK_MASK 0x0000000f 136 #define MC_DC_BAM_CSBANK_SHIFT 4 137 #define MC_DC_BAM_CSBANK_SWIZZLE 0x40000000 138 139 /* 140 * BKDG 3.29 section 3.4.8 - DRAM Hole register, revs E and later 141 */ 142 #define MC_DC_HOLE_VALID 0x00000001 143 #define MC_DC_HOLE_OFFSET_MASK 0x0000ff00 144 #define MC_DC_HOLE_OFFSET_LSHIFT 16 145 146 /* 147 * BKDG 3.29 section 3.5.11 - DRAM configuration high and low registers. 148 * The following defines may be applied to a uint64_t made by 149 * concatenating those two 32-bit registers. 150 */ 151 #define MC_DC_DCFG_DLL_DIS 0x0000000000000001 152 #define MC_DC_DCFG_D_DRV 0x0000000000000002 153 #define MC_DC_DCFG_QFC_EN 0x0000000000000004 154 #define MC_DC_DCFG_DISDQSYS 0x0000000000000008 155 #define MC_DC_DCFG_BURST2OPT 0x0000000000000020 156 #define MC_DC_DCFG_MOD64BITMUX 0x0000000000000040 157 #define MC_DC_DCFG_PWRDWNTRIEN 0x0000000000000080 /* >= rev E */ 158 #define MC_DC_DCFG_SCRATCHBIT 0x0000000000000080 /* <= rev D */ 159 #define MC_DC_DCFG_DRAMINIT 0x0000000000000100 160 #define MC_DC_DCFG_DUALDIMMEN 0x0000000000000200 161 #define MC_DC_DCFG_DRAMENABLE 0x0000000000000400 162 #define MC_DC_DCFG_MEMCLRSTATUS 0x0000000000000800 163 #define MC_DC_DCFG_ESR 0x0000000000001000 164 #define MC_DC_DCFG_SR_S 0x0000000000002000 165 #define MC_DC_DCFG_RDWRQBYP_MASK 0x000000000000c000 166 #define MC_DC_DCFG_128 0x0000000000010000 167 #define MC_DC_DCFG_DIMMECEN 0x0000000000020000 168 #define MC_DC_DCFG_UNBUFFDIMM 0x0000000000040000 169 #define MC_DC_DCFG_32BYTEEN 0x0000000000080000 170 #define MC_DC_DCFG_X4DIMMS_MASK 0x0000000000f00000 171 #define MC_DC_DCFG_X4DIMMS_SHIFT 20 172 #define MC_DC_DCFG_DISINRCVRS 0x0000000001000000 173 #define MC_DC_DCFG_BYPMAX_MASK 0x000000000e000000 174 #define MC_DC_DCFG_EN2T 0x0000000010000000 175 #define MC_DC_DCFG_UPPERCSMAP 0x0000000020000000 176 #define MC_DC_DCFG_PWRDOWNCTL_MASK 0x00000000c0000000 177 #define MC_DC_DCFG_ASYNCLAT_MASK 0x0000000f00000000 178 #define MC_DC_DCFG_RDPREAMBLE_MASK 0x00000f0000000000 179 #define MC_DC_DCFG_MEMDQDRVSTREN_MASK 0x0000600000000000 180 #define MC_DC_DCFG_DISABLEJITTER 0x0000800000000000 181 #define MC_DC_DCFG_ILD_LMT_MASK 0x0007000000000000 182 #define MC_DC_DCFG_ECC_EN 0x0008000000000000 183 #define MC_DC_DCFG_MEMCLK_MASK 0x0070000000000000 184 #define MC_DC_DCFG_MCR 0x0200000000000000 185 #define MC_DC_DCFG_MC0_EN 0x0400000000000000 186 #define MC_DC_DCFG_MC1_EN 0x0800000000000000 187 #define MC_DC_DCFG_MC2_EN 0x1000000000000000 188 #define MC_DC_DCFG_MC3_EN 0x2000000000000000 189 #define MC_DC_DCFG_ODDDIVISORCORRECT 0x8000000000000000 190 191 #ifdef __cplusplus 192 } 193 #endif 194 195 #endif /* _MC_AMD_H */ 196