1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 * 21 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 22 * Use is subject to license terms. 23 */ 24 25 #ifndef _MC_AMD_H 26 #define _MC_AMD_H 27 28 #pragma ident "%Z%%M% %I% %E% SMI" 29 30 #include <sys/mc.h> 31 #include <sys/x86_archext.h> 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 /* 38 * The mc-amd driver exports an nvlist to userland, where the primary 39 * consumer is the "chip" topology enumerator for this platform type which 40 * builds a full topology subtree from this information. Others can use 41 * it, too, but don't depend on it not changing without an ARC contract 42 * (and the contract should probably concern the topology, not this nvlist). 43 * 44 * In the initial mc-amd implementation this nvlist was not versioned; 45 * we'll think of that as version 0 and it may be recognised by the absence 46 * of a "mcamd-nvlist-version member. 47 * 48 * Version 1 is defined as follows. A name in square brackets indicates 49 * that member is optional (only present if the actual value is valid). 50 * 51 * Name Type Description 52 * -------------------- --------------- --------------------------------------- 53 * mcamd-nvlist-version uint8 Exported nvlist version number 54 * num uint64 Chip id of this memory controller 55 * revision uint64 cpuid_getchiprev() result 56 * revname string cpuid_getchiprevstr() result 57 * socket string "Socket 755|939|940|AM2|F(1207)|S1g1" 58 * ecc-type string "ChipKill 128/16" or "Normal 64/8" 59 * base-addr uint64 Node base address 60 * lim-addr uint64 Node limit address 61 * node-ilen uint64 0|1|3|7 for 0/2/4/8 way node interleave 62 * node-ilsel uint64 Node interleave position of this node 63 * cs-intlv-factor uint64 chip-select interleave: 1/2/4/8 64 * dram-hole-size uint64 size in bytes from dram hole addr reg 65 * access-width uint64 MC mode, 64 or 128 bit 66 * bank-mapping uint64 Raw DRAM Bank Address Mapping Register 67 * bankswizzle uint64 1 if bank swizzling enabled; else 0 68 * mismatched-dimm-support uint64 1 if active; else 0 69 * [spare-csnum] uint64 Chip-select pair number of any spare 70 * [bad-csnum] uint64 Chip-select pair number of swapped cs 71 * cslist nvlist array See below; may have 0 members 72 * dimmlist nvlist array See below; may have 0 members 73 * 74 * cslist is an array of nvlist, each as follows: 75 * 76 * Name Type Description 77 * -------------------- --------------- --------------------------------------- 78 * num uint64 Chip-select base/mask pair number 79 * base-addr uint64 Chip-select base address (rel to node) 80 * mask uint64 Chip-select mask 81 * size uint64 Chip-select size in bytes 82 * dimm1-num uint64 First dimm (lodimm if a pair) 83 * dimm1-csname string Socket cs# line name for 1st dimm rank 84 * [dimm2-num] uint64 Second dimm if applicable (updimm) 85 * [dimm2-csname] string Socket cs# line name for 2nd dimm rank 86 * 87 * dimmlist is an array of nvlist, each as follows: 88 * 89 * Name Type Description 90 * -------------------- --------------- --------------------------------------- 91 * num uint64 DIMM instance number 92 * size uint64 DIMM size in bytes 93 * csnums uint64 array CS base/mask pair(s) on this DIMM 94 * csnames string array Socket cs# line name(s) on this DIMM 95 * 96 * The n'th csnums entry corresponds to the n'th csnames entry 97 */ 98 #define MC_NVLIST_VERSTR "mcamd-nvlist-version" 99 #define MC_NVLIST_VERS0 0 100 #define MC_NVLIST_VERS1 1 101 #define MC_NVLIST_VERS MC_NVLIST_VERS1 102 103 /* 104 * Constants and feature/revision test macros that are not expected to vary 105 * among different AMD family 0xf processor revisions. 106 */ 107 108 /* 109 * Configuration constants 110 */ 111 #define MC_CHIP_MAXNODES 8 /* max number of MCs in system */ 112 #define MC_CHIP_NDIMM 8 /* max dimms per MC */ 113 #define MC_CHIP_NCS 8 /* number of chip-selects per MC */ 114 #define MC_CHIP_NDRAMCHAN 2 /* maximum number of dram channels */ 115 #define MC_CHIP_DIMMRANKMAX 4 /* largest number of ranks per dimm */ 116 #define MC_CHIP_DIMMPERCS 2 /* max number of dimms per cs */ 117 #define MC_CHIP_DIMMPAIR(csnum) (csnum / MC_CHIP_DIMMPERCS) 118 119 #if MC_CHIP_DIMMPERCS > MC_UNUM_NDIMM 120 #error "MC_CHIP_DIMMPERCS exceeds MC_UNUM_NDIMM" 121 #endif 122 123 /* 124 * MC_REV_* are used a a convenient shorter form of the X86_CHIPREV 125 * counterparts; these must map directly as we fill mcp_rev from 126 * a cpuid_getchiprev call. 127 */ 128 #define MC_REV_UNKNOWN X86_CHIPREV_UNKNOWN 129 #define MC_REV_B X86_CHIPREV_AMD_F_REV_B 130 #define MC_REV_C (X86_CHIPREV_AMD_F_REV_C0 | X86_CHIPREV_AMD_F_REV_CG) 131 #define MC_REV_D X86_CHIPREV_AMD_F_REV_D 132 #define MC_REV_E X86_CHIPREV_AMD_F_REV_E 133 #define MC_REV_F X86_CHIPREV_AMD_F_REV_F 134 #define MC_REV_G X86_CHIPREV_AMD_F_REV_G 135 136 /* 137 * The most common groupings for memory controller features. 138 */ 139 #define MC_REVS_BC (MC_REV_B | MC_REV_C) 140 #define MC_REVS_DE (MC_REV_D | MC_REV_E) 141 #define MC_REVS_BCDE (MC_REVS_BC | MC_REVS_DE) 142 #define MC_REVS_FG (MC_REV_F | MC_REV_G) 143 144 /* 145 * Is 'rev' included in the 'revmask' bitmask? 146 */ 147 #define MC_REV_MATCH(rev, revmask) X86_CHIPREV_MATCH(rev, revmask) 148 149 /* 150 * Is 'rev' at least revision 'revmin' or greater 151 */ 152 #define MC_REV_ATLEAST(rev, minrev) X86_CHIPREV_ATLEAST(rev, minrev) 153 154 /* 155 * Chip socket types 156 */ 157 #define MC_SKT_UNKNOWN 0x0 158 #define MC_SKT_754 0x1 159 #define MC_SKT_939 0x2 160 #define MC_SKT_940 0x3 161 #define MC_SKT_S1g1 0x4 162 #define MC_SKT_AM2 0x5 163 #define MC_SKT_F1207 0x6 164 165 /* 166 * Memory controller registers are read via PCI config space accesses on 167 * bus 0, device 24 + NodeId, and function as follows: 168 * 169 * Function 0: HyperTransport Technology Configuration 170 * Function 1: Address Map 171 * Function 2: DRAM Controller & HyperTransport Technology Trace Mode 172 * Function 3: Miscellaneous Control 173 * 174 * For a given (bus, device, function) a particular offset selects the 175 * desired register. All registers are 32-bits wide. 176 * 177 * Different family 0xf processor revisions vary slightly in the content 178 * of these configuration registers. The biggest change is with rev F 179 * where DDR2 support has been introduced along with some hardware-controlled 180 * correctable memory error thresholding. Fortunately most of the config info 181 * required by the mc-amd driver is similar across revisions. 182 * 183 * We will try to insulate most of the driver code from config register 184 * details by reading all memory-controller PCI config registers that we 185 * will need at driver attach time for each of functions 0 through 3, and 186 * storing them in a "cooked" form as memory controller properties. 187 * These are to be accessed directly where we have an mc_t to hand, otherwise 188 * through mcamd_get_numprop. As such we expect most/all use of the 189 * structures and macros defined below to be in those attach codepaths. 190 */ 191 192 /* 193 * Registers will be represented as unions, with one fixed-width unsigned 194 * integer member providing access to the raw register value and one or more 195 * structs breaking the register out into bitfields (more than one struct if 196 * the register definitions varies across processor revisions). 197 * 198 * The "raw" union member will always be '_val32'. Use MCREG_VAL32 to 199 * access this member. 200 * 201 * The bitfield structs are all named _fmt_xxx where xxx identifies the 202 * processor revision to which it applies. At this point the only xxx 203 * values in use are: 204 * 'cmn' - applies to all revisions 205 * 'preF' - applies to revisions E and earlier 206 * 'revFG' - applies to revisions F and G 207 * Variants such as 'preD', 'revDE', 'postCG' etc should be introduced 208 * as requirements arise. The MC_REV_* and MC_REV_MATCH etc macros 209 * will also need to grow to match. Use MCREG_FIELD_* to access the 210 * individual bitfields of a register, perhaps using MC_REV_* and MC_REV_MATCH 211 * to decide which revision suffix to provide. Where a bitfield appears 212 * in different revisions but has the same use it should be named identically 213 * (even if the BKDG varies a little) so that the MC_REG_FIELD_* macros 214 * can lookup that member based on revision only. 215 */ 216 217 #define _MCREG_FIELD(up, revsuffix, field) ((up)->_fmt_##revsuffix.field) 218 219 #define MCREG_VAL32(up) ((up)->_val32) 220 221 #define MCREG_FIELD_CMN(up, field) _MCREG_FIELD(up, cmn, field) 222 #define MCREG_FIELD_preF(up, field) _MCREG_FIELD(up, preF, field) 223 #define MCREG_FIELD_revFG(up, field) _MCREG_FIELD(up, revFG, field) 224 225 /* 226 * Function 0 - HT Configuration: Routing Table Node Register 227 */ 228 union mcreg_htroute { 229 uint32_t _val32; 230 struct { 231 uint32_t RQRte:4; /* 3:0 */ 232 uint32_t reserved1:4; /* 7:4 */ 233 uint32_t RPRte:4; /* 11:8 */ 234 uint32_t reserved2:4; /* 15:12 */ 235 uint32_t BCRte:4; /* 19:16 */ 236 uint32_t reserved3:12; /* 31:20 */ 237 } _fmt_cmn; 238 }; 239 240 /* 241 * Function 0 - HT Configuration: Node ID Register 242 */ 243 union mcreg_nodeid { 244 uint32_t _val32; 245 struct { 246 uint32_t NodeId:3; /* 2:0 */ 247 uint32_t reserved1:1; /* 3:3 */ 248 uint32_t NodeCnt:3; /* 6:4 */ 249 uint32_t reserved2:1; /* 7:7 */ 250 uint32_t SbNode:3; /* 10:8 */ 251 uint32_t reserved3:1; /* 11:11 */ 252 uint32_t LkNode:3; /* 14:12 */ 253 uint32_t reserved4:1; /* 15:15 */ 254 uint32_t CpuCnt:4; /* 19:16 */ 255 uint32_t reserved:12; /* 31:20 */ 256 } _fmt_cmn; 257 }; 258 259 #define HT_COHERENTNODES(up) (MCREG_FIELD_CMN(up, NodeCnt) + 1) 260 #define HT_SYSTEMCORECOUNT(up) (MCREG_FIELD_CMN(up, CpuCnt) + 1) 261 262 /* 263 * Function 0 - HT Configuration: Unit ID Register 264 */ 265 union mcreg_unitid { 266 uint32_t _val32; 267 struct { 268 uint32_t C0Unit:2; /* 1:0 */ 269 uint32_t C1Unit:2; /* 3:2 */ 270 uint32_t McUnit:2; /* 5:4 */ 271 uint32_t HbUnit:2; /* 7:6 */ 272 uint32_t SbLink:2; /* 9:8 */ 273 uint32_t reserved:22; /* 31:10 */ 274 } _fmt_cmn; 275 }; 276 277 /* 278 * Function 1 - DRAM Address Map: DRAM Base i Registers 279 * 280 */ 281 282 union mcreg_drambase { 283 uint32_t _val32; 284 struct { 285 uint32_t RE:1; /* 0:0 - Read Enable */ 286 uint32_t WE:1; /* 1:1 - Write Enable */ 287 uint32_t reserved1:6; /* 7:2 */ 288 uint32_t IntlvEn:3; /* 10:8 - Interleave Enable */ 289 uint32_t reserved2:5; /* 15:11 */ 290 uint32_t DRAMBasei:16; /* 31:16 - Base Addr 39:24 */ 291 } _fmt_cmn; 292 }; 293 294 #define MC_DRAMBASE(up) ((uint64_t)MCREG_FIELD_CMN(up, DRAMBasei) << 24) 295 296 /* 297 * Function 1 - DRAM Address Map: DRAM Limit i Registers 298 * 299 */ 300 301 union mcreg_dramlimit { 302 uint32_t _val32; 303 struct { 304 uint32_t DstNode:3; /* 2:0 - Destination Node */ 305 uint32_t reserved1:5; /* 7:3 */ 306 uint32_t IntlvSel:3; /* 10:8 - Interleave Select */ 307 uint32_t reserved2:5; /* 15:11 */ 308 uint32_t DRAMLimiti:16; /* 31:16 - Limit Addr 39:24 */ 309 } _fmt_cmn; 310 }; 311 312 #define MC_DRAMLIM(up) \ 313 ((uint64_t)MCREG_FIELD_CMN(up, DRAMLimiti) << 24 | \ 314 (MCREG_FIELD_CMN(up, DRAMLimiti) ? ((1 << 24) - 1) : 0)) 315 316 /* 317 * Function 1 - DRAM Address Map: DRAM Hole Address Register 318 */ 319 320 union mcreg_dramhole { 321 uint32_t _val32; 322 struct { 323 uint32_t DramHoleValid:1; /* 0:0 */ 324 uint32_t reserved1:7; /* 7:1 */ 325 uint32_t DramHoleOffset:8; /* 15:8 */ 326 uint32_t reserved2:8; /* 23:16 */ 327 uint32_t DramHoleBase:8; /* 31:24 */ 328 } _fmt_cmn; 329 }; 330 331 #define MC_DRAMHOLE_SIZE(up) (MCREG_FIELD_CMN(up, DramHoleOffset) << 24) 332 333 /* 334 * Function 2 - DRAM Controller: DRAM CS Base Address Registers 335 */ 336 337 union mcreg_csbase { 338 uint32_t _val32; 339 /* 340 * Register format in revisions E and earlier 341 */ 342 struct { 343 uint32_t CSEnable:1; /* 0:0 - CS Bank Enable */ 344 uint32_t reserved1:8; /* 8:1 */ 345 uint32_t BaseAddrLo:7; /* 15:9 - Base Addr 19:13 */ 346 uint32_t reserved2:5; /* 20:16 */ 347 uint32_t BaseAddrHi:11; /* 31:21 - Base Addr 35:25 */ 348 } _fmt_preF; 349 /* 350 * Register format in revisions F and G 351 */ 352 struct { 353 uint32_t CSEnable:1; /* 0:0 - CS Bank Enable */ 354 uint32_t Spare:1; /* 1:1 - Spare Rank */ 355 uint32_t TestFail:1; /* 2:2 - Memory Test Failed */ 356 uint32_t reserved1:2; /* 4:3 */ 357 uint32_t BaseAddrLo:9; /* 13:5 - Base Addr 21:13 */ 358 uint32_t reserved2:5; /* 18:14 */ 359 uint32_t BaseAddrHi:10; /* 28:19 - Base Addr 36:27 */ 360 uint32_t reserved3:3; /* 31:39 */ 361 } _fmt_revFG; 362 }; 363 364 #define MC_CSBASE(up, rev) (MC_REV_MATCH(rev, MC_REVS_FG) ? \ 365 (uint64_t)MCREG_FIELD_revFG(up, BaseAddrHi) << 27 | \ 366 (uint64_t)MCREG_FIELD_revFG(up, BaseAddrLo) << 13 : \ 367 (uint64_t)MCREG_FIELD_preF(up, BaseAddrHi) << 25 | \ 368 (uint64_t)MCREG_FIELD_preF(up, BaseAddrLo) << 13) 369 370 /* 371 * Function 2 - DRAM Controller: DRAM CS Mask Registers 372 */ 373 374 union mcreg_csmask { 375 uint32_t _val32; 376 /* 377 * Register format in revisions E and earlier 378 */ 379 struct { 380 uint32_t reserved1:9; /* 8:0 */ 381 uint32_t AddrMaskLo:7; /* 15:9 - Addr Mask 19:13 */ 382 uint32_t reserved2:5; /* 20:16 */ 383 uint32_t AddrMaskHi:9; /* 29:21 - Addr Mask 33:25 */ 384 uint32_t reserved3:2; /* 31:30 */ 385 } _fmt_preF; 386 /* 387 * Register format in revisions F and G 388 */ 389 struct { 390 uint32_t reserved1:5; /* 4:0 */ 391 uint32_t AddrMaskLo:9; /* 13:5 - Addr Mask 21:13 */ 392 uint32_t reserved2:5; /* 18:14 */ 393 uint32_t AddrMaskHi:10; /* 28:19 - Addr Mask 36:27 */ 394 uint32_t reserved3:3; /* 31:29 */ 395 } _fmt_revFG; 396 }; 397 398 #define MC_CSMASKLO_LOBIT(rev) (MC_REV_MATCH(rev, MC_REVS_FG) ? 13 : 13) 399 #define MC_CSMASKLO_HIBIT(rev) (MC_REV_MATCH(rev, MC_REVS_FG) ? 21 : 19) 400 401 #define MC_CSMASKHI_LOBIT(rev) (MC_REV_MATCH(rev, MC_REVS_FG) ? 27 : 25) 402 #define MC_CSMASKHI_HIBIT(rev) (MC_REV_MATCH(rev, MC_REVS_FG) ? 36 : 33) 403 404 #define MC_CSMASK_UNMASKABLE(rev) (MC_REV_MATCH(rev, MC_REVS_FG) ? 0 : 2) 405 406 #define MC_CSMASK(up, rev) (MC_REV_MATCH(rev, MC_REVS_FG) ? \ 407 (uint64_t)MCREG_FIELD_revFG(up, AddrMaskHi) << 27 | \ 408 (uint64_t)MCREG_FIELD_revFG(up, AddrMaskLo) << 13 | 0x7c01fff : \ 409 (uint64_t)MCREG_FIELD_preF(up, AddrMaskHi) << 25 | \ 410 (uint64_t)MCREG_FIELD_preF(up, AddrMaskLo) << 13 | 0x1f01fff) 411 412 /* 413 * Function 2 - DRAM Controller: DRAM Bank Address Mapping Registers 414 */ 415 416 union mcreg_bankaddrmap { 417 uint32_t _val32; 418 /* 419 * Register format in revisions E and earlier 420 */ 421 struct { 422 uint32_t cs10:4; /* 3:0 - CS1/0 */ 423 uint32_t cs32:4; /* 7:4 - CS3/2 */ 424 uint32_t cs54:4; /* 11:8 - CS5/4 */ 425 uint32_t cs76:4; /* 15:12 - CS7/6 */ 426 uint32_t reserved1:14; /* 29:16 */ 427 uint32_t BankSwizzleMode:1; /* 30:30 */ 428 uint32_t reserved2:1; /* 31:31 */ 429 } _fmt_preF; 430 /* 431 * Register format in revisions F and G 432 */ 433 struct { 434 uint32_t cs10:4; /* 3:0 - CS1/0 */ 435 uint32_t cs32:4; /* 7:4 - CS3/2 */ 436 uint32_t cs54:4; /* 11:8 - CS5/4 */ 437 uint32_t cs76:4; /* 15:12 - CS7/6 */ 438 uint32_t reserved1:16; /* 31:16 */ 439 } _fmt_revFG; 440 /* 441 * Accessing all mode encodings as one uint16 442 */ 443 struct { 444 uint32_t allcsmodes:16; /* 15:0 */ 445 uint32_t pad:16; /* 31:16 */ 446 } _fmt_bankmodes; 447 }; 448 449 #define MC_DC_BAM_CSBANK_MASK 0x0000000f 450 #define MC_DC_BAM_CSBANK_SHIFT 4 451 452 #define MC_CSBANKMODE(up, csnum) ((up)->_fmt_bankmodes.allcsmodes >> \ 453 MC_DC_BAM_CSBANK_SHIFT * MC_CHIP_DIMMPAIR(csnum) & MC_DC_BAM_CSBANK_MASK) 454 455 /* 456 * Function 2 - DRAM Controller: DRAM Configuration Low and High 457 */ 458 459 union mcreg_dramcfg_lo { 460 uint32_t _val32; 461 /* 462 * Register format in revisions E and earlier. 463 * Bit 7 is a BIOS ScratchBit in revs D and earlier, 464 * PwrDwnTriEn in revision E; we don't use it so 465 * we'll call it ambig1. 466 */ 467 struct { 468 uint32_t DLL_Dis:1; /* 0 */ 469 uint32_t D_DRV:1; /* 1 */ 470 uint32_t QFC_EN:1; /* 2 */ 471 uint32_t DisDqsHys:1; /* 3 */ 472 uint32_t reserved1:1; /* 4 */ 473 uint32_t Burst2Opt:1; /* 5 */ 474 uint32_t Mod64BitMux:1; /* 6 */ 475 uint32_t ambig1:1; /* 7 */ 476 uint32_t DramInit:1; /* 8 */ 477 uint32_t DualDimmEn:1; /* 9 */ 478 uint32_t DramEnable:1; /* 10 */ 479 uint32_t MemClrStatus:1; /* 11 */ 480 uint32_t ESR:1; /* 12 */ 481 uint32_t SR_S:1; /* 13 */ 482 uint32_t RdWrQByp:2; /* 15:14 */ 483 uint32_t Width128:1; /* 16 */ 484 uint32_t DimmEcEn:1; /* 17 */ 485 uint32_t UnBufDimm:1; /* 18 */ 486 uint32_t ByteEn32:1; /* 19 */ 487 uint32_t x4DIMMs:4; /* 23:20 */ 488 uint32_t DisInRcvrs:1; /* 24 */ 489 uint32_t BypMax:3; /* 27:25 */ 490 uint32_t En2T:1; /* 28 */ 491 uint32_t UpperCSMap:1; /* 29 */ 492 uint32_t PwrDownCtl:2; /* 31:30 */ 493 } _fmt_preF; 494 /* 495 * Register format in revisions F and G 496 */ 497 struct { 498 uint32_t InitDram:1; /* 0 */ 499 uint32_t ExitSelfRef:1; /* 1 */ 500 uint32_t reserved1:2; /* 3:2 */ 501 uint32_t DramTerm:2; /* 5:4 */ 502 uint32_t reserved2:1; /* 6 */ 503 uint32_t DramDrvWeak:1; /* 7 */ 504 uint32_t ParEn:1; /* 8 */ 505 uint32_t SelRefRateEn:1; /* 9 */ 506 uint32_t BurstLength32:1; /* 10 */ 507 uint32_t Width128:1; /* 11 */ 508 uint32_t x4DIMMs:4; /* 15:12 */ 509 uint32_t UnBuffDimm:1; /* 16 */ 510 uint32_t reserved3:2; /* 18:17 */ 511 uint32_t DimmEccEn:1; /* 19 */ 512 uint32_t reserved4:12; /* 31:20 */ 513 } _fmt_revFG; 514 }; 515 516 /* 517 * Function 2 - DRAM Controller: DRAM Controller Miscellaneous Data 518 */ 519 520 union mcreg_drammisc { 521 uint32_t _val32; 522 /* 523 * Register format in revisions F and G 524 */ 525 struct { 526 uint32_t reserved2:1; /* 0 */ 527 uint32_t DisableJitter:1; /* 1 */ 528 uint32_t RdWrQByp:2; /* 3:2 */ 529 uint32_t Mod64Mux:1; /* 4 */ 530 uint32_t DCC_EN:1; /* 5 */ 531 uint32_t ILD_lmt:3; /* 8:6 */ 532 uint32_t DramEnabled:1; /* 9 */ 533 uint32_t PwrSavingsEn:1; /* 10 */ 534 uint32_t reserved1:13; /* 23:11 */ 535 uint32_t MemClkDis:8; /* 31:24 */ 536 } _fmt_revFG; 537 }; 538 539 union mcreg_dramcfg_hi { 540 uint32_t _val32; 541 /* 542 * Register format in revisions E and earlier. 543 */ 544 struct { 545 uint32_t AsyncLat:4; /* 3:0 */ 546 uint32_t reserved1:4; /* 7:4 */ 547 uint32_t RdPreamble:4; /* 11:8 */ 548 uint32_t reserved2:1; /* 12 */ 549 uint32_t MemDQDrvStren:2; /* 14:13 */ 550 uint32_t DisableJitter:1; /* 15 */ 551 uint32_t ILD_lmt:3; /* 18:16 */ 552 uint32_t DCC_EN:1; /* 19 */ 553 uint32_t MemClk:3; /* 22:20 */ 554 uint32_t reserved3:2; /* 24:23 */ 555 uint32_t MCR:1; /* 25 */ 556 uint32_t MC0_EN:1; /* 26 */ 557 uint32_t MC1_EN:1; /* 27 */ 558 uint32_t MC2_EN:1; /* 28 */ 559 uint32_t MC3_EN:1; /* 29 */ 560 uint32_t reserved4:1; /* 30 */ 561 uint32_t OddDivisorCorrect:1; /* 31 */ 562 } _fmt_preF; 563 /* 564 * Register format in revisions F and G 565 */ 566 struct { 567 uint32_t MemClkFreq:3; /* 2:0 */ 568 uint32_t MemClkFreqVal:1; /* 3 */ 569 uint32_t MaxAsyncLat:4; /* 7:4 */ 570 uint32_t reserved1:4; /* 11:8 */ 571 uint32_t RDqsEn:1; /* 12 */ 572 uint32_t reserved2:1; /* 13 */ 573 uint32_t DisDramInterface:1; /* 14 */ 574 uint32_t PowerDownEn:1; /* 15 */ 575 uint32_t PowerDownMode:1; /* 16 */ 576 uint32_t FourRankSODimm:1; /* 17 */ 577 uint32_t FourRankRDimm:1; /* 18 */ 578 uint32_t reserved3:1; /* 19 */ 579 uint32_t SlowAccessMode:1; /* 20 */ 580 uint32_t reserved4:1; /* 21 */ 581 uint32_t BankSwizzleMode:1; /* 22 */ 582 uint32_t undocumented1:1; /* 23 */ 583 uint32_t DcqBypassMax:4; /* 27:24 */ 584 uint32_t FourActWindow:4; /* 31:28 */ 585 } _fmt_revFG; 586 }; 587 588 /* 589 * Function 3 - Miscellaneous Control: Scrub Control Register 590 */ 591 592 union mcreg_scrubctl { 593 uint32_t _val32; 594 struct { 595 uint32_t DramScrub:5; /* 4:0 */ 596 uint32_t reserved3:3; /* 7:5 */ 597 uint32_t L2Scrub:5; /* 12:8 */ 598 uint32_t reserved2:3; /* 15:13 */ 599 uint32_t DcacheScrub:5; /* 20:16 */ 600 uint32_t reserved1:11; /* 31:21 */ 601 } _fmt_cmn; 602 }; 603 604 /* 605 * Function 3 - Miscellaneous Control: On-Line Spare Control Register 606 */ 607 608 union mcreg_nbcfg { 609 uint32_t _val32; 610 /* 611 * Register format in revisions E and earlier. 612 */ 613 struct { 614 uint32_t CpuEccErrEn:1; /* 0 */ 615 uint32_t CpuRdDatErrEn:1; /* 1 */ 616 uint32_t SyncOnUcEccEn:1; /* 2 */ 617 uint32_t SyncPktGenDis:1; /* 3 */ 618 uint32_t SyncPktPropDis:1; /* 4 */ 619 uint32_t IoMstAbortDis:1; /* 5 */ 620 uint32_t CpuErrDis:1; /* 6 */ 621 uint32_t IoErrDis:1; /* 7 */ 622 uint32_t WdogTmrDis:1; /* 8 */ 623 uint32_t WdogTmrCntSel:3; /* 11:9 */ 624 uint32_t WdogTmrBaseSel:2; /* 13:12 */ 625 uint32_t LdtLinkSel:2; /* 15:14 */ 626 uint32_t GenCrcErrByte0:1; /* 16 */ 627 uint32_t GenCrcErrByte1:1; /* 17 */ 628 uint32_t reserved1:2; /* 19:18 */ 629 uint32_t SyncOnWdogEn:1; /* 20 */ 630 uint32_t SyncOnAnyErrEn:1; /* 21 */ 631 uint32_t EccEn:1; /* 22 */ 632 uint32_t ChipKillEccEn:1; /* 23 */ 633 uint32_t IoRdDatErrEn:1; /* 24 */ 634 uint32_t DisPciCfgCpuErrRsp:1; /* 25 */ 635 uint32_t reserved2:1; /* 26 */ 636 uint32_t NbMcaToMstCpuEn:1; /* 27 */ 637 uint32_t reserved3:4; /* 31:28 */ 638 } _fmt_preF; 639 /* 640 * Register format in revisions F and G 641 */ 642 struct { 643 uint32_t CpuEccErrEn:1; /* 0 */ 644 uint32_t CpuRdDatErrEn:1; /* 1 */ 645 uint32_t SyncOnUcEccEn:1; /* 2 */ 646 uint32_t SyncPktGenDis:1; /* 3 */ 647 uint32_t SyncPktPropDis:1; /* 4 */ 648 uint32_t IoMstAbortDis:1; /* 5 */ 649 uint32_t CpuErrDis:1; /* 6 */ 650 uint32_t IoErrDis:1; /* 7 */ 651 uint32_t WdogTmrDis:1; /* 8 */ 652 uint32_t WdogTmrCntSel:3; /* 11:9 */ 653 uint32_t WdogTmrBaseSel:2; /* 13:12 */ 654 uint32_t LdtLinkSel:2; /* 15:14 */ 655 uint32_t GenCrcErrByte0:1; /* 16 */ 656 uint32_t GenCrcErrByte1:1; /* 17 */ 657 uint32_t reserved1:2; /* 19:18 */ 658 uint32_t SyncOnWdogEn:1; /* 20 */ 659 uint32_t SyncOnAnyErrEn:1; /* 21 */ 660 uint32_t EccEn:1; /* 22 */ 661 uint32_t ChipKillEccEn:1; /* 23 */ 662 uint32_t IoRdDatErrEn:1; /* 24 */ 663 uint32_t DisPciCfgCpuErrRsp:1; /* 25 */ 664 uint32_t reserved2:1; /* 26 */ 665 uint32_t NbMcaToMstCpuEn:1; /* 27 */ 666 uint32_t DisTgtAbtCpuErrRsp:1; /* 28 */ 667 uint32_t DisMstAbtCpuErrRsp:1; /* 29 */ 668 uint32_t SyncOnDramAdrParErrEn:1; /* 30 */ 669 uint32_t reserved3:1; /* 31 */ 670 671 } _fmt_revFG; 672 }; 673 674 /* 675 * Function 3 - Miscellaneous Control: On-Line Spare Control Register 676 */ 677 678 union mcreg_sparectl { 679 uint32_t _val32; 680 /* 681 * Register format in revisions F and G 682 */ 683 struct { 684 uint32_t SwapEn:1; /* 0 */ 685 uint32_t SwapDone:1; /* 1 */ 686 uint32_t reserved1:2; /* 3:2 */ 687 uint32_t BadDramCs:3; /* 6:4 */ 688 uint32_t reserved2:5; /* 11:7 */ 689 uint32_t SwapDoneInt:2; /* 13:12 */ 690 uint32_t EccErrInt:2; /* 15:14 */ 691 uint32_t EccErrCntDramCs:3; /* 18:16 */ 692 uint32_t reserved3:1; /* 19 */ 693 uint32_t EccErrCntDramChan:1; /* 20 */ 694 uint32_t reserved4:2; /* 22:21 */ 695 uint32_t EccErrCntWrEn:1; /* 23 */ 696 uint32_t EccErrCnt:4; /* 27:24 */ 697 uint32_t reserved5:4; /* 31:28 */ 698 } _fmt_revFG; 699 }; 700 701 #ifdef __cplusplus 702 } 703 #endif 704 705 #endif /* _MC_AMD_H */ 706