1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_CONTROLREGS_H 28 #define _SYS_CONTROLREGS_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifndef _ASM 33 #include <sys/types.h> 34 #endif 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 /* 41 * This file describes the x86 architecture control registers which 42 * are part of the privileged architecture. 43 * 44 * Many of these definitions are shared between IA-32-style and 45 * AMD64-style processors. 46 */ 47 48 /* CR0 Register */ 49 50 #define CR0_PG 0x80000000 /* paging enabled */ 51 #define CR0_CD 0x40000000 /* cache disable */ 52 #define CR0_NW 0x20000000 /* not writethrough */ 53 #define CR0_AM 0x00040000 /* alignment mask */ 54 #define CR0_WP 0x00010000 /* write protect */ 55 #define CR0_NE 0x00000020 /* numeric error */ 56 #define CR0_ET 0x00000010 /* extension type */ 57 #define CR0_TS 0x00000008 /* task switch */ 58 #define CR0_EM 0x00000004 /* emulation */ 59 #define CR0_MP 0x00000002 /* monitor coprocessor */ 60 #define CR0_PE 0x00000001 /* protection enabled */ 61 62 /* XX64 eliminate these compatibility defines */ 63 64 #define CR0_CE CR0_CD 65 #define CR0_WT CR0_NW 66 67 #define FMT_CR0 \ 68 "\20\40pg\37cd\36nw\35am\21wp\6ne\5et\4ts\3em\2mp\1pe" 69 70 /* CR3 Register */ 71 72 #define CR3_PCD 0x00000010 /* cache disable */ 73 #define CR3_PWT 0x00000008 /* write through */ 74 75 #define FMT_CR3 "\20\5pcd\4pwt" 76 77 /* CR4 Register */ 78 79 #define CR4_VME 0x0001 /* virtual-8086 mode extensions */ 80 #define CR4_PVI 0x0002 /* protected-mode virtual interrupts */ 81 #define CR4_TSD 0x0004 /* time stamp disable */ 82 #define CR4_DE 0x0008 /* debugging extensions */ 83 #define CR4_PSE 0x0010 /* page size extensions */ 84 #define CR4_PAE 0x0020 /* physical address extension */ 85 #define CR4_MCE 0x0040 /* machine check enable */ 86 #define CR4_PGE 0x0080 /* page global enable */ 87 #define CR4_PCE 0x0100 /* perf-monitoring counter enable */ 88 #define CR4_OSFXSR 0x0200 /* OS fxsave/fxrstor support */ 89 #define CR4_OSXMMEXCPT 0x0400 /* OS unmasked exception support */ 90 91 #define FMT_CR4 \ 92 "\20\13xmme\12fxsr\11pce\10pge\7mce\6pae\5pse\4de\3tsd\2pvi\1vme" 93 94 /* Intel's SYSENTER configuration registers */ 95 96 #define MSR_INTC_SEP_CS 0x174 /* kernel code selector MSR */ 97 #define MSR_INTC_SEP_ESP 0x175 /* kernel esp MSR */ 98 #define MSR_INTC_SEP_EIP 0x176 /* kernel eip MSR */ 99 100 /* AMD's EFER register */ 101 102 #define MSR_AMD_EFER 0xc0000080 /* extended feature enable MSR */ 103 104 #define AMD_EFER_NXE 0x800 /* no-execute enable */ 105 #define AMD_EFER_LMA 0x400 /* long mode active (read-only) */ 106 #define AMD_EFER_LME 0x100 /* long mode enable */ 107 #define AMD_EFER_SCE 0x001 /* system call extensions */ 108 109 #define FMT_AMD_EFER \ 110 "\20\14nxe\13lma\11lme\1sce" 111 112 /* AMD's SYSCFG register */ 113 114 #define MSR_AMD_SYSCFG 0xc0000010 /* system configuration MSR */ 115 116 #define AMD_SYSCFG_TOM2 0x200000 /* MtrrTom2En */ 117 #define AMD_SYSCFG_MVDM 0x100000 /* MtrrVarDramEn */ 118 #define AMD_SYSCFG_MFDM 0x080000 /* MtrrFixDramModEn */ 119 #define AMD_SYSCFG_MFDE 0x040000 /* MtrrFixDramEn */ 120 121 #define FMT_AMD_SYSCFG \ 122 "\20\26tom2\25mvdm\24mfdm\23mfde" 123 124 /* AMD's syscall/sysret MSRs */ 125 126 #define MSR_AMD_STAR 0xc0000081 /* %cs:%ss:%cs:%ss:%eip for syscall */ 127 #define MSR_AMD_LSTAR 0xc0000082 /* target %rip of 64-bit syscall */ 128 #define MSR_AMD_CSTAR 0xc0000083 /* target %rip of 32-bit syscall */ 129 #define MSR_AMD_SFMASK 0xc0000084 /* syscall flag mask */ 130 131 /* AMD's FS.base and GS.base MSRs */ 132 133 #define MSR_AMD_FSBASE 0xc0000100 /* 64-bit base address for %fs */ 134 #define MSR_AMD_GSBASE 0xc0000101 /* 64-bit base address for %gs */ 135 #define MSR_AMD_KGSBASE 0xc0000102 /* swapgs swaps this with gsbase */ 136 137 /* AMD's configuration MSRs, weakly documented in the revision guide */ 138 139 #define MSR_AMD_DC_CFG 0xc0011022 140 141 #define AMD_DC_CFG_DIS_CNV_WC_SSO (UINT64_C(1) << 3) 142 #define AMD_DC_CFG_DIS_SMC_CHK_BUF (UINT64_C(1) << 10) 143 144 /* AMD's HWCR MSR */ 145 146 #define MSR_AMD_HWCR 0xc0010015 147 148 #define AMD_HWCR_FFDIS 0x40 /* set to disable TLB Flush Filter */ 149 150 /* AMD's NorthBridge Config MSR, SHOULD ONLY BE WRITTEN TO BY BIOS */ 151 152 #define MSR_AMD_NB_CFG 0xc001001f 153 154 #define AMD_NB_CFG_SRQ_HEARTBEAT (UINT64_C(1) << 20) 155 156 /* AMD */ 157 #define MSR_AMD_PATCHLEVEL 0x8b 158 159 #ifdef __cplusplus 160 } 161 #endif 162 163 #endif /* !_SYS_CONTROLREGS_H */ 164