1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _PCIEX_PCI_NVIDIA_H 28 #define _PCIEX_PCI_NVIDIA_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 /* 35 * PCI Configuration (Nvidia, PCIe) related library functions 36 */ 37 boolean_t look_for_any_pciex_device(uchar_t); 38 boolean_t check_if_device_is_pciex(dev_info_t *, uchar_t, uchar_t, 39 uchar_t, ushort_t *, ushort_t *); 40 boolean_t create_pcie_root_bus(uchar_t, dev_info_t *); 41 void add_nvidia_isa_bridge_props(dev_info_t *, uchar_t, uchar_t, 42 uchar_t); 43 44 /* Generic Nvidia chipset IDs and defines */ 45 #define NVIDIA_VENDOR_ID 0x10de /* Nvidia Vendor Id */ 46 #define NVIDIA_INTR_BCR_OFF 0x3C /* NV_XVR_INTR_BCR */ 47 #define NVIDIA_INTR_BCR_SERR_FORWARD_BIT 0x02 /* SERR_FORWARD bit */ 48 49 /* CK8-04 PCIe RC and LPC-PCI Bridge device IDs */ 50 #define NVIDIA_CK804_DEVICE_ID 0x5d /* ck8-04 dev id */ 51 #define NVIDIA_CK804_DEFAULT_ISA_BRIDGE_DEVID 0x50 /* LPC Default Bridge */ 52 #define NVIDIA_CK804_PRO_ISA_BRIDGE_DEVID 0x51 /* LPC Bridge */ 53 #define NVIDIA_CK804_SLAVE_ISA_BRIDGE_DEVID 0xd3 /* Slave LPC Bridge */ 54 #define NVIDIA_CK804_AER_VALID_REVID 0xa3 /* RID w/ AER enabled */ 55 56 #define NVIDIA_CK804_LPC2PCI_DEVICE_ID(did) \ 57 (((did) == NVIDIA_CK804_DEFAULT_ISA_BRIDGE_DEVID) || \ 58 ((did) == NVIDIA_CK804_PRO_ISA_BRIDGE_DEVID) || \ 59 ((did) == NVIDIA_CK804_SLAVE_ISA_BRIDGE_DEVID)) 60 61 /* 62 * Only for Nvidia's CrushK 8-04 chipsets: 63 * To enable hotplug; we need to map in two I/O BARs 64 * from ISA bridge's config space 65 */ 66 #define NVIDIA_CK804_ISA_SYSCTRL_BAR_OFF 0x64 /* System Control BAR */ 67 #define NVIDIA_CK804_ISA_ANALOG_BAR_OFF 0x68 /* Analog BAR */ 68 69 /* NV_XVR_VEND_CYA1 related defines */ 70 #define NVIDIA_CK804_VEND_CYA1_OFF 0xf40 /* NV_XVR_VEND_CYA1 */ 71 #define NVIDIA_CK804_VEND_CYA1_ERPT_VAL 0x2000 /* enable CYA1 ERPT */ 72 #define NVIDIA_CK804_VEND_CYA1_ERPT_MASK 0xdfff /* CYA1 ERPT mask */ 73 74 /* 75 * C51 related defines 76 */ 77 78 /* C51 PCIe Root Complex Device ID defines */ 79 #define NVIDIA_C51_DEVICE_ID_XVR16 0x2fb 80 #define NVIDIA_C51_DEVICE_ID_XVR1_0 0x2fc 81 #define NVIDIA_C51_DEVICE_ID_XVR1_1 0x2fd 82 83 #define NVIDIA_C51_DEVICE_ID(did) \ 84 (((did) == NVIDIA_C51_DEVICE_ID_XVR16) || \ 85 ((did) == NVIDIA_C51_DEVICE_ID_XVR1_0) || \ 86 ((did) == NVIDIA_C51_DEVICE_ID_XVR1_1)) 87 88 /* 89 * MCP55 related defines 90 */ 91 92 /* MCP55 PCIe Root Complex Device ID defines */ 93 #define NVIDIA_MCP55_DEVICE_ID_XVR4 0x374 94 #define NVIDIA_MCP55_DEVICE_ID_XVR8 0x375 95 #define NVIDIA_MCP55_DEVICE_ID_XVR8_VC1 0x376 96 #define NVIDIA_MCP55_DEVICE_ID_XVR16 0x377 97 #define NVIDIA_MCP55_DEVICE_ID_XVR4_VC1 0x378 98 99 #define NVIDIA_MCP55_DEVICE_ID(did) \ 100 (((did) == NVIDIA_MCP55_DEVICE_ID_XVR4) || \ 101 ((did) == NVIDIA_MCP55_DEVICE_ID_XVR8) || \ 102 ((did) == NVIDIA_MCP55_DEVICE_ID_XVR16) || \ 103 ((did) == NVIDIA_MCP55_DEVICE_ID_XVR4_VC1) || \ 104 ((did) == NVIDIA_MCP55_DEVICE_ID_XVR8_VC1)) 105 106 /* MCP55 LPC-PCI Bridge Device ID defines */ 107 #define NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP0 0x360 108 #define NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP1 0x361 109 #define NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP2 0x362 110 #define NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP3 0x363 111 #define NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP4 0x364 112 #define NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP5 0x365 113 #define NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP6 0x366 114 #define NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP7 0x367 115 116 #define NVIDIA_MCP55_LPC2PCI_DEVICE_ID(did) \ 117 (((did) == NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP0) || \ 118 ((did) == NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP1) || \ 119 ((did) == NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP2) || \ 120 ((did) == NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP3) || \ 121 ((did) == NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP4) || \ 122 ((did) == NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP5) || \ 123 ((did) == NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP6) || \ 124 ((did) == NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP7)) 125 126 /* 127 * MCP61 related defines 128 */ 129 130 /* MCP61 PCIe Root Complex Device ID defines */ 131 #define NVIDIA_MCP61_DEVICE_ID_XVR4 0x3e8 132 #define NVIDIA_MCP61_DEVICE_ID_XVR8 0x3e9 133 134 #define NVIDIA_MCP61_DEVICE_ID(did) \ 135 (((did) == NVIDIA_MCP61_DEVICE_ID_XVR4) || \ 136 ((did) == NVIDIA_MCP61_DEVICE_ID_XVR8)) 137 138 /* 139 * MCP65 related defines 140 */ 141 142 /* MCP65 PCIe Root Complex Device ID defines */ 143 #define NVIDIA_MCP65_DEVICE_ID_XVR4 0x458 144 #define NVIDIA_MCP65_DEVICE_ID_XVR8 0x459 145 #define NVIDIA_MCP65_DEVICE_ID_XVR16 0x45a 146 147 #define NVIDIA_MCP65_DEVICE_ID(did) \ 148 (((did) == NVIDIA_MCP65_DEVICE_ID_XVR4) || \ 149 ((did) == NVIDIA_MCP65_DEVICE_ID_XVR8) || \ 150 ((did) == NVIDIA_MCP65_DEVICE_ID_XVR16)) 151 152 /* 153 * Check if the given device is a Nvidia's LPC bridge 154 */ 155 #define NVIDIA_IS_LPC_BRIDGE(vid, did) \ 156 (((vid) == NVIDIA_VENDOR_ID) && \ 157 (NVIDIA_CK804_LPC2PCI_DEVICE_ID(did) || \ 158 NVIDIA_MCP55_LPC2PCI_DEVICE_ID(did))) 159 160 /* Check for PCIe RC Device ID */ 161 #define NVIDIA_PCIE_RC_DEV_ID(did) \ 162 (((did) == NVIDIA_CK804_DEVICE_ID) || \ 163 NVIDIA_C51_DEVICE_ID(did) || \ 164 NVIDIA_MCP55_DEVICE_ID(did) || \ 165 NVIDIA_MCP61_DEVICE_ID(did) || \ 166 NVIDIA_MCP65_DEVICE_ID(did)) 167 168 /* 169 * Defines to figure out what kind of hotplug is supported 170 */ 171 #define INBAND_HPC_NONE 0x0 /* No hotplug supported */ 172 #define INBAND_HPC_PCIE 0x1 /* PCIe based hotplug supported */ 173 #define INBAND_HPC_SHPC 0x2 /* SHPC based hotplug supported */ 174 175 #ifdef __cplusplus 176 } 177 #endif 178 179 #endif /* _PCIEX_PCI_NVIDIA_H */ 180