1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * Library file that has code for PCIe booting 31 */ 32 33 #include <sys/conf.h> 34 #include <sys/pci.h> 35 #include <sys/sunndi.h> 36 #include <sys/pcie.h> 37 #include <sys/pci_cfgspace.h> 38 #include <io/pciex/pcie_nvidia.h> 39 40 /* 41 * PCI Configuration (Nvidia chipsets, PCIe) related library functions 42 */ 43 static boolean_t look_for_any_pciex_device(uchar_t); 44 45 /* Globals */ 46 extern int pci_boot_debug; 47 48 boolean_t 49 check_if_device_is_pciex(dev_info_t *cdip, uchar_t bus, uchar_t dev, 50 uchar_t func, ushort_t *slot_number, ushort_t *is_pci_bridge) 51 { 52 boolean_t found_pciex = B_FALSE; 53 ushort_t cap; 54 ushort_t capsp; 55 ushort_t cap_count = PCI_CAP_MAX_PTR; 56 ushort_t status; 57 uint32_t slot_cap; 58 59 *slot_number = 0; 60 61 status = (*pci_getw_func)(bus, dev, func, PCI_CONF_STAT); 62 if (!(status & PCI_STAT_CAP)) 63 return (B_FALSE); 64 65 capsp = (*pci_getb_func)(bus, dev, func, PCI_CONF_CAP_PTR); 66 while (cap_count-- && capsp >= PCI_CAP_PTR_OFF) { 67 capsp &= PCI_CAP_PTR_MASK; 68 cap = (*pci_getb_func)(bus, dev, func, capsp); 69 70 if (cap == PCI_CAP_ID_PCIX && cdip) 71 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 72 "pcix-capid-pointer", capsp); 73 74 if (cap == PCI_CAP_ID_PCI_E) { 75 #ifdef DEBUG 76 if (pci_boot_debug) 77 cmn_err(CE_CONT, "PCI-Express (%x,%x,%x) " 78 "capability found\n", bus, dev, func); 79 #endif /* DEBUG */ 80 81 status = (*pci_getw_func)(bus, dev, func, capsp + 2); 82 /* 83 * See section 7.8.2 of PCI-Express Base Spec v1.0a 84 * for Device/Port Type. 85 * PCIE_PCIECAP_DEV_TYPE_PCIE2PCI implies that the 86 * device is a PCIe2PCI bridge 87 */ 88 *is_pci_bridge = 89 ((status & PCIE_PCIECAP_DEV_TYPE_PCIE2PCI) == 90 PCIE_PCIECAP_DEV_TYPE_PCIE2PCI) ? 1 : 0; 91 92 /* 93 * Check for "Slot Implemented" bit 94 * PCIE_PCIECAP_SLOT_IMPL implies that. 95 */ 96 if (status & PCIE_PCIECAP_SLOT_IMPL) { 97 /* offset 14h is Slot Cap Register */ 98 slot_cap = (*pci_getl_func)(bus, dev, func, 99 capsp + PCIE_SLOTCAP); 100 *slot_number = 101 PCIE_SLOTCAP_PHY_SLOT_NUM(slot_cap); 102 103 if (cdip) 104 (void) ndi_prop_update_int( 105 DDI_DEV_T_NONE, cdip, 106 "pcie-slotcap-reg", slot_cap); 107 108 /* Is PCI Express HotPlug capability set? */ 109 if (cdip && 110 (slot_cap & PCIE_SLOTCAP_HP_CAPABLE)) { 111 (void) ndi_prop_update_int( 112 DDI_DEV_T_NONE, cdip, 113 "pci-hotplug-type", 114 INBAND_HPC_PCIE); 115 } 116 } 117 118 /* 119 * Can only do I/O based config space access at 120 * this early stage. Meaning, one cannot access 121 * extended config space i.e. > 256 bytes. 122 * So, AER cap_id property will be created much later. 123 */ 124 if (cdip) { 125 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 126 "pcie-capid-reg", 127 (*pci_getw_func)(bus, dev, func, 128 capsp + PCIE_PCIECAP)); 129 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 130 "pcie-capid-pointer", capsp); 131 } 132 133 found_pciex = B_TRUE; 134 } 135 136 if (cdip && (cap == PCI_CAP_ID_PCI_HOTPLUG)) { 137 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 138 "pci-hotplug-type", INBAND_HPC_SHPC); 139 } 140 141 capsp = (*pci_getb_func)(bus, dev, func, 142 capsp + PCI_CAP_NEXT_PTR); 143 } 144 145 return (found_pciex); 146 } 147 148 149 /* 150 * scan all buses, devices, functions to look for any 151 * PCI-Express device in the system. 152 * If found, return B_TRUE else B_FALSE 153 */ 154 static boolean_t 155 look_for_any_pciex_device(uchar_t bus) 156 { 157 uchar_t dev, func; 158 uchar_t nfunc, header; 159 ushort_t venid, slot_num, is_pci_bridge = 0; 160 161 for (dev = 0; dev < 32; dev++) { 162 nfunc = 1; 163 for (func = 0; func < nfunc; func++) { 164 #ifdef DEBUG 165 if (pci_boot_debug) 166 cmn_err(CE_NOTE, "pciex dev 0x%x, func 0x%x", 167 dev, func); 168 #endif /* DEBUG */ 169 170 venid = (*pci_getw_func)(bus, dev, func, 171 PCI_CONF_VENID); 172 /* no function at this address */ 173 if ((venid == 0xffff) || (venid == 0)) 174 continue; 175 176 header = (*pci_getb_func)(bus, dev, func, 177 PCI_CONF_HEADER); 178 if (header == 0xff) 179 continue; /* illegal value */ 180 181 /* 182 * according to some mail from Microsoft posted to 183 * the pci-drivers alias, their only requirement for 184 * a multifunction device is for the 1st function to 185 * have to PCI_HEADER_MULTI bit set. 186 */ 187 if ((func == 0) && (header & PCI_HEADER_MULTI)) 188 nfunc = 8; 189 190 if (check_if_device_is_pciex(NULL, bus, dev, func, 191 &slot_num, &is_pci_bridge) == B_TRUE) 192 return (B_TRUE); 193 } /* end of func */ 194 } /* end of dev */ 195 196 return (B_FALSE); 197 } 198 199 200 boolean_t 201 create_pcie_root_bus(uchar_t bus, dev_info_t *dip) 202 { 203 /* 204 * Currently this is being hard-coded. 205 * We need to figure out if the root bus does indeed 206 * have PCI-Ex in the path by looking for MCFG in 207 * the ACPI tables 208 */ 209 if (look_for_any_pciex_device(bus) == B_FALSE) 210 return (B_FALSE); 211 212 #ifdef DEBUG 213 if (pci_boot_debug) 214 cmn_err(CE_CONT, "Found PCI-Ex in the system\n"); 215 #endif /* DEBUG */ 216 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 217 "device_type", "pciex"); 218 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 219 "compatible", "pciex_root_complex"); 220 221 return (B_TRUE); 222 } 223 224 225 /* 226 * add_nvidia_isa_bridge_props(): 227 * To enable native hotplug; we need to map in two I/O BARs 228 * from ISA bridge's config space 229 * 230 * NOTE: For now, this function is only used for Nvidia's CrushK 8-04 chipsets. 231 */ 232 void 233 add_nvidia_isa_bridge_props(dev_info_t *dip, uchar_t bus, uchar_t dev, 234 uchar_t func) 235 { 236 uint_t devloc, base; 237 pci_regspec_t regs[2] = {{0}}; 238 pci_regspec_t assigned[2] = {{0}}; 239 240 devloc = (uint_t)bus << PCI_REG_BUS_SHIFT | 241 (uint_t)dev << PCI_REG_DEV_SHIFT | 242 (uint_t)func << PCI_REG_FUNC_SHIFT; 243 regs[0].pci_phys_hi = devloc; 244 245 /* System Control BAR i/o space */ 246 base = (*pci_getl_func)(bus, dev, func, 247 NVIDIA_CK804_ISA_SYSCTRL_BAR_OFF); 248 regs[0].pci_size_low = assigned[0].pci_size_low = PCI_CONF_HDR_SIZE; 249 assigned[0].pci_phys_hi = regs[0].pci_phys_hi = (PCI_RELOCAT_B | 250 PCI_ADDR_IO | devloc | NVIDIA_CK804_ISA_SYSCTRL_BAR_OFF); 251 assigned[0].pci_phys_low = regs[0].pci_phys_low = 252 base & PCI_BASE_IO_ADDR_M; 253 254 /* Analog BAR i/o space */ 255 base = (*pci_getl_func)(bus, dev, func, 256 NVIDIA_CK804_ISA_ANALOG_BAR_OFF); 257 regs[1].pci_size_low = assigned[1].pci_size_low = PCI_CONF_HDR_SIZE; 258 assigned[1].pci_phys_hi = regs[1].pci_phys_hi = (PCI_RELOCAT_B | 259 PCI_ADDR_IO | devloc | NVIDIA_CK804_ISA_ANALOG_BAR_OFF); 260 assigned[1].pci_phys_low = regs[1].pci_phys_low = 261 base & PCI_BASE_IO_ADDR_M; 262 263 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg", 264 (int *)regs, 2 * sizeof (pci_regspec_t) / sizeof (int)); 265 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 266 "assigned-addresses", 267 (int *)assigned, 2 * sizeof (pci_regspec_t) / sizeof (int)); 268 } 269