1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * Library file that has code for PCIe booting 29 */ 30 31 #include <sys/conf.h> 32 #include <sys/pci.h> 33 #include <sys/sunndi.h> 34 #include <sys/pcie.h> 35 #include <sys/pci_cfgspace.h> 36 #include <io/pciex/pcie_nvidia.h> 37 38 /* 39 * PCI Configuration (Nvidia chipsets, PCIe) related library functions 40 */ 41 static boolean_t look_for_any_pciex_device(uchar_t); 42 43 /* Globals */ 44 extern int pci_boot_debug; 45 46 boolean_t 47 check_if_device_is_pciex(dev_info_t *cdip, uchar_t bus, uchar_t dev, 48 uchar_t func, ushort_t *slot_number, ushort_t *is_pci_bridge) 49 { 50 boolean_t found_pciex = B_FALSE; 51 ushort_t cap; 52 ushort_t capsp; 53 ushort_t cap_count = PCI_CAP_MAX_PTR; 54 ushort_t status; 55 uint32_t slot_cap; 56 57 *slot_number = 0; 58 59 status = (*pci_getw_func)(bus, dev, func, PCI_CONF_STAT); 60 if (!(status & PCI_STAT_CAP)) 61 return (B_FALSE); 62 63 capsp = (*pci_getb_func)(bus, dev, func, PCI_CONF_CAP_PTR); 64 while (cap_count-- && capsp >= PCI_CAP_PTR_OFF) { 65 capsp &= PCI_CAP_PTR_MASK; 66 cap = (*pci_getb_func)(bus, dev, func, capsp); 67 68 if (cap == PCI_CAP_ID_PCI_E) { 69 #ifdef DEBUG 70 if (pci_boot_debug) 71 cmn_err(CE_CONT, "PCI-Express (%x,%x,%x) " 72 "capability found\n", bus, dev, func); 73 #endif /* DEBUG */ 74 75 status = (*pci_getw_func)(bus, dev, func, capsp + 2); 76 /* 77 * See section 7.8.2 of PCI-Express Base Spec v1.0a 78 * for Device/Port Type. 79 * PCIE_PCIECAP_DEV_TYPE_PCIE2PCI implies that the 80 * device is a PCIe2PCI bridge 81 */ 82 *is_pci_bridge = 83 ((status & PCIE_PCIECAP_DEV_TYPE_MASK) == 84 PCIE_PCIECAP_DEV_TYPE_PCIE2PCI) ? 1 : 0; 85 86 /* 87 * Check for "Slot Implemented" bit 88 * PCIE_PCIECAP_SLOT_IMPL implies that. 89 */ 90 if (status & PCIE_PCIECAP_SLOT_IMPL) { 91 /* offset 14h is Slot Cap Register */ 92 slot_cap = (*pci_getl_func)(bus, dev, func, 93 capsp + PCIE_SLOTCAP); 94 *slot_number = 95 PCIE_SLOTCAP_PHY_SLOT_NUM(slot_cap); 96 97 /* Is PCI Express HotPlug capability set? */ 98 if (cdip && 99 (slot_cap & PCIE_SLOTCAP_HP_CAPABLE)) { 100 (void) ndi_prop_update_int( 101 DDI_DEV_T_NONE, cdip, 102 "pci-hotplug-type", 103 INBAND_HPC_PCIE); 104 } 105 } 106 107 found_pciex = B_TRUE; 108 } 109 110 if (cdip && (cap == PCI_CAP_ID_PCI_HOTPLUG)) { 111 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 112 "pci-hotplug-type", INBAND_HPC_SHPC); 113 } 114 115 capsp = (*pci_getb_func)(bus, dev, func, 116 capsp + PCI_CAP_NEXT_PTR); 117 } 118 119 return (found_pciex); 120 } 121 122 123 /* 124 * scan all buses, devices, functions to look for any 125 * PCI-Express device in the system. 126 * If found, return B_TRUE else B_FALSE 127 */ 128 static boolean_t 129 look_for_any_pciex_device(uchar_t bus) 130 { 131 uchar_t dev, func; 132 uchar_t nfunc, header; 133 ushort_t venid, slot_num, is_pci_bridge = 0; 134 135 for (dev = 0; dev < 32; dev++) { 136 nfunc = 1; 137 for (func = 0; func < nfunc; func++) { 138 #ifdef DEBUG 139 if (pci_boot_debug) 140 cmn_err(CE_NOTE, "pciex dev 0x%x, func 0x%x", 141 dev, func); 142 #endif /* DEBUG */ 143 144 venid = (*pci_getw_func)(bus, dev, func, 145 PCI_CONF_VENID); 146 /* no function at this address */ 147 if ((venid == 0xffff) || (venid == 0)) 148 continue; 149 150 header = (*pci_getb_func)(bus, dev, func, 151 PCI_CONF_HEADER); 152 if (header == 0xff) 153 continue; /* illegal value */ 154 155 /* 156 * according to some mail from Microsoft posted to 157 * the pci-drivers alias, their only requirement for 158 * a multifunction device is for the 1st function to 159 * have to PCI_HEADER_MULTI bit set. 160 */ 161 if ((func == 0) && (header & PCI_HEADER_MULTI)) 162 nfunc = 8; 163 164 if (check_if_device_is_pciex(NULL, bus, dev, func, 165 &slot_num, &is_pci_bridge) == B_TRUE) 166 return (B_TRUE); 167 } /* end of func */ 168 } /* end of dev */ 169 170 return (B_FALSE); 171 } 172 173 174 boolean_t 175 create_pcie_root_bus(uchar_t bus, dev_info_t *dip) 176 { 177 /* 178 * Currently this is being hard-coded. 179 * We need to figure out if the root bus does indeed 180 * have PCI-Ex in the path by looking for MCFG in 181 * the ACPI tables 182 */ 183 if (look_for_any_pciex_device(bus) == B_FALSE) 184 return (B_FALSE); 185 186 #ifdef DEBUG 187 if (pci_boot_debug) 188 cmn_err(CE_CONT, "Found PCI-Ex in the system\n"); 189 #endif /* DEBUG */ 190 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 191 "device_type", "pciex"); 192 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 193 "compatible", "pciex_root_complex"); 194 195 return (B_TRUE); 196 } 197 198 199 /* 200 * add_nvidia_isa_bridge_props(): 201 * To enable native hotplug; we need to map in two I/O BARs 202 * from ISA bridge's config space 203 * 204 * NOTE: For now, this function is only used for Nvidia's CrushK 8-04 chipsets. 205 */ 206 void 207 add_nvidia_isa_bridge_props(dev_info_t *dip, uchar_t bus, uchar_t dev, 208 uchar_t func) 209 { 210 uint_t devloc, base; 211 pci_regspec_t regs[2] = {{0}}; 212 pci_regspec_t assigned[2] = {{0}}; 213 214 devloc = (uint_t)bus << PCI_REG_BUS_SHIFT | 215 (uint_t)dev << PCI_REG_DEV_SHIFT | 216 (uint_t)func << PCI_REG_FUNC_SHIFT; 217 regs[0].pci_phys_hi = devloc; 218 219 /* System Control BAR i/o space */ 220 base = (*pci_getl_func)(bus, dev, func, 221 NVIDIA_CK804_ISA_SYSCTRL_BAR_OFF); 222 regs[0].pci_size_low = assigned[0].pci_size_low = PCI_CONF_HDR_SIZE; 223 assigned[0].pci_phys_hi = regs[0].pci_phys_hi = (PCI_RELOCAT_B | 224 PCI_ADDR_IO | devloc | NVIDIA_CK804_ISA_SYSCTRL_BAR_OFF); 225 assigned[0].pci_phys_low = regs[0].pci_phys_low = 226 base & PCI_BASE_IO_ADDR_M; 227 228 /* Analog BAR i/o space */ 229 base = (*pci_getl_func)(bus, dev, func, 230 NVIDIA_CK804_ISA_ANALOG_BAR_OFF); 231 regs[1].pci_size_low = assigned[1].pci_size_low = PCI_CONF_HDR_SIZE; 232 assigned[1].pci_phys_hi = regs[1].pci_phys_hi = (PCI_RELOCAT_B | 233 PCI_ADDR_IO | devloc | NVIDIA_CK804_ISA_ANALOG_BAR_OFF); 234 assigned[1].pci_phys_low = regs[1].pci_phys_low = 235 base & PCI_BASE_IO_ADDR_M; 236 237 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg", 238 (int *)regs, 2 * sizeof (pci_regspec_t) / sizeof (int)); 239 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 240 "assigned-addresses", 241 (int *)assigned, 2 * sizeof (pci_regspec_t) / sizeof (int)); 242 } 243