1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * Library file that has code for PCIe booting 31 */ 32 33 #include <sys/conf.h> 34 #include <sys/pci.h> 35 #include <sys/sunndi.h> 36 #include <sys/pcie.h> 37 #include <sys/pci_cfgspace.h> 38 #include <io/pciex/pcie_nvidia.h> 39 40 /* 41 * PCI Configuration (Nvidia chipsets, PCIe) related library functions 42 */ 43 static boolean_t look_for_any_pciex_device(uchar_t); 44 45 /* Globals */ 46 extern int pci_boot_debug; 47 48 boolean_t 49 check_if_device_is_pciex(dev_info_t *cdip, uchar_t bus, uchar_t dev, 50 uchar_t func, ushort_t *slot_number, ushort_t *is_pci_bridge) 51 { 52 boolean_t found_pciex = B_FALSE; 53 ushort_t cap; 54 ushort_t capsp; 55 ushort_t cap_count = PCI_CAP_MAX_PTR; 56 ushort_t status; 57 uint32_t slot_cap; 58 59 *slot_number = 0; 60 61 status = (*pci_getw_func)(bus, dev, func, PCI_CONF_STAT); 62 if (!(status & PCI_STAT_CAP)) 63 return (B_FALSE); 64 65 capsp = (*pci_getb_func)(bus, dev, func, PCI_CONF_CAP_PTR); 66 while (cap_count-- && capsp >= PCI_CAP_PTR_OFF) { 67 capsp &= PCI_CAP_PTR_MASK; 68 cap = (*pci_getb_func)(bus, dev, func, capsp); 69 70 if (cap == PCI_CAP_ID_PCIX && cdip) 71 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 72 "pcix-capid-pointer", capsp); 73 74 if (cap == PCI_CAP_ID_MSI && cdip) { 75 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 76 "pci-msi-capid-pointer", capsp); 77 } 78 79 if (cap == PCI_CAP_ID_MSI_X && cdip) { 80 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 81 "pci-msix-capid-pointer", capsp); 82 } 83 84 if (cap == PCI_CAP_ID_PCI_E) { 85 #ifdef DEBUG 86 if (pci_boot_debug) 87 cmn_err(CE_CONT, "PCI-Express (%x,%x,%x) " 88 "capability found\n", bus, dev, func); 89 #endif /* DEBUG */ 90 91 status = (*pci_getw_func)(bus, dev, func, capsp + 2); 92 /* 93 * See section 7.8.2 of PCI-Express Base Spec v1.0a 94 * for Device/Port Type. 95 * PCIE_PCIECAP_DEV_TYPE_PCIE2PCI implies that the 96 * device is a PCIe2PCI bridge 97 */ 98 *is_pci_bridge = 99 ((status & PCIE_PCIECAP_DEV_TYPE_PCIE2PCI) == 100 PCIE_PCIECAP_DEV_TYPE_PCIE2PCI) ? 1 : 0; 101 102 /* 103 * Check for "Slot Implemented" bit 104 * PCIE_PCIECAP_SLOT_IMPL implies that. 105 */ 106 if (status & PCIE_PCIECAP_SLOT_IMPL) { 107 /* offset 14h is Slot Cap Register */ 108 slot_cap = (*pci_getl_func)(bus, dev, func, 109 capsp + PCIE_SLOTCAP); 110 *slot_number = 111 PCIE_SLOTCAP_PHY_SLOT_NUM(slot_cap); 112 113 if (cdip) 114 (void) ndi_prop_update_int( 115 DDI_DEV_T_NONE, cdip, 116 "pcie-slotcap-reg", slot_cap); 117 118 /* Is PCI Express HotPlug capability set? */ 119 if (cdip && 120 (slot_cap & PCIE_SLOTCAP_HP_CAPABLE)) { 121 (void) ndi_prop_update_int( 122 DDI_DEV_T_NONE, cdip, 123 "pci-hotplug-type", 124 INBAND_HPC_PCIE); 125 } 126 } 127 128 /* 129 * Can only do I/O based config space access at 130 * this early stage. Meaning, one cannot access 131 * extended config space i.e. > 256 bytes. 132 * So, AER cap_id property will be created much later. 133 */ 134 if (cdip) { 135 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 136 "pcie-capid-reg", 137 (*pci_getw_func)(bus, dev, func, 138 capsp + PCIE_PCIECAP)); 139 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 140 "pcie-capid-pointer", capsp); 141 } 142 143 found_pciex = B_TRUE; 144 } 145 146 if (cdip && (cap == PCI_CAP_ID_PCI_HOTPLUG)) { 147 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 148 "pci-hotplug-type", INBAND_HPC_SHPC); 149 } 150 151 capsp = (*pci_getb_func)(bus, dev, func, 152 capsp + PCI_CAP_NEXT_PTR); 153 } 154 155 return (found_pciex); 156 } 157 158 159 /* 160 * scan all buses, devices, functions to look for any 161 * PCI-Express device in the system. 162 * If found, return B_TRUE else B_FALSE 163 */ 164 static boolean_t 165 look_for_any_pciex_device(uchar_t bus) 166 { 167 uchar_t dev, func; 168 uchar_t nfunc, header; 169 ushort_t venid, slot_num, is_pci_bridge = 0; 170 171 for (dev = 0; dev < 32; dev++) { 172 nfunc = 1; 173 for (func = 0; func < nfunc; func++) { 174 #ifdef DEBUG 175 if (pci_boot_debug) 176 cmn_err(CE_NOTE, "pciex dev 0x%x, func 0x%x", 177 dev, func); 178 #endif /* DEBUG */ 179 180 venid = (*pci_getw_func)(bus, dev, func, 181 PCI_CONF_VENID); 182 /* no function at this address */ 183 if ((venid == 0xffff) || (venid == 0)) 184 continue; 185 186 header = (*pci_getb_func)(bus, dev, func, 187 PCI_CONF_HEADER); 188 if (header == 0xff) 189 continue; /* illegal value */ 190 191 /* 192 * according to some mail from Microsoft posted to 193 * the pci-drivers alias, their only requirement for 194 * a multifunction device is for the 1st function to 195 * have to PCI_HEADER_MULTI bit set. 196 */ 197 if ((func == 0) && (header & PCI_HEADER_MULTI)) 198 nfunc = 8; 199 200 if (check_if_device_is_pciex(NULL, bus, dev, func, 201 &slot_num, &is_pci_bridge) == B_TRUE) 202 return (B_TRUE); 203 } /* end of func */ 204 } /* end of dev */ 205 206 return (B_FALSE); 207 } 208 209 210 boolean_t 211 create_pcie_root_bus(uchar_t bus, dev_info_t *dip) 212 { 213 /* 214 * Currently this is being hard-coded. 215 * We need to figure out if the root bus does indeed 216 * have PCI-Ex in the path by looking for MCFG in 217 * the ACPI tables 218 */ 219 if (look_for_any_pciex_device(bus) == B_FALSE) 220 return (B_FALSE); 221 222 #ifdef DEBUG 223 if (pci_boot_debug) 224 cmn_err(CE_CONT, "Found PCI-Ex in the system\n"); 225 #endif /* DEBUG */ 226 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 227 "device_type", "pciex"); 228 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 229 "compatible", "pciex_root_complex"); 230 231 return (B_TRUE); 232 } 233 234 235 /* 236 * add_nvidia_isa_bridge_props(): 237 * To enable native hotplug; we need to map in two I/O BARs 238 * from ISA bridge's config space 239 * 240 * NOTE: For now, this function is only used for Nvidia's CrushK 8-04 chipsets. 241 */ 242 void 243 add_nvidia_isa_bridge_props(dev_info_t *dip, uchar_t bus, uchar_t dev, 244 uchar_t func) 245 { 246 uint_t devloc, base; 247 pci_regspec_t regs[2] = {{0}}; 248 pci_regspec_t assigned[2] = {{0}}; 249 250 devloc = (uint_t)bus << PCI_REG_BUS_SHIFT | 251 (uint_t)dev << PCI_REG_DEV_SHIFT | 252 (uint_t)func << PCI_REG_FUNC_SHIFT; 253 regs[0].pci_phys_hi = devloc; 254 255 /* System Control BAR i/o space */ 256 base = (*pci_getl_func)(bus, dev, func, 257 NVIDIA_CK804_ISA_SYSCTRL_BAR_OFF); 258 regs[0].pci_size_low = assigned[0].pci_size_low = PCI_CONF_HDR_SIZE; 259 assigned[0].pci_phys_hi = regs[0].pci_phys_hi = (PCI_RELOCAT_B | 260 PCI_ADDR_IO | devloc | NVIDIA_CK804_ISA_SYSCTRL_BAR_OFF); 261 assigned[0].pci_phys_low = regs[0].pci_phys_low = 262 base & PCI_BASE_IO_ADDR_M; 263 264 /* Analog BAR i/o space */ 265 base = (*pci_getl_func)(bus, dev, func, 266 NVIDIA_CK804_ISA_ANALOG_BAR_OFF); 267 regs[1].pci_size_low = assigned[1].pci_size_low = PCI_CONF_HDR_SIZE; 268 assigned[1].pci_phys_hi = regs[1].pci_phys_hi = (PCI_RELOCAT_B | 269 PCI_ADDR_IO | devloc | NVIDIA_CK804_ISA_ANALOG_BAR_OFF); 270 assigned[1].pci_phys_low = regs[1].pci_phys_low = 271 base & PCI_BASE_IO_ADDR_M; 272 273 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg", 274 (int *)regs, 2 * sizeof (pci_regspec_t) / sizeof (int)); 275 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 276 "assigned-addresses", 277 (int *)assigned, 2 * sizeof (pci_regspec_t) / sizeof (int)); 278 } 279