1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _PCIEX_PCI_INTEL_NB5000_H 28 #define _PCIEX_PCI_INTEL_NB5000_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #define INTEL_VENDOR_ID 0x8086 37 38 /* 39 * Note: the Chipset MCH devices (i.e. host bridge/mem ctrl) for the chipsets 40 * we recognize here also provide a PCIE port for the interconnect to 41 * the south bridge (aka ESI bus) that partially acts like a root port. 42 */ 43 44 /* 45 * 25c0 5000X Chipset Memory Controller Hub 46 * 25d0 5000Z Chipset Memory Controller Hub 47 * 25d4 5000V Chipset Memory Controller Hub 48 * 25d8 5000P Chipset Memory Controller Hub 49 * 50 * 25e2 5000 Series Chipset PCI Express x4 Port 2 51 * 25e3 5000 Series Chipset PCI Express x4 Port 3 52 * 25e4 5000 Series Chipset PCI Express x4 Port 4 53 * 25e5 5000 Series Chipset PCI Express x4 Port 5 54 * 25e6 5000 Series Chipset PCI Express x4 Port 6 55 * 25e7 5000 Series Chipset PCI Express x4 Port 7 56 * 57 * 25f7 5000 Series Chipset PCI Express x8 Port 2-3 58 * 25f8 5000 Series Chipset PCI Express x8 Port 4-5 59 * 25f9 5000 Series Chipset PCI Express x8 Port 6-7 60 * 25fa 5000X Chipset PCI Express x16 Port 4-7 61 */ 62 #define INTEL_5000_PCIE_DEV_ID(did) \ 63 ((did) == 0x25c0 || \ 64 (did) == 0x25d0 || \ 65 (did) == 0x25d4 || \ 66 (did) == 0x25d8 || \ 67 ((did) >= 0x25e2 && (did) <= 0x25e7) || \ 68 ((did) >= 0x25f7 && (did) <= 0x25fa)) 69 70 /* 71 * 3600 7300 Chipset Memory Controller Hub 72 * 3604 7300 Chipset PCI Express Port 1 73 * 3605 7300 Chipset PCI Express Port 2 74 * 3606 7300 Chipset PCI Express Port 3 75 * 3607 7300 Chipset PCI Express Port 4 76 * 3608 7300 Chipset PCI Express Port 5 77 * 3609 7300 Chipset PCI Express Port 6 78 * 360a 7300 Chipset PCI Express Port 7 79 */ 80 #define INTEL_7300_PCIE_DEV_ID(did) ((did) >= 0x3600 && (did) <= 0x360a) 81 82 #define INTEL_NB5000_PCIE_DEV_ID(did) \ 83 (INTEL_5000_PCIE_DEV_ID(did) || INTEL_7300_PCIE_DEV_ID(did)) 84 85 /* 86 * Chipset specific registers 87 */ 88 #define INTEL_7300_PEXCTRL 0x48 /* PCIE Control Register */ 89 #define INTEL_7300_PEXCTRL_HPINB 0x20000000 /* Inband HP msgs */ 90 #define INTEL_7300_PEXCTRL_MSINFAT 0x40000000 /* nonfatal error MSI */ 91 #define INTEL_7300_PEXCTRL_MSICOR 0x80000000 /* correctable error MSI */ 92 93 #define INTEL_7300_PEXCTRL3 0x4D /* PCIE Control Register 3 */ 94 #define INTEL_7300_PEXCTRL3_MSIRAS 0x1 /* MSI for PCIE err enable */ 95 96 #ifdef __cplusplus 97 } 98 #endif 99 100 #endif /* _PCIEX_PCI_INTEL_NB5000_H */ 101