1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include <sys/types.h> 27 #include <sys/stat.h> 28 #include <sys/sysmacros.h> 29 #include <sys/sunndi.h> 30 #include <sys/pci.h> 31 #include <sys/pci_impl.h> 32 #include <sys/pci_cfgspace.h> 33 #include <sys/memlist.h> 34 #include <sys/bootconf.h> 35 #include <io/pci/mps_table.h> 36 #include <sys/pci_cfgspace.h> 37 #include <sys/pci_cfgspace_impl.h> 38 #include <sys/psw.h> 39 #include "../../../../common/pci/pci_strings.h" 40 #include <sys/apic.h> 41 #include <io/pciex/pcie_nvidia.h> 42 #include <io/hotplug/pciehpc/pciehpc_acpi.h> 43 #include <sys/acpi/acpi.h> 44 #include <sys/acpica.h> 45 #include <sys/intel_iommu.h> 46 #include <sys/iommulib.h> 47 48 #define pci_getb (*pci_getb_func) 49 #define pci_getw (*pci_getw_func) 50 #define pci_getl (*pci_getl_func) 51 #define pci_putb (*pci_putb_func) 52 #define pci_putw (*pci_putw_func) 53 #define pci_putl (*pci_putl_func) 54 #define dcmn_err if (pci_boot_debug) cmn_err 55 56 #define CONFIG_INFO 0 57 #define CONFIG_UPDATE 1 58 #define CONFIG_NEW 2 59 #define CONFIG_FIX 3 60 #define COMPAT_BUFSIZE 512 61 62 #define PPB_IO_ALIGNMENT 0x1000 /* 4K aligned */ 63 #define PPB_MEM_ALIGNMENT 0x100000 /* 1M aligned */ 64 /* round down to nearest power of two */ 65 #define P2LE(align) \ 66 { \ 67 int i = 0; \ 68 while (align >>= 1) \ 69 i ++; \ 70 align = 1 << i; \ 71 } \ 72 73 /* for is_vga and list_is_vga_only */ 74 75 enum io_mem { 76 IO, 77 MEM 78 }; 79 80 /* See AMD-8111 Datasheet Rev 3.03, Page 149: */ 81 #define LPC_IO_CONTROL_REG_1 0x40 82 #define AMD8111_ENABLENMI (uint8_t)0x80 83 #define DEVID_AMD8111_LPC 0x7468 84 85 struct pci_fixundo { 86 uint8_t bus; 87 uint8_t dev; 88 uint8_t fn; 89 void (*undofn)(uint8_t, uint8_t, uint8_t); 90 struct pci_fixundo *next; 91 }; 92 93 struct pci_devfunc { 94 struct pci_devfunc *next; 95 dev_info_t *dip; 96 uchar_t dev; 97 uchar_t func; 98 boolean_t reprogram; /* this device needs to be reprogrammed */ 99 }; 100 101 extern int pseudo_isa; 102 extern int pci_bios_nbus; 103 static uchar_t max_dev_pci = 32; /* PCI standard */ 104 int pci_boot_debug = 0; 105 extern struct memlist *find_bus_res(int, int); 106 static struct pci_fixundo *undolist = NULL; 107 static int num_root_bus = 0; /* count of root buses */ 108 extern volatile int acpi_resource_discovery; 109 110 /* 111 * Module prototypes 112 */ 113 static void enumerate_bus_devs(uchar_t bus, int config_op); 114 static void create_root_bus_dip(uchar_t bus); 115 static void process_devfunc(uchar_t, uchar_t, uchar_t, uchar_t, 116 ushort_t, int); 117 static void add_compatible(dev_info_t *, ushort_t, ushort_t, 118 ushort_t, ushort_t, uchar_t, uint_t, int); 119 static int add_reg_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, int); 120 static void add_ppb_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, 121 ushort_t); 122 static void add_model_prop(dev_info_t *, uint_t); 123 static void add_bus_range_prop(int); 124 static void add_bus_slot_names_prop(int); 125 static void add_ranges_prop(int, int); 126 static void add_bus_available_prop(int); 127 static int get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id); 128 static void fix_ppb_res(uchar_t, boolean_t); 129 static void alloc_res_array(); 130 static void create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 131 ushort_t deviceid); 132 static void pciex_slot_names_prop(dev_info_t *, ushort_t); 133 static void populate_bus_res(uchar_t bus); 134 static void memlist_remove_list(struct memlist **list, 135 struct memlist *remove_list); 136 137 extern int pci_slot_names_prop(int, char *, int); 138 139 /* set non-zero to force PCI peer-bus renumbering */ 140 int pci_bus_always_renumber = 0; 141 142 /* 143 * used to register ISA resource usage which must not be made 144 * "available" from other PCI node' resource maps 145 */ 146 static struct { 147 struct memlist *io_used; 148 struct memlist *mem_used; 149 } isa_res; 150 151 /* 152 * Enumerate all PCI devices 153 */ 154 void 155 pci_setup_tree() 156 { 157 uint_t i, root_bus_addr = 0; 158 159 alloc_res_array(); 160 for (i = 0; i <= pci_bios_nbus; i++) { 161 pci_bus_res[i].par_bus = (uchar_t)-1; 162 pci_bus_res[i].root_addr = (uchar_t)-1; 163 pci_bus_res[i].sub_bus = i; 164 } 165 166 pci_bus_res[0].root_addr = root_bus_addr++; 167 create_root_bus_dip(0); 168 enumerate_bus_devs(0, CONFIG_INFO); 169 170 /* 171 * Now enumerate peer busses 172 * 173 * We loop till pci_bios_nbus. On most systems, there is 174 * one more bus at the high end, which implements the ISA 175 * compatibility bus. We don't care about that. 176 * 177 * Note: In the old (bootconf) enumeration, the peer bus 178 * address did not use the bus number, and there were 179 * too many peer busses created. The root_bus_addr is 180 * used to maintain the old peer bus address assignment. 181 * However, we stop enumerating phantom peers with no 182 * device below. 183 */ 184 for (i = 1; i <= pci_bios_nbus; i++) { 185 if (pci_bus_res[i].dip == NULL) { 186 pci_bus_res[i].root_addr = root_bus_addr++; 187 } 188 enumerate_bus_devs(i, CONFIG_INFO); 189 190 /* add slot-names property for named pci hot-plug slots */ 191 add_bus_slot_names_prop(i); 192 } 193 194 } 195 196 /* 197 * >0 = present, 0 = not present, <0 = error 198 */ 199 static int 200 pci_bbn_present(int bus) 201 { 202 ACPI_HANDLE hdl; 203 int rv; 204 205 /* no dip means no _BBN */ 206 if (pci_bus_res[bus].dip == NULL) 207 return (0); 208 209 rv = -1; /* default return value in case of error below */ 210 if (ACPI_SUCCESS(acpica_get_handle(pci_bus_res[bus].dip, &hdl))) { 211 switch (AcpiEvaluateObject(hdl, "_BBN", NULL, NULL)) { 212 case AE_OK: 213 rv = 1; 214 break; 215 case AE_NOT_FOUND: 216 rv = 0; 217 break; 218 default: 219 break; 220 } 221 } 222 223 return (rv); 224 } 225 226 /* 227 * Return non-zero if any PCI bus in the system has an associated 228 * _BBN object, 0 otherwise. 229 */ 230 static int 231 pci_roots_have_bbn(void) 232 { 233 int i; 234 235 /* 236 * Scan the PCI busses and look for at least 1 _BBN 237 */ 238 for (i = 0; i <= pci_bios_nbus; i++) { 239 /* skip non-root (peer) PCI busses */ 240 if (pci_bus_res[i].par_bus != (uchar_t)-1) 241 continue; 242 243 if (pci_bbn_present(i) > 0) 244 return (1); 245 } 246 return (0); 247 248 } 249 250 /* 251 * return non-zero if the machine is one on which we renumber 252 * the internal pci unit-addresses 253 */ 254 static int 255 pci_bus_renumber() 256 { 257 ACPI_TABLE_HEADER *fadt; 258 259 if (pci_bus_always_renumber) 260 return (1); 261 262 /* get the FADT */ 263 if (AcpiGetTable(ACPI_SIG_FADT, 1, (ACPI_TABLE_HEADER **)&fadt) != 264 AE_OK) 265 return (0); 266 267 /* compare OEM Table ID to "SUNm31" */ 268 if (strncmp("SUNm31", fadt->OemId, 6)) 269 return (0); 270 else 271 return (1); 272 } 273 274 /* 275 * Initial enumeration of the physical PCI bus hierarchy can 276 * leave 'gaps' in the order of peer PCI bus unit-addresses. 277 * Systems with more than one peer PCI bus *must* have an ACPI 278 * _BBN object associated with each peer bus; use the presence 279 * of this object to remove gaps in the numbering of the peer 280 * PCI bus unit-addresses - only peer busses with an associated 281 * _BBN are counted. 282 */ 283 static void 284 pci_renumber_root_busses(void) 285 { 286 int pci_regs[] = {0, 0, 0}; 287 int i, root_addr = 0; 288 289 /* 290 * Currently, we only enable the re-numbering on specific 291 * Sun machines; this is a work-around for the more complicated 292 * issue of upgrade changing physical device paths 293 */ 294 if (!pci_bus_renumber()) 295 return; 296 297 /* 298 * If we find no _BBN objects at all, we either don't need 299 * to do anything or can't do anything anyway 300 */ 301 if (!pci_roots_have_bbn()) 302 return; 303 304 for (i = 0; i <= pci_bios_nbus; i++) { 305 /* skip non-root (peer) PCI busses */ 306 if (pci_bus_res[i].par_bus != (uchar_t)-1) 307 continue; 308 309 if (pci_bbn_present(i) < 1) { 310 pci_bus_res[i].root_addr = (uchar_t)-1; 311 continue; 312 } 313 314 ASSERT(pci_bus_res[i].dip != NULL); 315 if (pci_bus_res[i].root_addr != root_addr) { 316 /* update reg property for node */ 317 pci_bus_res[i].root_addr = root_addr; 318 pci_regs[0] = pci_bus_res[i].root_addr; 319 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 320 pci_bus_res[i].dip, "reg", (int *)pci_regs, 3); 321 } 322 root_addr++; 323 } 324 } 325 326 void 327 pci_register_isa_resources(int type, uint32_t base, uint32_t size) 328 { 329 (void) memlist_insert( 330 (type == 1) ? &isa_res.io_used : &isa_res.mem_used, 331 base, size); 332 } 333 334 /* 335 * Remove the resources which are already used by devices under a subtractive 336 * bridge from the bus's resources lists, because they're not available, and 337 * shouldn't be allocated to other buses. This is necessary because tracking 338 * resources for subtractive bridges is not complete. (Subtractive bridges only 339 * track some of their claimed resources, not "the rest of the address space" as 340 * they should, so that allocation to peer non-subtractive PPBs is easier. We 341 * need a fully-capable global resource allocator). 342 */ 343 static void 344 remove_subtractive_res() 345 { 346 int i, j; 347 struct memlist *list; 348 349 for (i = 0; i <= pci_bios_nbus; i++) { 350 if (pci_bus_res[i].subtractive) { 351 /* remove used io ports */ 352 list = pci_bus_res[i].io_used; 353 while (list) { 354 for (j = 0; j <= pci_bios_nbus; j++) 355 (void) memlist_remove( 356 &pci_bus_res[j].io_avail, 357 list->address, list->size); 358 list = list->next; 359 } 360 /* remove used mem resource */ 361 list = pci_bus_res[i].mem_used; 362 while (list) { 363 for (j = 0; j <= pci_bios_nbus; j++) { 364 (void) memlist_remove( 365 &pci_bus_res[j].mem_avail, 366 list->address, list->size); 367 (void) memlist_remove( 368 &pci_bus_res[j].pmem_avail, 369 list->address, list->size); 370 } 371 list = list->next; 372 } 373 /* remove used prefetchable mem resource */ 374 list = pci_bus_res[i].pmem_used; 375 while (list) { 376 for (j = 0; j <= pci_bios_nbus; j++) { 377 (void) memlist_remove( 378 &pci_bus_res[j].pmem_avail, 379 list->address, list->size); 380 (void) memlist_remove( 381 &pci_bus_res[j].mem_avail, 382 list->address, list->size); 383 } 384 list = list->next; 385 } 386 } 387 } 388 } 389 390 /* 391 * Set up (or complete the setup of) the bus_avail resource list 392 */ 393 static void 394 setup_bus_res(int bus) 395 { 396 uchar_t par_bus; 397 398 if (pci_bus_res[bus].dip == NULL) /* unused bus */ 399 return; 400 401 /* 402 * Set up bus_avail if not already filled in by populate_bus_res() 403 */ 404 if (pci_bus_res[bus].bus_avail == NULL) { 405 ASSERT(pci_bus_res[bus].sub_bus >= bus); 406 memlist_insert(&pci_bus_res[bus].bus_avail, bus, 407 pci_bus_res[bus].sub_bus - bus + 1); 408 } 409 410 ASSERT(pci_bus_res[bus].bus_avail != NULL); 411 412 /* 413 * Remove resources from parent bus node if this is not a 414 * root bus. 415 */ 416 par_bus = pci_bus_res[bus].par_bus; 417 if (par_bus != (uchar_t)-1) { 418 ASSERT(pci_bus_res[par_bus].bus_avail != NULL); 419 memlist_remove_list(&pci_bus_res[par_bus].bus_avail, 420 pci_bus_res[bus].bus_avail); 421 } 422 423 /* remove self from bus_avail */; 424 (void) memlist_remove(&pci_bus_res[bus].bus_avail, bus, 1); 425 } 426 427 static uint64_t 428 get_parbus_io_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align) 429 { 430 uint64_t addr = 0; 431 uchar_t res_bus; 432 433 /* 434 * Skip root(peer) buses in multiple-root-bus systems when 435 * ACPI resource discovery was not successfully done. 436 */ 437 if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) && 438 (num_root_bus > 1) && (acpi_resource_discovery <= 0)) 439 return (0); 440 441 res_bus = parbus; 442 while (pci_bus_res[res_bus].subtractive) { 443 if (pci_bus_res[res_bus].io_avail) 444 break; 445 res_bus = pci_bus_res[res_bus].par_bus; 446 if (res_bus == (uchar_t)-1) 447 break; /* root bus already */ 448 } 449 450 if (pci_bus_res[res_bus].io_avail) { 451 addr = memlist_find(&pci_bus_res[res_bus].io_avail, 452 size, align); 453 if (addr) { 454 memlist_insert(&pci_bus_res[res_bus].io_used, 455 addr, size); 456 457 /* free the old resource */ 458 memlist_free_all(&pci_bus_res[bus].io_avail); 459 memlist_free_all(&pci_bus_res[bus].io_used); 460 461 /* add the new resource */ 462 memlist_insert(&pci_bus_res[bus].io_avail, addr, size); 463 } 464 } 465 466 return (addr); 467 } 468 469 static uint64_t 470 get_parbus_mem_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align) 471 { 472 uint64_t addr = 0; 473 uchar_t res_bus; 474 475 /* 476 * Skip root(peer) buses in multiple-root-bus systems when 477 * ACPI resource discovery was not successfully done. 478 */ 479 if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) && 480 (num_root_bus > 1) && (acpi_resource_discovery <= 0)) 481 return (0); 482 483 res_bus = parbus; 484 while (pci_bus_res[res_bus].subtractive) { 485 if (pci_bus_res[res_bus].mem_avail) 486 break; 487 res_bus = pci_bus_res[res_bus].par_bus; 488 if (res_bus == (uchar_t)-1) 489 break; /* root bus already */ 490 } 491 492 if (pci_bus_res[res_bus].mem_avail) { 493 addr = memlist_find(&pci_bus_res[res_bus].mem_avail, 494 size, align); 495 if (addr) { 496 memlist_insert(&pci_bus_res[res_bus].mem_used, 497 addr, size); 498 (void) memlist_remove(&pci_bus_res[res_bus].pmem_avail, 499 addr, size); 500 501 /* free the old resource */ 502 memlist_free_all(&pci_bus_res[bus].mem_avail); 503 memlist_free_all(&pci_bus_res[bus].mem_used); 504 505 /* add the new resource */ 506 memlist_insert(&pci_bus_res[bus].mem_avail, addr, size); 507 } 508 } 509 510 return (addr); 511 } 512 513 /* 514 * given a cap_id, return its cap_id location in config space 515 */ 516 static int 517 get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id) 518 { 519 uint8_t curcap, cap_id_loc; 520 uint16_t status; 521 int location = -1; 522 523 /* 524 * Need to check the Status register for ECP support first. 525 * Also please note that for type 1 devices, the 526 * offset could change. Should support type 1 next. 527 */ 528 status = pci_getw(bus, dev, func, PCI_CONF_STAT); 529 if (!(status & PCI_STAT_CAP)) { 530 return (-1); 531 } 532 cap_id_loc = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR); 533 534 /* Walk the list of capabilities */ 535 while (cap_id_loc && cap_id_loc != (uint8_t)-1) { 536 curcap = pci_getb(bus, dev, func, cap_id_loc); 537 538 if (curcap == cap_id) { 539 location = cap_id_loc; 540 break; 541 } 542 cap_id_loc = pci_getb(bus, dev, func, cap_id_loc + 1); 543 } 544 return (location); 545 } 546 547 /* 548 * Does this resource element live in the legacy VGA range? 549 */ 550 551 int 552 is_vga(struct memlist *elem, enum io_mem io) 553 { 554 555 if (io == IO) { 556 if ((elem->address == 0x3b0 && elem->size == 0xc) || 557 (elem->address == 0x3c0 && elem->size == 0x20)) 558 return (1); 559 } else { 560 if (elem->address == 0xa0000 && elem->size == 0x20000) 561 return (1); 562 } 563 return (0); 564 } 565 566 /* 567 * Does this entire resource list consist only of legacy VGA resources? 568 */ 569 570 int 571 list_is_vga_only(struct memlist *l, enum io_mem io) 572 { 573 do { 574 if (!is_vga(l, io)) 575 return (0); 576 } while ((l = l->next) != NULL); 577 return (1); 578 } 579 580 /* 581 * Assign valid resources to unconfigured pci(e) bridges. We are trying 582 * to reprogram the bridge when its 583 * i) SECBUS == SUBBUS || 584 * ii) IOBASE > IOLIM || 585 * iii) MEMBASE > MEMLIM 586 * This must be done after one full pass through the PCI tree to collect 587 * all BIOS-configured resources, so that we know what resources are 588 * free and available to assign to the unconfigured PPBs. 589 */ 590 static void 591 fix_ppb_res(uchar_t secbus, boolean_t prog_sub) 592 { 593 uchar_t bus, dev, func; 594 uchar_t parbus, subbus; 595 uint_t io_base, io_limit, mem_base, mem_limit; 596 uint_t io_size, mem_size, io_align, mem_align; 597 uint64_t addr = 0; 598 int *regp = NULL; 599 uint_t reglen; 600 int rv, cap_ptr, physhi; 601 dev_info_t *dip; 602 uint16_t cmd_reg; 603 struct memlist *list, *scratch_list; 604 605 /* skip root (peer) PCI busses */ 606 if (pci_bus_res[secbus].par_bus == (uchar_t)-1) 607 return; 608 609 /* skip subtractive PPB when prog_sub is not TRUE */ 610 if (pci_bus_res[secbus].subtractive && !prog_sub) 611 return; 612 613 /* some entries may be empty due to discontiguous bus numbering */ 614 dip = pci_bus_res[secbus].dip; 615 if (dip == NULL) 616 return; 617 618 rv = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 619 "reg", ®p, ®len); 620 if (rv != DDI_PROP_SUCCESS || reglen == 0) 621 return; 622 physhi = regp[0]; 623 ddi_prop_free(regp); 624 625 func = (uchar_t)PCI_REG_FUNC_G(physhi); 626 dev = (uchar_t)PCI_REG_DEV_G(physhi); 627 bus = (uchar_t)PCI_REG_BUS_G(physhi); 628 629 /* 630 * If pcie bridge, check to see if link is enabled 631 */ 632 cap_ptr = get_pci_cap(bus, dev, func, PCI_CAP_ID_PCI_E); 633 if (cap_ptr != -1) { 634 cmd_reg = pci_getw(bus, dev, func, 635 (uint16_t)cap_ptr + PCIE_LINKCTL); 636 if (cmd_reg & PCIE_LINKCTL_LINK_DISABLE) { 637 dcmn_err(CE_NOTE, 638 "!fix_ppb_res: ppb[%x/%x/%x] link is disabled.\n", 639 bus, dev, func); 640 return; 641 } 642 } 643 644 subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 645 parbus = pci_bus_res[secbus].par_bus; 646 ASSERT(parbus == bus); 647 cmd_reg = pci_getw(bus, dev, func, PCI_CONF_COMM); 648 649 /* 650 * If we have a Cardbus bridge, but no bus space 651 */ 652 if (pci_bus_res[secbus].num_cbb != 0 && 653 pci_bus_res[secbus].bus_avail == NULL) { 654 uchar_t range; 655 656 /* normally there are 2 buses under a cardbus bridge */ 657 range = pci_bus_res[secbus].num_cbb * 2; 658 659 /* 660 * Try to find and allocate a bus-range starting at subbus+1 661 * from the parent of the PPB. 662 */ 663 for (; range != 0; range--) { 664 if (memlist_find_with_startaddr( 665 &pci_bus_res[parbus].bus_avail, 666 subbus + 1, range, 1) != NULL) 667 break; /* find bus range resource at parent */ 668 } 669 if (range != 0) { 670 memlist_insert(&pci_bus_res[secbus].bus_avail, 671 subbus + 1, range); 672 subbus = subbus + range; 673 pci_bus_res[secbus].sub_bus = subbus; 674 pci_putb(bus, dev, func, PCI_BCNF_SUBBUS, subbus); 675 add_bus_range_prop(secbus); 676 677 cmn_err(CE_NOTE, "!reprogram bus-range on ppb" 678 "[%x/%x/%x]: %x ~ %x\n", bus, dev, func, 679 secbus, subbus); 680 } 681 } 682 683 /* 684 * Calculate required IO size and alignment 685 * If bus io_size is zero, we are going to assign 512 bytes per bus, 686 * otherwise, we'll choose the maximum value of such calculation and 687 * bus io_size. The size needs to be 4K aligned. 688 * 689 * We calculate alignment as the largest power of two less than the 690 * the sum of all children's IO size requirements, because this will 691 * align to the size of the largest child request within that size 692 * (which is always a power of two). 693 */ 694 io_size = (subbus - secbus + 1) * 0x200; 695 if (io_size < pci_bus_res[secbus].io_size) 696 io_size = pci_bus_res[secbus].io_size; 697 io_size = P2ROUNDUP(io_size, PPB_IO_ALIGNMENT); 698 io_align = io_size; 699 P2LE(io_align); 700 701 /* 702 * Calculate required MEM size and alignment 703 * If bus mem_size is zero, we are going to assign 1M bytes per bus, 704 * otherwise, we'll choose the maximum value of such calculation and 705 * bus mem_size. The size needs to be 1M aligned. 706 * 707 * For the alignment, refer to the I/O comment above. 708 */ 709 mem_size = (subbus - secbus + 1) * PPB_MEM_ALIGNMENT; 710 if (mem_size < pci_bus_res[secbus].mem_size) { 711 mem_size = pci_bus_res[secbus].mem_size; 712 mem_size = P2ROUNDUP(mem_size, PPB_MEM_ALIGNMENT); 713 } 714 mem_align = mem_size; 715 P2LE(mem_align); 716 717 /* Subtractive bridge */ 718 if (pci_bus_res[secbus].subtractive && prog_sub) { 719 /* 720 * We program an arbitrary amount of I/O and memory resource 721 * for the subtractive bridge so that child dynamic-resource- 722 * allocating devices (such as Cardbus bridges) have a chance 723 * of success. Until we have full-tree resource rebalancing, 724 * dynamic resource allocation (thru busra) only looks at the 725 * parent bridge, so all PPBs must have some allocatable 726 * resource. For non-subtractive bridges, the resources come 727 * from the base/limit register "windows", but subtractive 728 * bridges often don't program those (since they don't need to). 729 * If we put all the remaining resources on the subtractive 730 * bridge, then peer non-subtractive bridges can't allocate 731 * more space (even though this is probably most correct). 732 * If we put the resources only on the parent, then allocations 733 * from children of subtractive bridges will fail without 734 * special-case code for bypassing the subtractive bridge. 735 * This solution is the middle-ground temporary solution until 736 * we have fully-capable resource allocation. 737 */ 738 739 /* 740 * Add an arbitrary I/O resource to the subtractive PPB 741 */ 742 if (pci_bus_res[secbus].io_avail == NULL) { 743 addr = get_parbus_io_res(parbus, secbus, io_size, 744 io_align); 745 if (addr) { 746 add_ranges_prop(secbus, 1); 747 pci_bus_res[secbus].io_reprogram = 748 pci_bus_res[parbus].io_reprogram; 749 750 cmn_err(CE_NOTE, "!add io-range on subtractive" 751 " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 752 bus, dev, func, (uint32_t)addr, 753 (uint32_t)addr + io_size - 1); 754 } 755 } 756 /* 757 * Add an arbitrary memory resource to the subtractive PPB 758 */ 759 if (pci_bus_res[secbus].mem_avail == NULL) { 760 addr = get_parbus_mem_res(parbus, secbus, mem_size, 761 mem_align); 762 if (addr) { 763 add_ranges_prop(secbus, 1); 764 pci_bus_res[secbus].mem_reprogram = 765 pci_bus_res[parbus].mem_reprogram; 766 767 cmn_err(CE_NOTE, "!add mem-range on " 768 "subtractive ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 769 bus, dev, func, (uint32_t)addr, 770 (uint32_t)addr + mem_size - 1); 771 } 772 } 773 774 goto cmd_enable; 775 } 776 777 /* 778 * Check to see if we need to reprogram I/O space, either because the 779 * parent bus needed reprogramming and so do we, or because I/O space is 780 * disabled in base/limit or command register. 781 */ 782 io_base = pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 783 io_limit = pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 784 io_base = (io_base & 0xf0) << 8; 785 io_limit = ((io_limit & 0xf0) << 8) | 0xfff; 786 787 /* Form list of all resources passed (avail + used) */ 788 scratch_list = memlist_dup(pci_bus_res[secbus].io_avail); 789 memlist_merge(&pci_bus_res[secbus].io_used, &scratch_list); 790 791 if ((pci_bus_res[parbus].io_reprogram || 792 (io_base > io_limit) || 793 (!(cmd_reg & PCI_COMM_IO))) && 794 !list_is_vga_only(scratch_list, IO)) { 795 if (pci_bus_res[secbus].io_used) { 796 memlist_subsume(&pci_bus_res[secbus].io_used, 797 &pci_bus_res[secbus].io_avail); 798 } 799 if (pci_bus_res[secbus].io_avail && 800 (!pci_bus_res[parbus].io_reprogram) && 801 (!pci_bus_res[parbus].subtractive)) { 802 /* rechoose old io ports info */ 803 list = pci_bus_res[secbus].io_avail; 804 io_base = 0; 805 do { 806 if (is_vga(list, IO)) 807 continue; 808 if (!io_base) { 809 io_base = (uint_t)list->address; 810 io_limit = (uint_t) 811 list->address + list->size - 1; 812 io_base = 813 P2ALIGN(io_base, PPB_IO_ALIGNMENT); 814 } else { 815 if (list->address + list->size > 816 io_limit) { 817 io_limit = (uint_t) 818 (list->address + 819 list->size - 1); 820 } 821 } 822 } while ((list = list->next) != NULL); 823 /* 4K aligned */ 824 io_limit = P2ROUNDUP(io_limit, PPB_IO_ALIGNMENT) - 1; 825 io_size = io_limit - io_base + 1; 826 ASSERT(io_base <= io_limit); 827 memlist_free_all(&pci_bus_res[secbus].io_avail); 828 memlist_insert(&pci_bus_res[secbus].io_avail, 829 io_base, io_size); 830 memlist_insert(&pci_bus_res[parbus].io_used, 831 io_base, io_size); 832 (void) memlist_remove(&pci_bus_res[parbus].io_avail, 833 io_base, io_size); 834 pci_bus_res[secbus].io_reprogram = B_TRUE; 835 } else { 836 /* get new io ports from parent bus */ 837 addr = get_parbus_io_res(parbus, secbus, io_size, 838 io_align); 839 if (addr) { 840 io_base = addr; 841 io_limit = addr + io_size - 1; 842 pci_bus_res[secbus].io_reprogram = B_TRUE; 843 } 844 } 845 if (pci_bus_res[secbus].io_reprogram) { 846 /* reprogram PPB regs */ 847 pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW, 848 (uchar_t)((io_base>>8) & 0xf0)); 849 pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW, 850 (uchar_t)((io_limit>>8) & 0xf0)); 851 pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0); 852 pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0); 853 add_ranges_prop(secbus, 1); 854 855 cmn_err(CE_NOTE, "!reprogram io-range on" 856 " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 857 bus, dev, func, io_base, io_limit); 858 } 859 } 860 memlist_free_all(&scratch_list); 861 862 /* 863 * Check memory space as we did I/O space. 864 */ 865 mem_base = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); 866 mem_base = (mem_base & 0xfff0) << 16; 867 mem_limit = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); 868 mem_limit = ((mem_limit & 0xfff0) << 16) | 0xfffff; 869 870 scratch_list = memlist_dup(pci_bus_res[secbus].mem_avail); 871 memlist_merge(&pci_bus_res[secbus].mem_used, &scratch_list); 872 873 if ((pci_bus_res[parbus].mem_reprogram || 874 (mem_base > mem_limit) || 875 (!(cmd_reg & PCI_COMM_MAE))) && 876 !list_is_vga_only(scratch_list, MEM)) { 877 if (pci_bus_res[secbus].mem_used) { 878 memlist_subsume(&pci_bus_res[secbus].mem_used, 879 &pci_bus_res[secbus].mem_avail); 880 } 881 if (pci_bus_res[secbus].mem_avail && 882 (!pci_bus_res[parbus].mem_reprogram) && 883 (!pci_bus_res[parbus].subtractive)) { 884 /* rechoose old mem resource */ 885 list = pci_bus_res[secbus].mem_avail; 886 mem_base = 0; 887 do { 888 if (is_vga(list, MEM)) 889 continue; 890 if (mem_base == 0) { 891 mem_base = (uint_t)list->address; 892 mem_base = P2ALIGN(mem_base, 893 PPB_MEM_ALIGNMENT); 894 mem_limit = (uint_t) 895 (list->address + list->size - 1); 896 } else { 897 if ((list->address + list->size) > 898 mem_limit) { 899 mem_limit = (uint_t) 900 (list->address + 901 list->size - 1); 902 } 903 } 904 } while ((list = list->next) != NULL); 905 mem_limit = P2ROUNDUP(mem_limit, PPB_MEM_ALIGNMENT) - 1; 906 mem_size = mem_limit + 1 - mem_base; 907 ASSERT(mem_base <= mem_limit); 908 memlist_free_all(&pci_bus_res[secbus].mem_avail); 909 memlist_insert(&pci_bus_res[secbus].mem_avail, 910 mem_base, mem_size); 911 memlist_insert(&pci_bus_res[parbus].mem_used, 912 mem_base, mem_size); 913 (void) memlist_remove(&pci_bus_res[parbus].mem_avail, 914 mem_base, mem_size); 915 pci_bus_res[secbus].mem_reprogram = B_TRUE; 916 } else { 917 /* get new mem resource from parent bus */ 918 addr = get_parbus_mem_res(parbus, secbus, mem_size, 919 mem_align); 920 if (addr) { 921 mem_base = addr; 922 mem_limit = addr + mem_size - 1; 923 pci_bus_res[secbus].mem_reprogram = B_TRUE; 924 } 925 } 926 927 if (pci_bus_res[secbus].mem_reprogram) { 928 /* reprogram PPB MEM regs */ 929 pci_putw(bus, dev, func, PCI_BCNF_MEM_BASE, 930 (uint16_t)((mem_base>>16) & 0xfff0)); 931 pci_putw(bus, dev, func, PCI_BCNF_MEM_LIMIT, 932 (uint16_t)((mem_limit>>16) & 0xfff0)); 933 /* 934 * Disable PMEM window by setting base > limit. 935 * We currently don't reprogram the PMEM like we've 936 * done for I/O and MEM. (Devices that support prefetch 937 * can use non-prefetch MEM.) Anyway, if the MEM access 938 * bit is initially disabled by BIOS, we disable the 939 * PMEM window manually by setting PMEM base > PMEM 940 * limit here, in case there are incorrect values in 941 * them from BIOS, so that we won't get in trouble once 942 * the MEM access bit is enabled at the end of this 943 * function. 944 */ 945 if (!(cmd_reg & PCI_COMM_MAE)) { 946 pci_putw(bus, dev, func, PCI_BCNF_PF_BASE_LOW, 947 0xfff0); 948 pci_putw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW, 949 0x0); 950 pci_putl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH, 951 0xffffffff); 952 pci_putl(bus, dev, func, PCI_BCNF_PF_LIMIT_HIGH, 953 0x0); 954 } 955 956 add_ranges_prop(secbus, 1); 957 958 cmn_err(CE_NOTE, "!reprogram mem-range on" 959 " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 960 bus, dev, func, mem_base, mem_limit); 961 } 962 } 963 memlist_free_all(&scratch_list); 964 965 cmd_enable: 966 if (pci_bus_res[secbus].io_avail) 967 cmd_reg |= PCI_COMM_IO | PCI_COMM_ME; 968 if (pci_bus_res[secbus].mem_avail) 969 cmd_reg |= PCI_COMM_MAE | PCI_COMM_ME; 970 pci_putw(bus, dev, func, PCI_CONF_COMM, cmd_reg); 971 } 972 973 void 974 pci_reprogram(void) 975 { 976 int i, pci_reconfig = 1; 977 char *onoff; 978 int bus; 979 980 /* 981 * Excise phantom roots if possible 982 */ 983 pci_renumber_root_busses(); 984 985 /* 986 * Do root-bus resource discovery 987 */ 988 for (bus = 0; bus <= pci_bios_nbus; bus++) { 989 /* skip non-root (peer) PCI busses */ 990 if (pci_bus_res[bus].par_bus != (uchar_t)-1) 991 continue; 992 993 /* 994 * 1. find resources associated with this root bus 995 */ 996 populate_bus_res(bus); 997 998 999 /* 1000 * 2. Remove used PCI and ISA resources from bus resource map 1001 */ 1002 1003 memlist_remove_list(&pci_bus_res[bus].io_avail, 1004 pci_bus_res[bus].io_used); 1005 memlist_remove_list(&pci_bus_res[bus].mem_avail, 1006 pci_bus_res[bus].mem_used); 1007 memlist_remove_list(&pci_bus_res[bus].pmem_avail, 1008 pci_bus_res[bus].pmem_used); 1009 memlist_remove_list(&pci_bus_res[bus].mem_avail, 1010 pci_bus_res[bus].pmem_used); 1011 memlist_remove_list(&pci_bus_res[bus].pmem_avail, 1012 pci_bus_res[bus].mem_used); 1013 1014 memlist_remove_list(&pci_bus_res[bus].io_avail, 1015 isa_res.io_used); 1016 memlist_remove_list(&pci_bus_res[bus].mem_avail, 1017 isa_res.mem_used); 1018 } 1019 1020 memlist_free_all(&isa_res.io_used); 1021 memlist_free_all(&isa_res.mem_used); 1022 1023 /* add bus-range property for root/peer bus nodes */ 1024 for (i = 0; i <= pci_bios_nbus; i++) { 1025 /* create bus-range property on root/peer buses */ 1026 if (pci_bus_res[i].par_bus == (uchar_t)-1) 1027 add_bus_range_prop(i); 1028 1029 /* setup bus range resource on each bus */ 1030 setup_bus_res(i); 1031 } 1032 1033 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(), 1034 DDI_PROP_DONTPASS, "pci-reprog", &onoff) == DDI_SUCCESS) { 1035 if (strcmp(onoff, "off") == 0) { 1036 pci_reconfig = 0; 1037 cmn_err(CE_NOTE, "pci device reprogramming disabled"); 1038 } 1039 ddi_prop_free(onoff); 1040 } 1041 1042 remove_subtractive_res(); 1043 1044 /* reprogram the non-subtractive PPB */ 1045 if (pci_reconfig) 1046 for (i = 0; i <= pci_bios_nbus; i++) 1047 fix_ppb_res(i, B_FALSE); 1048 1049 for (i = 0; i <= pci_bios_nbus; i++) { 1050 /* configure devices not configured by BIOS */ 1051 if (pci_reconfig) { 1052 /* 1053 * Reprogram the subtractive PPB. At this time, all its 1054 * siblings should have got their resources already. 1055 */ 1056 if (pci_bus_res[i].subtractive) 1057 fix_ppb_res(i, B_TRUE); 1058 enumerate_bus_devs(i, CONFIG_NEW); 1059 } 1060 } 1061 1062 /* All dev programmed, so we can create available prop */ 1063 for (i = 0; i <= pci_bios_nbus; i++) 1064 add_bus_available_prop(i); 1065 } 1066 1067 /* 1068 * populate bus resources 1069 */ 1070 static void 1071 populate_bus_res(uchar_t bus) 1072 { 1073 1074 /* scan BIOS structures */ 1075 pci_bus_res[bus].pmem_avail = find_bus_res(bus, PREFETCH_TYPE); 1076 pci_bus_res[bus].mem_avail = find_bus_res(bus, MEM_TYPE); 1077 pci_bus_res[bus].io_avail = find_bus_res(bus, IO_TYPE); 1078 pci_bus_res[bus].bus_avail = find_bus_res(bus, BUSRANGE_TYPE); 1079 1080 /* 1081 * attempt to initialize sub_bus from the largest range-end 1082 * in the bus_avail list 1083 */ 1084 if (pci_bus_res[bus].bus_avail != NULL) { 1085 struct memlist *entry; 1086 int current; 1087 1088 entry = pci_bus_res[bus].bus_avail; 1089 while (entry != NULL) { 1090 current = entry->address + entry->size - 1; 1091 if (current > pci_bus_res[bus].sub_bus) 1092 pci_bus_res[bus].sub_bus = current; 1093 entry = entry->next; 1094 } 1095 } 1096 1097 if (bus == 0) { 1098 /* 1099 * Special treatment of bus 0: 1100 * If no IO/MEM resource from ACPI/MPSPEC/HRT, copy 1101 * pcimem from boot and make I/O space the entire range 1102 * starting at 0x100. 1103 */ 1104 if (pci_bus_res[0].mem_avail == NULL) 1105 pci_bus_res[0].mem_avail = 1106 memlist_dup(bootops->boot_mem->pcimem); 1107 /* Exclude 0x00 to 0xff of the I/O space, used by all PCs */ 1108 if (pci_bus_res[0].io_avail == NULL) 1109 memlist_insert(&pci_bus_res[0].io_avail, 0x100, 0xffff); 1110 } 1111 1112 /* 1113 * Create 'ranges' property here before any resources are 1114 * removed from the resource lists 1115 */ 1116 add_ranges_prop(bus, 0); 1117 } 1118 1119 1120 /* 1121 * Create top-level bus dips, i.e. /pci@0,0, /pci@1,0... 1122 */ 1123 static void 1124 create_root_bus_dip(uchar_t bus) 1125 { 1126 int pci_regs[] = {0, 0, 0}; 1127 dev_info_t *dip; 1128 1129 ASSERT(pci_bus_res[bus].par_bus == (uchar_t)-1); 1130 1131 num_root_bus++; 1132 ndi_devi_alloc_sleep(ddi_root_node(), "pci", 1133 (pnode_t)DEVI_SID_NODEID, &dip); 1134 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1135 "#address-cells", 3); 1136 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1137 "#size-cells", 2); 1138 pci_regs[0] = pci_bus_res[bus].root_addr; 1139 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1140 "reg", (int *)pci_regs, 3); 1141 1142 /* 1143 * If system has PCIe bus, then create different properties 1144 */ 1145 if (create_pcie_root_bus(bus, dip) == B_FALSE) 1146 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1147 "device_type", "pci"); 1148 1149 (void) ndi_devi_bind_driver(dip, 0); 1150 pci_bus_res[bus].dip = dip; 1151 } 1152 1153 /* 1154 * For any fixed configuration (often compatability) pci devices 1155 * and those with their own expansion rom, create device nodes 1156 * to hold the already configured device details. 1157 */ 1158 void 1159 enumerate_bus_devs(uchar_t bus, int config_op) 1160 { 1161 uchar_t dev, func, nfunc, header; 1162 ushort_t venid; 1163 struct pci_devfunc *devlist = NULL, *entry; 1164 1165 if (config_op == CONFIG_NEW) { 1166 dcmn_err(CE_NOTE, "configuring pci bus 0x%x", bus); 1167 } else if (config_op == CONFIG_FIX) { 1168 dcmn_err(CE_NOTE, "fixing devices on pci bus 0x%x", bus); 1169 } else 1170 dcmn_err(CE_NOTE, "enumerating pci bus 0x%x", bus); 1171 1172 if (config_op == CONFIG_NEW) { 1173 devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 1174 while (devlist) { 1175 entry = devlist; 1176 devlist = entry->next; 1177 if (entry->reprogram || 1178 pci_bus_res[bus].io_reprogram || 1179 pci_bus_res[bus].mem_reprogram) { 1180 /* reprogram device(s) */ 1181 (void) add_reg_props(entry->dip, bus, 1182 entry->dev, entry->func, CONFIG_NEW, 0); 1183 } 1184 kmem_free(entry, sizeof (*entry)); 1185 } 1186 pci_bus_res[bus].privdata = NULL; 1187 return; 1188 } 1189 1190 for (dev = 0; dev < max_dev_pci; dev++) { 1191 nfunc = 1; 1192 for (func = 0; func < nfunc; func++) { 1193 1194 dcmn_err(CE_NOTE, "probing dev 0x%x, func 0x%x", 1195 dev, func); 1196 1197 venid = pci_getw(bus, dev, func, PCI_CONF_VENID); 1198 1199 if ((venid == 0xffff) || (venid == 0)) { 1200 /* no function at this address */ 1201 continue; 1202 } 1203 1204 header = pci_getb(bus, dev, func, PCI_CONF_HEADER); 1205 if (header == 0xff) { 1206 continue; /* illegal value */ 1207 } 1208 1209 /* 1210 * according to some mail from Microsoft posted 1211 * to the pci-drivers alias, their only requirement 1212 * for a multifunction device is for the 1st 1213 * function to have to PCI_HEADER_MULTI bit set. 1214 */ 1215 if ((func == 0) && (header & PCI_HEADER_MULTI)) { 1216 nfunc = 8; 1217 } 1218 1219 if (config_op == CONFIG_FIX || 1220 config_op == CONFIG_INFO) { 1221 /* 1222 * Create the node, unconditionally, on the 1223 * first pass only. It may still need 1224 * resource assignment, which will be 1225 * done on the second, CONFIG_NEW, pass. 1226 */ 1227 process_devfunc(bus, dev, func, header, 1228 venid, config_op); 1229 1230 } 1231 } 1232 } 1233 1234 /* percolate bus used resources up through parents to root */ 1235 if (config_op == CONFIG_INFO) { 1236 int par_bus; 1237 1238 par_bus = pci_bus_res[bus].par_bus; 1239 while (par_bus != (uchar_t)-1) { 1240 pci_bus_res[par_bus].io_size += 1241 pci_bus_res[bus].io_size; 1242 pci_bus_res[par_bus].mem_size += 1243 pci_bus_res[bus].mem_size; 1244 1245 if (pci_bus_res[bus].io_used) 1246 memlist_merge(&pci_bus_res[bus].io_used, 1247 &pci_bus_res[par_bus].io_used); 1248 1249 if (pci_bus_res[bus].mem_used) 1250 memlist_merge(&pci_bus_res[bus].mem_used, 1251 &pci_bus_res[par_bus].mem_used); 1252 1253 if (pci_bus_res[bus].pmem_used) 1254 memlist_merge(&pci_bus_res[bus].pmem_used, 1255 &pci_bus_res[par_bus].pmem_used); 1256 1257 bus = par_bus; 1258 par_bus = pci_bus_res[par_bus].par_bus; 1259 } 1260 } 1261 } 1262 1263 static int 1264 check_pciide_prop(uchar_t revid, ushort_t venid, ushort_t devid, 1265 ushort_t subvenid, ushort_t subdevid) 1266 { 1267 static int prop_exist = -1; 1268 static char *pciide_str; 1269 char compat[32]; 1270 1271 if (prop_exist == -1) { 1272 prop_exist = (ddi_prop_lookup_string(DDI_DEV_T_ANY, 1273 ddi_root_node(), DDI_PROP_DONTPASS, "pci-ide", 1274 &pciide_str) == DDI_SUCCESS); 1275 } 1276 1277 if (!prop_exist) 1278 return (0); 1279 1280 /* compare property value against various forms of compatible */ 1281 if (subvenid) { 1282 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x.%x", 1283 venid, devid, subvenid, subdevid, revid); 1284 if (strcmp(pciide_str, compat) == 0) 1285 return (1); 1286 1287 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x", 1288 venid, devid, subvenid, subdevid); 1289 if (strcmp(pciide_str, compat) == 0) 1290 return (1); 1291 1292 (void) snprintf(compat, sizeof (compat), "pci%x,%x", 1293 subvenid, subdevid); 1294 if (strcmp(pciide_str, compat) == 0) 1295 return (1); 1296 } 1297 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x", 1298 venid, devid, revid); 1299 if (strcmp(pciide_str, compat) == 0) 1300 return (1); 1301 1302 (void) snprintf(compat, sizeof (compat), "pci%x,%x", venid, devid); 1303 if (strcmp(pciide_str, compat) == 0) 1304 return (1); 1305 1306 return (0); 1307 } 1308 1309 static int 1310 is_pciide(uchar_t basecl, uchar_t subcl, uchar_t revid, 1311 ushort_t venid, ushort_t devid, ushort_t subvenid, ushort_t subdevid) 1312 { 1313 struct ide_table { /* table for PCI_MASS_OTHER */ 1314 ushort_t venid; 1315 ushort_t devid; 1316 } *entry; 1317 1318 /* XXX SATA and other devices: need a way to add dynamically */ 1319 static struct ide_table ide_other[] = { 1320 {0x1095, 0x3112}, 1321 {0x1095, 0x3114}, 1322 {0x1095, 0x3512}, 1323 {0x1095, 0x680}, /* Sil0680 */ 1324 {0x1283, 0x8211}, /* ITE 8211F is subcl PCI_MASS_OTHER */ 1325 {0, 0} 1326 }; 1327 1328 if (basecl != PCI_CLASS_MASS) 1329 return (0); 1330 1331 if (subcl == PCI_MASS_IDE) { 1332 return (1); 1333 } 1334 1335 if (check_pciide_prop(revid, venid, devid, subvenid, subdevid)) 1336 return (1); 1337 1338 if (subcl != PCI_MASS_OTHER && subcl != PCI_MASS_SATA) { 1339 return (0); 1340 } 1341 1342 entry = &ide_other[0]; 1343 while (entry->venid) { 1344 if (entry->venid == venid && entry->devid == devid) 1345 return (1); 1346 entry++; 1347 } 1348 return (0); 1349 } 1350 1351 static int 1352 is_display(uint_t classcode) 1353 { 1354 static uint_t disp_classes[] = { 1355 0x000100, 1356 0x030000, 1357 0x030001 1358 }; 1359 int i, nclasses = sizeof (disp_classes) / sizeof (uint_t); 1360 1361 for (i = 0; i < nclasses; i++) { 1362 if (classcode == disp_classes[i]) 1363 return (1); 1364 } 1365 return (0); 1366 } 1367 1368 static void 1369 add_undofix_entry(uint8_t bus, uint8_t dev, uint8_t fn, 1370 void (*undofn)(uint8_t, uint8_t, uint8_t)) 1371 { 1372 struct pci_fixundo *newundo; 1373 1374 newundo = kmem_alloc(sizeof (struct pci_fixundo), KM_SLEEP); 1375 1376 /* 1377 * Adding an item to this list means that we must turn its NMIENABLE 1378 * bit back on at a later time. 1379 */ 1380 newundo->bus = bus; 1381 newundo->dev = dev; 1382 newundo->fn = fn; 1383 newundo->undofn = undofn; 1384 newundo->next = undolist; 1385 1386 /* add to the undo list in LIFO order */ 1387 undolist = newundo; 1388 } 1389 1390 void 1391 add_pci_fixes(void) 1392 { 1393 int i; 1394 1395 for (i = 0; i <= pci_bios_nbus; i++) { 1396 /* 1397 * For each bus, apply needed fixes to the appropriate devices. 1398 * This must be done before the main enumeration loop because 1399 * some fixes must be applied to devices normally encountered 1400 * later in the pci scan (e.g. if a fix to device 7 must be 1401 * applied before scanning device 6, applying fixes in the 1402 * normal enumeration loop would obviously be too late). 1403 */ 1404 enumerate_bus_devs(i, CONFIG_FIX); 1405 } 1406 } 1407 1408 void 1409 undo_pci_fixes(void) 1410 { 1411 struct pci_fixundo *nextundo; 1412 uint8_t bus, dev, fn; 1413 1414 /* 1415 * All fixes in the undo list are performed unconditionally. Future 1416 * fixes may require selective undo. 1417 */ 1418 while (undolist != NULL) { 1419 1420 bus = undolist->bus; 1421 dev = undolist->dev; 1422 fn = undolist->fn; 1423 1424 (*(undolist->undofn))(bus, dev, fn); 1425 1426 nextundo = undolist->next; 1427 kmem_free(undolist, sizeof (struct pci_fixundo)); 1428 undolist = nextundo; 1429 } 1430 } 1431 1432 static void 1433 undo_amd8111_pci_fix(uint8_t bus, uint8_t dev, uint8_t fn) 1434 { 1435 uint8_t val8; 1436 1437 val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 1438 /* 1439 * The NMIONERR bit is turned back on to allow the SMM BIOS 1440 * to handle more critical PCI errors (e.g. PERR#). 1441 */ 1442 val8 |= AMD8111_ENABLENMI; 1443 pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 1444 } 1445 1446 static void 1447 pci_fix_amd8111(uint8_t bus, uint8_t dev, uint8_t fn) 1448 { 1449 uint8_t val8; 1450 1451 val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 1452 1453 if ((val8 & AMD8111_ENABLENMI) == 0) 1454 return; 1455 1456 /* 1457 * We reset NMIONERR in the LPC because master-abort on the PCI 1458 * bridge side of the 8111 will cause NMI, which might cause SMI, 1459 * which sometimes prevents all devices from being enumerated. 1460 */ 1461 val8 &= ~AMD8111_ENABLENMI; 1462 1463 pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 1464 1465 add_undofix_entry(bus, dev, fn, undo_amd8111_pci_fix); 1466 } 1467 1468 static void 1469 set_devpm_d0(uchar_t bus, uchar_t dev, uchar_t func) 1470 { 1471 uint16_t status; 1472 uint8_t header; 1473 uint8_t cap_ptr; 1474 uint8_t cap_id; 1475 uint16_t pmcsr; 1476 1477 status = pci_getw(bus, dev, func, PCI_CONF_STAT); 1478 if (!(status & PCI_STAT_CAP)) 1479 return; /* No capabilities list */ 1480 1481 header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 1482 if (header == PCI_HEADER_CARDBUS) 1483 cap_ptr = pci_getb(bus, dev, func, PCI_CBUS_CAP_PTR); 1484 else 1485 cap_ptr = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR); 1486 /* 1487 * Walk the capabilities list searching for a PM entry. 1488 */ 1489 while (cap_ptr != PCI_CAP_NEXT_PTR_NULL && cap_ptr >= PCI_CAP_PTR_OFF) { 1490 cap_ptr &= PCI_CAP_PTR_MASK; 1491 cap_id = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_ID); 1492 if (cap_id == PCI_CAP_ID_PM) { 1493 pmcsr = pci_getw(bus, dev, func, cap_ptr + PCI_PMCSR); 1494 pmcsr &= ~(PCI_PMCSR_STATE_MASK); 1495 pmcsr |= PCI_PMCSR_D0; /* D0 state */ 1496 pci_putw(bus, dev, func, cap_ptr + PCI_PMCSR, pmcsr); 1497 break; 1498 } 1499 cap_ptr = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_NEXT_PTR); 1500 } 1501 1502 } 1503 1504 #define is_isa(bc, sc) \ 1505 (((bc) == PCI_CLASS_BRIDGE) && ((sc) == PCI_BRIDGE_ISA)) 1506 1507 static void 1508 process_devfunc(uchar_t bus, uchar_t dev, uchar_t func, uchar_t header, 1509 ushort_t vendorid, int config_op) 1510 { 1511 char nodename[32], unitaddr[5]; 1512 dev_info_t *dip; 1513 uchar_t basecl, subcl, progcl, intr, revid; 1514 ushort_t subvenid, subdevid, status; 1515 ushort_t slot_num; 1516 uint_t classcode, revclass; 1517 int reprogram = 0, pciide = 0; 1518 int power[2] = {1, 1}; 1519 int pciex = 0; 1520 ushort_t is_pci_bridge = 0; 1521 struct pci_devfunc *devlist = NULL, *entry = NULL; 1522 gfx_entry_t *gfxp; 1523 1524 ushort_t deviceid = pci_getw(bus, dev, func, PCI_CONF_DEVID); 1525 1526 switch (header & PCI_HEADER_TYPE_M) { 1527 case PCI_HEADER_ZERO: 1528 subvenid = pci_getw(bus, dev, func, PCI_CONF_SUBVENID); 1529 subdevid = pci_getw(bus, dev, func, PCI_CONF_SUBSYSID); 1530 break; 1531 case PCI_HEADER_CARDBUS: 1532 subvenid = pci_getw(bus, dev, func, PCI_CBUS_SUBVENID); 1533 subdevid = pci_getw(bus, dev, func, PCI_CBUS_SUBSYSID); 1534 /* Record the # of cardbus bridges found on the bus */ 1535 if (config_op == CONFIG_INFO) 1536 pci_bus_res[bus].num_cbb++; 1537 break; 1538 default: 1539 subvenid = 0; 1540 subdevid = 0; 1541 break; 1542 } 1543 1544 if (config_op == CONFIG_FIX) { 1545 if (vendorid == VENID_AMD && deviceid == DEVID_AMD8111_LPC) { 1546 pci_fix_amd8111(bus, dev, func); 1547 } 1548 return; 1549 } 1550 1551 /* XXX should be use generic names? derive from class? */ 1552 revclass = pci_getl(bus, dev, func, PCI_CONF_REVID); 1553 classcode = revclass >> 8; 1554 revid = revclass & 0xff; 1555 1556 /* figure out if this is pci-ide */ 1557 basecl = classcode >> 16; 1558 subcl = (classcode >> 8) & 0xff; 1559 progcl = classcode & 0xff; 1560 1561 1562 if (is_display(classcode)) 1563 (void) snprintf(nodename, sizeof (nodename), "display"); 1564 else if (!pseudo_isa && is_isa(basecl, subcl)) 1565 (void) snprintf(nodename, sizeof (nodename), "isa"); 1566 else if (subvenid != 0) 1567 (void) snprintf(nodename, sizeof (nodename), 1568 "pci%x,%x", subvenid, subdevid); 1569 else 1570 (void) snprintf(nodename, sizeof (nodename), 1571 "pci%x,%x", vendorid, deviceid); 1572 1573 /* make sure parent bus dip has been created */ 1574 if (pci_bus_res[bus].dip == NULL) 1575 create_root_bus_dip(bus); 1576 1577 ndi_devi_alloc_sleep(pci_bus_res[bus].dip, nodename, 1578 DEVI_SID_NODEID, &dip); 1579 1580 if (check_if_device_is_pciex(dip, bus, dev, func, &slot_num, 1581 &is_pci_bridge) == B_TRUE) 1582 pciex = 1; 1583 1584 /* add properties */ 1585 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "device-id", deviceid); 1586 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "vendor-id", vendorid); 1587 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "revision-id", revid); 1588 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1589 "class-code", classcode); 1590 if (func == 0) 1591 (void) snprintf(unitaddr, sizeof (unitaddr), "%x", dev); 1592 else 1593 (void) snprintf(unitaddr, sizeof (unitaddr), 1594 "%x,%x", dev, func); 1595 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1596 "unit-address", unitaddr); 1597 1598 /* add device_type for display nodes */ 1599 if (is_display(classcode)) { 1600 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1601 "device_type", "display"); 1602 } 1603 /* add special stuff for header type */ 1604 if ((header & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) { 1605 uchar_t mingrant = pci_getb(bus, dev, func, PCI_CONF_MIN_G); 1606 uchar_t maxlatency = pci_getb(bus, dev, func, PCI_CONF_MAX_L); 1607 1608 if (subvenid != 0) { 1609 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1610 "subsystem-id", subdevid); 1611 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1612 "subsystem-vendor-id", subvenid); 1613 } 1614 if (!pciex) 1615 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1616 "min-grant", mingrant); 1617 if (!pciex) 1618 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1619 "max-latency", maxlatency); 1620 } 1621 1622 /* interrupt, record if not 0 */ 1623 intr = pci_getb(bus, dev, func, PCI_CONF_IPIN); 1624 if (intr != 0) 1625 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1626 "interrupts", intr); 1627 1628 /* 1629 * Add support for 133 mhz pci eventually 1630 */ 1631 status = pci_getw(bus, dev, func, PCI_CONF_STAT); 1632 1633 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1634 "devsel-speed", (status & PCI_STAT_DEVSELT) >> 9); 1635 if (!pciex && (status & PCI_STAT_FBBC)) 1636 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 1637 "fast-back-to-back"); 1638 if (!pciex && (status & PCI_STAT_66MHZ)) 1639 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 1640 "66mhz-capable"); 1641 if (status & PCI_STAT_UDF) 1642 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 1643 "udf-supported"); 1644 if (pciex && slot_num) { 1645 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1646 "physical-slot#", slot_num); 1647 if (!is_pci_bridge) 1648 pciex_slot_names_prop(dip, slot_num); 1649 } 1650 1651 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1652 "power-consumption", power, 2); 1653 1654 /* Set the device PM state to D0 */ 1655 set_devpm_d0(bus, dev, func); 1656 1657 if ((basecl == PCI_CLASS_BRIDGE) && (subcl == PCI_BRIDGE_PCI)) 1658 add_ppb_props(dip, bus, dev, func, pciex, is_pci_bridge); 1659 else { 1660 /* 1661 * Record the non-PPB devices on the bus for possible 1662 * reprogramming at 2nd bus enumeration. 1663 * Note: PPB reprogramming is done in fix_ppb_res() 1664 */ 1665 devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 1666 entry = kmem_zalloc(sizeof (*entry), KM_SLEEP); 1667 entry->dip = dip; 1668 entry->dev = dev; 1669 entry->func = func; 1670 entry->next = devlist; 1671 pci_bus_res[bus].privdata = entry; 1672 } 1673 1674 if (config_op == CONFIG_INFO && 1675 IS_CLASS_IOAPIC(basecl, subcl, progcl)) { 1676 create_ioapic_node(bus, dev, func, vendorid, deviceid); 1677 } 1678 1679 /* check for ck8-04 based PCI ISA bridge only */ 1680 if (NVIDIA_IS_LPC_BRIDGE(vendorid, deviceid) && (dev == 1) && 1681 (func == 0)) 1682 add_nvidia_isa_bridge_props(dip, bus, dev, func); 1683 1684 if (pciex && is_pci_bridge) 1685 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 1686 (char *)"PCIe-PCI bridge"); 1687 else 1688 add_model_prop(dip, classcode); 1689 1690 add_compatible(dip, subvenid, subdevid, vendorid, deviceid, 1691 revid, classcode, pciex); 1692 1693 /* 1694 * See if this device is a controller that advertises 1695 * itself to be a standard ATA task file controller, or one that 1696 * has been hard coded. 1697 * 1698 * If it is, check if any other higher precedence driver listed in 1699 * driver_aliases will claim the node by calling 1700 * ddi_compatibile_driver_major. If so, clear pciide and do not 1701 * create a pci-ide node or any other special handling. 1702 * 1703 * If another driver does not bind, set the node name to pci-ide 1704 * and then let the special pci-ide handling for registers and 1705 * child pci-ide nodes proceed below. 1706 */ 1707 if (is_pciide(basecl, subcl, revid, vendorid, deviceid, 1708 subvenid, subdevid) == 1) { 1709 if (ddi_compatible_driver_major(dip, NULL) == (major_t)-1) { 1710 (void) ndi_devi_set_nodename(dip, "pci-ide", 0); 1711 pciide = 1; 1712 } 1713 } 1714 1715 reprogram = add_reg_props(dip, bus, dev, func, config_op, pciide); 1716 (void) ndi_devi_bind_driver(dip, 0); 1717 1718 /* special handling for pci-ide */ 1719 if (pciide) { 1720 dev_info_t *cdip; 1721 1722 /* 1723 * Create properties specified by P1275 Working Group 1724 * Proposal #414 Version 1 1725 */ 1726 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1727 "device_type", "pci-ide"); 1728 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1729 "#address-cells", 1); 1730 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1731 "#size-cells", 0); 1732 1733 /* allocate two child nodes */ 1734 ndi_devi_alloc_sleep(dip, "ide", 1735 (pnode_t)DEVI_SID_NODEID, &cdip); 1736 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 1737 "reg", 0); 1738 (void) ndi_devi_bind_driver(cdip, 0); 1739 ndi_devi_alloc_sleep(dip, "ide", 1740 (pnode_t)DEVI_SID_NODEID, &cdip); 1741 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 1742 "reg", 1); 1743 (void) ndi_devi_bind_driver(cdip, 0); 1744 1745 reprogram = 0; /* don't reprogram pci-ide bridge */ 1746 } 1747 1748 if (is_display(classcode)) { 1749 gfxp = kmem_zalloc(sizeof (*gfxp), KM_SLEEP); 1750 gfxp->g_dip = dip; 1751 gfxp->g_prev = NULL; 1752 gfxp->g_next = gfx_devinfo_list; 1753 gfx_devinfo_list = gfxp; 1754 if (gfxp->g_next) 1755 gfxp->g_next->g_prev = gfxp; 1756 } 1757 1758 /* special handling for isa */ 1759 if (!pseudo_isa && is_isa(basecl, subcl)) { 1760 /* add device_type */ 1761 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1762 "device_type", "isa"); 1763 } 1764 1765 if (reprogram && (entry != NULL)) 1766 entry->reprogram = B_TRUE; 1767 1768 } 1769 1770 /* 1771 * Some vendors do not use unique subsystem IDs in their products, which 1772 * makes the use of form 2 compatible names (pciSSSS,ssss) inappropriate. 1773 * Allow for these compatible forms to be excluded on a per-device basis. 1774 */ 1775 /*ARGSUSED*/ 1776 static boolean_t 1777 subsys_compat_exclude(ushort_t venid, ushort_t devid, ushort_t subvenid, 1778 ushort_t subdevid, uchar_t revid, uint_t classcode) 1779 { 1780 /* Nvidia display adapters */ 1781 if ((venid == 0x10de) && (is_display(classcode))) 1782 return (B_TRUE); 1783 1784 return (B_FALSE); 1785 } 1786 1787 /* 1788 * Set the compatible property to a value compliant with 1789 * rev 2.1 of the IEEE1275 PCI binding. 1790 * (Also used for PCI-Express devices). 1791 * 1792 * pciVVVV,DDDD.SSSS.ssss.RR (0) 1793 * pciVVVV,DDDD.SSSS.ssss (1) 1794 * pciSSSS,ssss (2) 1795 * pciVVVV,DDDD.RR (3) 1796 * pciVVVV,DDDD (4) 1797 * pciclass,CCSSPP (5) 1798 * pciclass,CCSS (6) 1799 * 1800 * The Subsystem (SSSS) forms are not inserted if 1801 * subsystem-vendor-id is 0. 1802 * 1803 * NOTE: For PCI-Express devices "pci" is replaced with "pciex" in 0-6 above 1804 * property 2 is not created as per "1275 bindings for PCI Express Interconnect" 1805 * 1806 * Set with setprop and \x00 between each 1807 * to generate the encoded string array form. 1808 */ 1809 void 1810 add_compatible(dev_info_t *dip, ushort_t subvenid, ushort_t subdevid, 1811 ushort_t vendorid, ushort_t deviceid, uchar_t revid, uint_t classcode, 1812 int pciex) 1813 { 1814 int i = 0; 1815 int size = COMPAT_BUFSIZE; 1816 char *compat[13]; 1817 char *buf, *curr; 1818 1819 curr = buf = kmem_alloc(size, KM_SLEEP); 1820 1821 if (pciex) { 1822 if (subvenid) { 1823 compat[i++] = curr; /* form 0 */ 1824 (void) snprintf(curr, size, "pciex%x,%x.%x.%x.%x", 1825 vendorid, deviceid, subvenid, subdevid, revid); 1826 size -= strlen(curr) + 1; 1827 curr += strlen(curr) + 1; 1828 1829 compat[i++] = curr; /* form 1 */ 1830 (void) snprintf(curr, size, "pciex%x,%x.%x.%x", 1831 vendorid, deviceid, subvenid, subdevid); 1832 size -= strlen(curr) + 1; 1833 curr += strlen(curr) + 1; 1834 1835 } 1836 compat[i++] = curr; /* form 3 */ 1837 (void) snprintf(curr, size, "pciex%x,%x.%x", 1838 vendorid, deviceid, revid); 1839 size -= strlen(curr) + 1; 1840 curr += strlen(curr) + 1; 1841 1842 compat[i++] = curr; /* form 4 */ 1843 (void) snprintf(curr, size, "pciex%x,%x", vendorid, deviceid); 1844 size -= strlen(curr) + 1; 1845 curr += strlen(curr) + 1; 1846 1847 compat[i++] = curr; /* form 5 */ 1848 (void) snprintf(curr, size, "pciexclass,%06x", classcode); 1849 size -= strlen(curr) + 1; 1850 curr += strlen(curr) + 1; 1851 1852 compat[i++] = curr; /* form 6 */ 1853 (void) snprintf(curr, size, "pciexclass,%04x", 1854 (classcode >> 8)); 1855 size -= strlen(curr) + 1; 1856 curr += strlen(curr) + 1; 1857 } 1858 1859 if (subvenid) { 1860 compat[i++] = curr; /* form 0 */ 1861 (void) snprintf(curr, size, "pci%x,%x.%x.%x.%x", 1862 vendorid, deviceid, subvenid, subdevid, revid); 1863 size -= strlen(curr) + 1; 1864 curr += strlen(curr) + 1; 1865 1866 compat[i++] = curr; /* form 1 */ 1867 (void) snprintf(curr, size, "pci%x,%x.%x.%x", 1868 vendorid, deviceid, subvenid, subdevid); 1869 size -= strlen(curr) + 1; 1870 curr += strlen(curr) + 1; 1871 1872 if (subsys_compat_exclude(vendorid, deviceid, subvenid, 1873 subdevid, revid, classcode) == B_FALSE) { 1874 compat[i++] = curr; /* form 2 */ 1875 (void) snprintf(curr, size, "pci%x,%x", subvenid, 1876 subdevid); 1877 size -= strlen(curr) + 1; 1878 curr += strlen(curr) + 1; 1879 } 1880 } 1881 compat[i++] = curr; /* form 3 */ 1882 (void) snprintf(curr, size, "pci%x,%x.%x", vendorid, deviceid, revid); 1883 size -= strlen(curr) + 1; 1884 curr += strlen(curr) + 1; 1885 1886 compat[i++] = curr; /* form 4 */ 1887 (void) snprintf(curr, size, "pci%x,%x", vendorid, deviceid); 1888 size -= strlen(curr) + 1; 1889 curr += strlen(curr) + 1; 1890 1891 compat[i++] = curr; /* form 5 */ 1892 (void) snprintf(curr, size, "pciclass,%06x", classcode); 1893 size -= strlen(curr) + 1; 1894 curr += strlen(curr) + 1; 1895 1896 compat[i++] = curr; /* form 6 */ 1897 (void) snprintf(curr, size, "pciclass,%04x", (classcode >> 8)); 1898 size -= strlen(curr) + 1; 1899 curr += strlen(curr) + 1; 1900 1901 (void) ndi_prop_update_string_array(DDI_DEV_T_NONE, dip, 1902 "compatible", compat, i); 1903 kmem_free(buf, COMPAT_BUFSIZE); 1904 } 1905 1906 /* 1907 * Adjust the reg properties for a dual channel PCI-IDE device. 1908 * 1909 * NOTE: don't do anything that changes the order of the hard-decodes 1910 * and programmed BARs. The kernel driver depends on these values 1911 * being in this order regardless of whether they're for a 'native' 1912 * mode BAR or not. 1913 */ 1914 /* 1915 * config info for pci-ide devices 1916 */ 1917 static struct { 1918 uchar_t native_mask; /* 0 == 'compatibility' mode, 1 == native */ 1919 uchar_t bar_offset; /* offset for alt status register */ 1920 ushort_t addr; /* compatibility mode base address */ 1921 ushort_t length; /* number of ports for this BAR */ 1922 } pciide_bar[] = { 1923 { 0x01, 0, 0x1f0, 8 }, /* primary lower BAR */ 1924 { 0x01, 2, 0x3f6, 1 }, /* primary upper BAR */ 1925 { 0x04, 0, 0x170, 8 }, /* secondary lower BAR */ 1926 { 0x04, 2, 0x376, 1 } /* secondary upper BAR */ 1927 }; 1928 1929 static int 1930 pciIdeAdjustBAR(uchar_t progcl, int index, uint_t *basep, uint_t *lenp) 1931 { 1932 int hard_decode = 0; 1933 1934 /* 1935 * Adjust the base and len for the BARs of the PCI-IDE 1936 * device's primary and secondary controllers. The first 1937 * two BARs are for the primary controller and the next 1938 * two BARs are for the secondary controller. The fifth 1939 * and sixth bars are never adjusted. 1940 */ 1941 if (index >= 0 && index <= 3) { 1942 *lenp = pciide_bar[index].length; 1943 1944 if (progcl & pciide_bar[index].native_mask) { 1945 *basep += pciide_bar[index].bar_offset; 1946 } else { 1947 *basep = pciide_bar[index].addr; 1948 hard_decode = 1; 1949 } 1950 } 1951 1952 /* 1953 * if either base or len is zero make certain both are zero 1954 */ 1955 if (*basep == 0 || *lenp == 0) { 1956 *basep = 0; 1957 *lenp = 0; 1958 hard_decode = 0; 1959 } 1960 1961 return (hard_decode); 1962 } 1963 1964 1965 /* 1966 * Add the "reg" and "assigned-addresses" property 1967 */ 1968 static int 1969 add_reg_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 1970 int config_op, int pciide) 1971 { 1972 uchar_t baseclass, subclass, progclass, header; 1973 ushort_t bar_sz; 1974 uint_t value = 0, len, devloc; 1975 uint_t base, base_hi, type; 1976 ushort_t offset, end; 1977 int max_basereg, j, reprogram = 0; 1978 uint_t phys_hi; 1979 struct memlist **io_avail, **io_used; 1980 struct memlist **mem_avail, **mem_used; 1981 struct memlist **pmem_avail, **pmem_used; 1982 uchar_t res_bus; 1983 1984 pci_regspec_t regs[16] = {{0}}; 1985 pci_regspec_t assigned[15] = {{0}}; 1986 int nreg, nasgn; 1987 1988 io_avail = &pci_bus_res[bus].io_avail; 1989 io_used = &pci_bus_res[bus].io_used; 1990 mem_avail = &pci_bus_res[bus].mem_avail; 1991 mem_used = &pci_bus_res[bus].mem_used; 1992 pmem_avail = &pci_bus_res[bus].pmem_avail; 1993 pmem_used = &pci_bus_res[bus].pmem_used; 1994 1995 devloc = (uint_t)bus << 16 | (uint_t)dev << 11 | (uint_t)func << 8; 1996 regs[0].pci_phys_hi = devloc; 1997 nreg = 1; /* rest of regs[0] is all zero */ 1998 nasgn = 0; 1999 2000 baseclass = pci_getb(bus, dev, func, PCI_CONF_BASCLASS); 2001 subclass = pci_getb(bus, dev, func, PCI_CONF_SUBCLASS); 2002 progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 2003 header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 2004 2005 switch (header) { 2006 case PCI_HEADER_ZERO: 2007 max_basereg = PCI_BASE_NUM; 2008 break; 2009 case PCI_HEADER_PPB: 2010 max_basereg = PCI_BCNF_BASE_NUM; 2011 break; 2012 case PCI_HEADER_CARDBUS: 2013 max_basereg = PCI_CBUS_BASE_NUM; 2014 reprogram = 1; 2015 break; 2016 default: 2017 max_basereg = 0; 2018 break; 2019 } 2020 2021 /* 2022 * Create the register property by saving the current 2023 * value of the base register. Write 0xffffffff to the 2024 * base register. Read the value back to determine the 2025 * required size of the address space. Restore the base 2026 * register contents. 2027 * 2028 * Do not disable I/O and memory access; this isn't necessary 2029 * since no driver is yet attached to this device, and disabling 2030 * I/O and memory access has the side-effect of disabling PCI-PCI 2031 * bridge mappings, which makes the bridge transparent to secondary- 2032 * bus activity (see sections 4.1-4.3 of the PCI-PCI Bridge 2033 * Spec V1.2). 2034 */ 2035 end = PCI_CONF_BASE0 + max_basereg * sizeof (uint_t); 2036 for (j = 0, offset = PCI_CONF_BASE0; offset < end; 2037 j++, offset += bar_sz) { 2038 /* determine the size of the address space */ 2039 base = pci_getl(bus, dev, func, offset); 2040 pci_putl(bus, dev, func, offset, 0xffffffff); 2041 value = pci_getl(bus, dev, func, offset); 2042 pci_putl(bus, dev, func, offset, base); 2043 2044 /* construct phys hi,med.lo, size hi, lo */ 2045 if ((pciide && j < 4) || (base & PCI_BASE_SPACE_IO)) { 2046 int hard_decode = 0; 2047 2048 /* i/o space */ 2049 bar_sz = PCI_BAR_SZ_32; 2050 value &= PCI_BASE_IO_ADDR_M; 2051 len = ((value ^ (value-1)) + 1) >> 1; 2052 2053 /* XXX Adjust first 4 IDE registers */ 2054 if (pciide) { 2055 if (subclass != PCI_MASS_IDE) 2056 progclass = (PCI_IDE_IF_NATIVE_PRI | 2057 PCI_IDE_IF_NATIVE_SEC); 2058 hard_decode = pciIdeAdjustBAR(progclass, j, 2059 &base, &len); 2060 } else if (value == 0) { 2061 /* skip base regs with size of 0 */ 2062 continue; 2063 } 2064 2065 regs[nreg].pci_phys_hi = PCI_ADDR_IO | devloc | 2066 (hard_decode ? PCI_RELOCAT_B : offset); 2067 regs[nreg].pci_phys_low = hard_decode ? 2068 base & PCI_BASE_IO_ADDR_M : 0; 2069 assigned[nasgn].pci_phys_hi = 2070 PCI_RELOCAT_B | regs[nreg].pci_phys_hi; 2071 regs[nreg].pci_size_low = 2072 assigned[nasgn].pci_size_low = len; 2073 type = base & (~PCI_BASE_IO_ADDR_M); 2074 base &= PCI_BASE_IO_ADDR_M; 2075 /* 2076 * A device under a subtractive PPB can allocate 2077 * resources from its parent bus if there is no resource 2078 * available on its own bus. 2079 */ 2080 if ((config_op == CONFIG_NEW) && (*io_avail == NULL)) { 2081 res_bus = bus; 2082 while (pci_bus_res[res_bus].subtractive) { 2083 res_bus = pci_bus_res[res_bus].par_bus; 2084 if (res_bus == (uchar_t)-1) 2085 break; /* root bus already */ 2086 if (pci_bus_res[res_bus].io_avail) { 2087 io_avail = &pci_bus_res 2088 [res_bus].io_avail; 2089 break; 2090 } 2091 } 2092 } 2093 2094 /* 2095 * first pass - gather what's there 2096 * update/second pass - adjust/allocate regions 2097 * config - allocate regions 2098 */ 2099 if (config_op == CONFIG_INFO) { /* first pass */ 2100 /* take out of the resource map of the bus */ 2101 if (base != 0) { 2102 (void) memlist_remove(io_avail, base, 2103 len); 2104 memlist_insert(io_used, base, len); 2105 } else { 2106 reprogram = 1; 2107 } 2108 pci_bus_res[bus].io_size += len; 2109 } else if ((*io_avail && base == 0) || 2110 pci_bus_res[bus].io_reprogram) { 2111 base = (uint_t)memlist_find(io_avail, len, len); 2112 if (base != 0) { 2113 memlist_insert(io_used, base, len); 2114 /* XXX need to worry about 64-bit? */ 2115 pci_putl(bus, dev, func, offset, 2116 base | type); 2117 base = pci_getl(bus, dev, func, offset); 2118 base &= PCI_BASE_IO_ADDR_M; 2119 } 2120 if (base == 0) { 2121 cmn_err(CE_WARN, "failed to program" 2122 " IO space [%d/%d/%d] BAR@0x%x" 2123 " length 0x%x", 2124 bus, dev, func, offset, len); 2125 } 2126 } 2127 assigned[nasgn].pci_phys_low = base; 2128 nreg++, nasgn++; 2129 2130 } else { 2131 /* memory space */ 2132 if ((base & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) { 2133 bar_sz = PCI_BAR_SZ_64; 2134 base_hi = pci_getl(bus, dev, func, offset + 4); 2135 phys_hi = PCI_ADDR_MEM64; 2136 } else { 2137 bar_sz = PCI_BAR_SZ_32; 2138 base_hi = 0; 2139 phys_hi = PCI_ADDR_MEM32; 2140 } 2141 2142 /* skip base regs with size of 0 */ 2143 value &= PCI_BASE_M_ADDR_M; 2144 2145 if (value == 0) 2146 continue; 2147 2148 len = ((value ^ (value-1)) + 1) >> 1; 2149 regs[nreg].pci_size_low = 2150 assigned[nasgn].pci_size_low = len; 2151 2152 phys_hi |= (devloc | offset); 2153 if (base & PCI_BASE_PREF_M) 2154 phys_hi |= PCI_PREFETCH_B; 2155 2156 /* 2157 * A device under a subtractive PPB can allocate 2158 * resources from its parent bus if there is no resource 2159 * available on its own bus. 2160 */ 2161 if ((config_op == CONFIG_NEW) && (*mem_avail == NULL)) { 2162 res_bus = bus; 2163 while (pci_bus_res[res_bus].subtractive) { 2164 res_bus = pci_bus_res[res_bus].par_bus; 2165 if (res_bus == (uchar_t)-1) 2166 break; /* root bus already */ 2167 mem_avail = 2168 &pci_bus_res[res_bus].mem_avail; 2169 pmem_avail = 2170 &pci_bus_res [res_bus].pmem_avail; 2171 /* 2172 * Break out as long as at least 2173 * mem_avail is available 2174 */ 2175 if ((*pmem_avail && 2176 (phys_hi & PCI_PREFETCH_B)) || 2177 *mem_avail) 2178 break; 2179 } 2180 } 2181 2182 regs[nreg].pci_phys_hi = 2183 assigned[nasgn].pci_phys_hi = phys_hi; 2184 assigned[nasgn].pci_phys_hi |= PCI_RELOCAT_B; 2185 assigned[nasgn].pci_phys_mid = base_hi; 2186 type = base & ~PCI_BASE_M_ADDR_M; 2187 base &= PCI_BASE_M_ADDR_M; 2188 2189 if (config_op == CONFIG_INFO) { 2190 /* take out of the resource map of the bus */ 2191 if (base != NULL) { 2192 /* remove from PMEM and MEM space */ 2193 (void) memlist_remove(mem_avail, 2194 base, len); 2195 (void) memlist_remove(pmem_avail, 2196 base, len); 2197 /* only note as used in correct map */ 2198 if (phys_hi & PCI_PREFETCH_B) 2199 memlist_insert(pmem_used, 2200 base, len); 2201 else 2202 memlist_insert(mem_used, 2203 base, len); 2204 } else { 2205 reprogram = 1; 2206 } 2207 pci_bus_res[bus].mem_size += len; 2208 } else if ((*mem_avail && base == NULL) || 2209 pci_bus_res[bus].mem_reprogram) { 2210 /* 2211 * When desired, attempt a prefetchable 2212 * allocation first 2213 */ 2214 if (phys_hi & PCI_PREFETCH_B) { 2215 base = (uint_t)memlist_find(pmem_avail, 2216 len, len); 2217 if (base != NULL) { 2218 memlist_insert(pmem_used, 2219 base, len); 2220 (void) memlist_remove(mem_avail, 2221 base, len); 2222 } 2223 } 2224 /* 2225 * If prefetchable allocation was not 2226 * desired, or failed, attempt ordinary 2227 * memory allocation 2228 */ 2229 if (base == NULL) { 2230 base = (uint_t)memlist_find(mem_avail, 2231 len, len); 2232 if (base != NULL) { 2233 memlist_insert(mem_used, 2234 base, len); 2235 (void) memlist_remove( 2236 pmem_avail, base, len); 2237 } 2238 } 2239 if (base != NULL) { 2240 pci_putl(bus, dev, func, offset, 2241 base | type); 2242 base = pci_getl(bus, dev, func, offset); 2243 base &= PCI_BASE_M_ADDR_M; 2244 } else 2245 cmn_err(CE_WARN, "failed to program " 2246 "mem space [%d/%d/%d] BAR@0x%x" 2247 " length 0x%x", 2248 bus, dev, func, offset, len); 2249 } 2250 assigned[nasgn].pci_phys_low = base; 2251 nreg++, nasgn++; 2252 } 2253 } 2254 switch (header) { 2255 case PCI_HEADER_ZERO: 2256 offset = PCI_CONF_ROM; 2257 break; 2258 case PCI_HEADER_PPB: 2259 offset = PCI_BCNF_ROM; 2260 break; 2261 default: /* including PCI_HEADER_CARDBUS */ 2262 goto done; 2263 } 2264 2265 /* 2266 * Add the expansion rom memory space 2267 * Determine the size of the ROM base reg; don't write reserved bits 2268 * ROM isn't in the PCI memory space. 2269 */ 2270 base = pci_getl(bus, dev, func, offset); 2271 pci_putl(bus, dev, func, offset, PCI_BASE_ROM_ADDR_M); 2272 value = pci_getl(bus, dev, func, offset); 2273 pci_putl(bus, dev, func, offset, base); 2274 if (value & PCI_BASE_ROM_ENABLE) 2275 value &= PCI_BASE_ROM_ADDR_M; 2276 else 2277 value = 0; 2278 2279 if (value != 0) { 2280 regs[nreg].pci_phys_hi = (PCI_ADDR_MEM32 | devloc) + offset; 2281 assigned[nasgn].pci_phys_hi = (PCI_RELOCAT_B | 2282 PCI_ADDR_MEM32 | devloc) + offset; 2283 base &= PCI_BASE_ROM_ADDR_M; 2284 assigned[nasgn].pci_phys_low = base; 2285 len = ((value ^ (value-1)) + 1) >> 1; 2286 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = len; 2287 nreg++, nasgn++; 2288 /* take it out of the memory resource */ 2289 if (base != NULL) { 2290 (void) memlist_remove(mem_avail, base, len); 2291 memlist_insert(mem_used, base, len); 2292 pci_bus_res[bus].mem_size += len; 2293 } 2294 } 2295 2296 /* 2297 * Account for "legacy" (alias) video adapter resources 2298 */ 2299 2300 /* add the three hard-decode, aliased address spaces for VGA */ 2301 if ((baseclass == PCI_CLASS_DISPLAY && subclass == PCI_DISPLAY_VGA) || 2302 (baseclass == PCI_CLASS_NONE && subclass == PCI_NONE_VGA)) { 2303 2304 /* VGA hard decode 0x3b0-0x3bb */ 2305 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2306 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 2307 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3b0; 2308 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0xc; 2309 nreg++, nasgn++; 2310 (void) memlist_remove(io_avail, 0x3b0, 0xc); 2311 memlist_insert(io_used, 0x3b0, 0xc); 2312 pci_bus_res[bus].io_size += 0xc; 2313 2314 /* VGA hard decode 0x3c0-0x3df */ 2315 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2316 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 2317 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3c0; 2318 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x20; 2319 nreg++, nasgn++; 2320 (void) memlist_remove(io_avail, 0x3c0, 0x20); 2321 memlist_insert(io_used, 0x3c0, 0x20); 2322 pci_bus_res[bus].io_size += 0x20; 2323 2324 /* Video memory */ 2325 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2326 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_MEM32 | devloc); 2327 regs[nreg].pci_phys_low = 2328 assigned[nasgn].pci_phys_low = 0xa0000; 2329 regs[nreg].pci_size_low = 2330 assigned[nasgn].pci_size_low = 0x20000; 2331 nreg++, nasgn++; 2332 /* remove from MEM and PMEM space */ 2333 (void) memlist_remove(mem_avail, 0xa0000, 0x20000); 2334 (void) memlist_remove(pmem_avail, 0xa0000, 0x20000); 2335 memlist_insert(mem_used, 0xa0000, 0x20000); 2336 pci_bus_res[bus].mem_size += 0x20000; 2337 } 2338 2339 /* add the hard-decode, aliased address spaces for 8514 */ 2340 if ((baseclass == PCI_CLASS_DISPLAY) && 2341 (subclass == PCI_DISPLAY_VGA) && 2342 (progclass & PCI_DISPLAY_IF_8514)) { 2343 2344 /* hard decode 0x2e8 */ 2345 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2346 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 2347 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2e8; 2348 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x1; 2349 nreg++, nasgn++; 2350 (void) memlist_remove(io_avail, 0x2e8, 0x1); 2351 memlist_insert(io_used, 0x2e8, 0x1); 2352 pci_bus_res[bus].io_size += 0x1; 2353 2354 /* hard decode 0x2ea-0x2ef */ 2355 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2356 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 2357 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2ea; 2358 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x6; 2359 nreg++, nasgn++; 2360 (void) memlist_remove(io_avail, 0x2ea, 0x6); 2361 memlist_insert(io_used, 0x2ea, 0x6); 2362 pci_bus_res[bus].io_size += 0x6; 2363 } 2364 2365 done: 2366 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg", 2367 (int *)regs, nreg * sizeof (pci_regspec_t) / sizeof (int)); 2368 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 2369 "assigned-addresses", 2370 (int *)assigned, nasgn * sizeof (pci_regspec_t) / sizeof (int)); 2371 2372 return (reprogram); 2373 } 2374 2375 static void 2376 add_ppb_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 2377 int pciex, ushort_t is_pci_bridge) 2378 { 2379 char *dev_type; 2380 int i; 2381 uint_t val, io_range[2], mem_range[2], pmem_range[2]; 2382 uchar_t secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS); 2383 uchar_t subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 2384 uchar_t progclass; 2385 2386 ASSERT(secbus <= subbus); 2387 2388 /* 2389 * Check if it's a subtractive PPB. 2390 */ 2391 progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 2392 if (progclass == PCI_BRIDGE_PCI_IF_SUBDECODE) 2393 pci_bus_res[secbus].subtractive = B_TRUE; 2394 2395 /* 2396 * Some BIOSes lie about max pci busses, we allow for 2397 * such mistakes here 2398 */ 2399 if (subbus > pci_bios_nbus) { 2400 pci_bios_nbus = subbus; 2401 alloc_res_array(); 2402 } 2403 2404 ASSERT(pci_bus_res[secbus].dip == NULL); 2405 pci_bus_res[secbus].dip = dip; 2406 pci_bus_res[secbus].par_bus = bus; 2407 2408 dev_type = (pciex && !is_pci_bridge) ? "pciex" : "pci"; 2409 2410 /* setup bus number hierarchy */ 2411 pci_bus_res[secbus].sub_bus = subbus; 2412 /* 2413 * Keep track of the largest subordinate bus number (this is essential 2414 * for peer busses because there is no other way of determining its 2415 * subordinate bus number). 2416 */ 2417 if (subbus > pci_bus_res[bus].sub_bus) 2418 pci_bus_res[bus].sub_bus = subbus; 2419 /* 2420 * Loop through subordinate busses, initializing their parent bus 2421 * field to this bridge's parent. The subordinate busses' parent 2422 * fields may very well be further refined later, as child bridges 2423 * are enumerated. (The value is to note that the subordinate busses 2424 * are not peer busses by changing their par_bus fields to anything 2425 * other than -1.) 2426 */ 2427 for (i = secbus + 1; i <= subbus; i++) 2428 pci_bus_res[i].par_bus = bus; 2429 2430 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 2431 "device_type", dev_type); 2432 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2433 "#address-cells", 3); 2434 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2435 "#size-cells", 2); 2436 2437 /* 2438 * Collect bridge window specifications, and use them to populate 2439 * the "avail" resources for the bus. Not all of those resources will 2440 * end up being available; this is done top-down, and so the initial 2441 * collection of windows populates the 'ranges' property for the 2442 * bus node. Later, as children are found, resources are removed from 2443 * the 'avail' list, so that it becomes the freelist for 2444 * this point in the tree. ranges may be set again after bridge 2445 * reprogramming in fix_ppb_res(), in which case it's set from 2446 * used + avail. 2447 * 2448 * According to PPB spec, the base register should be programmed 2449 * with a value bigger than the limit register when there are 2450 * no resources available. This applies to io, memory, and 2451 * prefetchable memory. 2452 */ 2453 2454 /* 2455 * io range 2456 * We determine i/o windows that are left unconfigured by BIOS 2457 * through its i/o enable bit as Microsoft recommends OEMs to do. 2458 * If it is unset, we disable i/o and mark it for reconfiguration in 2459 * later passes by setting the base > limit 2460 */ 2461 val = (uint_t)pci_getw(bus, dev, func, PCI_CONF_COMM); 2462 if (val & PCI_COMM_IO) { 2463 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 2464 io_range[0] = ((val & 0xf0) << 8); 2465 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 2466 io_range[1] = ((val & 0xf0) << 8) | 0xFFF; 2467 } else { 2468 io_range[0] = 0x9fff; 2469 io_range[1] = 0x1000; 2470 pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW, 2471 (uint8_t)((io_range[0] >> 8) & 0xf0)); 2472 pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW, 2473 (uint8_t)((io_range[1] >> 8) & 0xf0)); 2474 pci_putw(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0); 2475 pci_putw(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0); 2476 } 2477 2478 if (io_range[0] != 0 && io_range[0] < io_range[1]) { 2479 memlist_insert(&pci_bus_res[secbus].io_avail, 2480 (uint64_t)io_range[0], 2481 (uint64_t)(io_range[1] - io_range[0] + 1)); 2482 memlist_insert(&pci_bus_res[bus].io_used, 2483 (uint64_t)io_range[0], 2484 (uint64_t)(io_range[1] - io_range[0] + 1)); 2485 if (pci_bus_res[bus].io_avail != NULL) { 2486 (void) memlist_remove(&pci_bus_res[bus].io_avail, 2487 (uint64_t)io_range[0], 2488 (uint64_t)(io_range[1] - io_range[0] + 1)); 2489 } 2490 dcmn_err(CE_NOTE, "bus %d io-range: 0x%x-%x", 2491 secbus, io_range[0], io_range[1]); 2492 /* if 32-bit supported, make sure upper bits are not set */ 2493 if ((val & 0xf) == 1 && 2494 pci_getw(bus, dev, func, PCI_BCNF_IO_BASE_HI)) { 2495 cmn_err(CE_NOTE, "unsupported 32-bit IO address on" 2496 " pci-pci bridge [%d/%d/%d]", bus, dev, func); 2497 } 2498 } 2499 2500 /* mem range */ 2501 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); 2502 mem_range[0] = ((val & 0xFFF0) << 16); 2503 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); 2504 mem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 2505 if (mem_range[0] != 0 && mem_range[0] < mem_range[1]) { 2506 memlist_insert(&pci_bus_res[secbus].mem_avail, 2507 (uint64_t)mem_range[0], 2508 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 2509 memlist_insert(&pci_bus_res[bus].mem_used, 2510 (uint64_t)mem_range[0], 2511 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 2512 /* remove from parent resource list */ 2513 (void) memlist_remove(&pci_bus_res[bus].mem_avail, 2514 (uint64_t)mem_range[0], 2515 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 2516 (void) memlist_remove(&pci_bus_res[bus].pmem_avail, 2517 (uint64_t)mem_range[0], 2518 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 2519 dcmn_err(CE_NOTE, "bus %d mem-range: 0x%x-%x", 2520 secbus, mem_range[0], mem_range[1]); 2521 } 2522 2523 /* prefetchable memory range */ 2524 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_BASE_LOW); 2525 pmem_range[0] = ((val & 0xFFF0) << 16); 2526 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW); 2527 pmem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 2528 if (pmem_range[0] != 0 && pmem_range[0] < pmem_range[1]) { 2529 memlist_insert(&pci_bus_res[secbus].pmem_avail, 2530 (uint64_t)pmem_range[0], 2531 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 2532 memlist_insert(&pci_bus_res[bus].pmem_used, 2533 (uint64_t)pmem_range[0], 2534 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 2535 /* remove from parent resource list */ 2536 (void) memlist_remove(&pci_bus_res[bus].pmem_avail, 2537 (uint64_t)pmem_range[0], 2538 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 2539 (void) memlist_remove(&pci_bus_res[bus].mem_avail, 2540 (uint64_t)pmem_range[0], 2541 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 2542 dcmn_err(CE_NOTE, "bus %d pmem-range: 0x%x-%x", 2543 secbus, pmem_range[0], pmem_range[1]); 2544 /* if 64-bit supported, make sure upper bits are not set */ 2545 if ((val & 0xf) == 1 && 2546 pci_getl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH)) { 2547 cmn_err(CE_NOTE, "unsupported 64-bit prefetch memory on" 2548 " pci-pci bridge [%d/%d/%d]", bus, dev, func); 2549 } 2550 } 2551 2552 /* 2553 * Add VGA legacy resources to the bridge's pci_bus_res if it 2554 * has VGA_ENABLE set. Note that we put them in 'avail', 2555 * because that's used to populate the ranges prop; they'll be 2556 * removed from there by the VGA device once it's found. Also, 2557 * remove them from the parent's available list and note them as 2558 * used in the parent. 2559 */ 2560 2561 if (pci_getw(bus, dev, func, PCI_BCNF_BCNTRL) & 2562 PCI_BCNF_BCNTRL_VGA_ENABLE) { 2563 2564 memlist_insert(&pci_bus_res[secbus].io_avail, 0x3b0, 0xc); 2565 2566 memlist_insert(&pci_bus_res[bus].io_used, 0x3b0, 0xc); 2567 if (pci_bus_res[bus].io_avail != NULL) { 2568 (void) memlist_remove(&pci_bus_res[bus].io_avail, 2569 0x3b0, 0xc); 2570 } 2571 2572 memlist_insert(&pci_bus_res[secbus].io_avail, 0x3c0, 0x20); 2573 2574 memlist_insert(&pci_bus_res[bus].io_used, 0x3c0, 0x20); 2575 if (pci_bus_res[bus].io_avail != NULL) { 2576 (void) memlist_remove(&pci_bus_res[bus].io_avail, 2577 0x3c0, 0x20); 2578 } 2579 2580 memlist_insert(&pci_bus_res[secbus].mem_avail, 0xa0000, 2581 0x20000); 2582 2583 memlist_insert(&pci_bus_res[bus].mem_used, 0xa0000, 0x20000); 2584 if (pci_bus_res[bus].mem_avail != NULL) { 2585 (void) memlist_remove(&pci_bus_res[bus].mem_avail, 2586 0xa0000, 0x20000); 2587 } 2588 } 2589 add_bus_range_prop(secbus); 2590 add_ranges_prop(secbus, 1); 2591 } 2592 2593 extern const struct pci_class_strings_s class_pci[]; 2594 extern int class_pci_items; 2595 2596 static void 2597 add_model_prop(dev_info_t *dip, uint_t classcode) 2598 { 2599 const char *desc; 2600 int i; 2601 uchar_t baseclass = classcode >> 16; 2602 uchar_t subclass = (classcode >> 8) & 0xff; 2603 uchar_t progclass = classcode & 0xff; 2604 2605 if ((baseclass == PCI_CLASS_MASS) && (subclass == PCI_MASS_IDE)) { 2606 desc = "IDE controller"; 2607 } else { 2608 for (desc = 0, i = 0; i < class_pci_items; i++) { 2609 if ((baseclass == class_pci[i].base_class) && 2610 (subclass == class_pci[i].sub_class) && 2611 (progclass == class_pci[i].prog_class)) { 2612 desc = class_pci[i].actual_desc; 2613 break; 2614 } 2615 } 2616 if (i == class_pci_items) 2617 desc = "Unknown class of pci/pnpbios device"; 2618 } 2619 2620 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 2621 (char *)desc); 2622 } 2623 2624 static void 2625 add_bus_range_prop(int bus) 2626 { 2627 int bus_range[2]; 2628 2629 if (pci_bus_res[bus].dip == NULL) 2630 return; 2631 bus_range[0] = bus; 2632 bus_range[1] = pci_bus_res[bus].sub_bus; 2633 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 2634 "bus-range", (int *)bus_range, 2); 2635 } 2636 2637 /* 2638 * Add slot-names property for any named pci hot-plug slots 2639 */ 2640 static void 2641 add_bus_slot_names_prop(int bus) 2642 { 2643 char slotprop[256]; 2644 int len; 2645 2646 if (pci_bus_res[bus].dip != NULL) { 2647 /* simply return if the property is already defined */ 2648 if (ddi_prop_exists(DDI_DEV_T_ANY, pci_bus_res[bus].dip, 2649 DDI_PROP_DONTPASS, "slot-names")) 2650 return; 2651 } 2652 2653 len = pci_slot_names_prop(bus, slotprop, sizeof (slotprop)); 2654 if (len > 0) { 2655 /* 2656 * Only create a peer bus node if this bus may be a peer bus. 2657 * It may be a peer bus if the dip is NULL and if par_bus is 2658 * -1 (par_bus is -1 if this bus was not found to be 2659 * subordinate to any PCI-PCI bridge). 2660 * If it's not a peer bus, then the ACPI BBN-handling code 2661 * will remove it later. 2662 */ 2663 if (pci_bus_res[bus].par_bus == (uchar_t)-1 && 2664 pci_bus_res[bus].dip == NULL) { 2665 2666 create_root_bus_dip(bus); 2667 } 2668 if (pci_bus_res[bus].dip != NULL) { 2669 ASSERT((len % sizeof (int)) == 0); 2670 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 2671 pci_bus_res[bus].dip, "slot-names", 2672 (int *)slotprop, len / sizeof (int)); 2673 } else { 2674 cmn_err(CE_NOTE, "!BIOS BUG: Invalid bus number in PCI " 2675 "IRQ routing table; Not adding slot-names " 2676 "property for incorrect bus %d", bus); 2677 } 2678 } 2679 } 2680 2681 /* 2682 * Handle both PCI root and PCI-PCI bridge range properties; 2683 * non-zero 'ppb' argument select PCI-PCI bridges versus root. 2684 */ 2685 static void 2686 memlist_to_ranges(void **rp, struct memlist *entry, int type, int ppb) 2687 { 2688 ppb_ranges_t *ppb_rp = *rp; 2689 pci_ranges_t *pci_rp = *rp; 2690 2691 while (entry != NULL) { 2692 if (ppb) { 2693 ppb_rp->child_high = ppb_rp->parent_high = type; 2694 ppb_rp->child_mid = ppb_rp->parent_mid = 2695 (uint32_t)(entry->address >> 32); /* XXX */ 2696 ppb_rp->child_low = ppb_rp->parent_low = 2697 (uint32_t)entry->address; 2698 ppb_rp->size_high = 2699 (uint32_t)(entry->size >> 32); /* XXX */ 2700 ppb_rp->size_low = (uint32_t)entry->size; 2701 *rp = ++ppb_rp; 2702 } else { 2703 pci_rp->child_high = type; 2704 pci_rp->child_mid = pci_rp->parent_high = 2705 (uint32_t)(entry->address >> 32); /* XXX */ 2706 pci_rp->child_low = pci_rp->parent_low = 2707 (uint32_t)entry->address; 2708 pci_rp->size_high = 2709 (uint32_t)(entry->size >> 32); /* XXX */ 2710 pci_rp->size_low = (uint32_t)entry->size; 2711 *rp = ++pci_rp; 2712 } 2713 entry = entry->next; 2714 } 2715 } 2716 2717 static void 2718 add_ranges_prop(int bus, int ppb) 2719 { 2720 int total, alloc_size; 2721 void *rp, *next_rp; 2722 struct memlist *iolist, *memlist, *pmemlist; 2723 2724 /* no devinfo node - unused bus, return */ 2725 if (pci_bus_res[bus].dip == NULL) 2726 return; 2727 2728 iolist = memlist = pmemlist = (struct memlist *)NULL; 2729 2730 memlist_merge(&pci_bus_res[bus].io_avail, &iolist); 2731 memlist_merge(&pci_bus_res[bus].io_used, &iolist); 2732 memlist_merge(&pci_bus_res[bus].mem_avail, &memlist); 2733 memlist_merge(&pci_bus_res[bus].mem_used, &memlist); 2734 memlist_merge(&pci_bus_res[bus].pmem_avail, &pmemlist); 2735 memlist_merge(&pci_bus_res[bus].pmem_used, &pmemlist); 2736 2737 total = memlist_count(iolist); 2738 total += memlist_count(memlist); 2739 total += memlist_count(pmemlist); 2740 2741 /* no property is created if no ranges are present */ 2742 if (total == 0) 2743 return; 2744 2745 alloc_size = total * 2746 (ppb ? sizeof (ppb_ranges_t) : sizeof (pci_ranges_t)); 2747 2748 next_rp = rp = kmem_alloc(alloc_size, KM_SLEEP); 2749 2750 memlist_to_ranges(&next_rp, iolist, PCI_ADDR_IO | PCI_REG_REL_M, ppb); 2751 memlist_to_ranges(&next_rp, memlist, 2752 PCI_ADDR_MEM32 | PCI_REG_REL_M, ppb); 2753 memlist_to_ranges(&next_rp, pmemlist, 2754 PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M, ppb); 2755 2756 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 2757 "ranges", (int *)rp, alloc_size / sizeof (int)); 2758 2759 kmem_free(rp, alloc_size); 2760 memlist_free_all(&iolist); 2761 memlist_free_all(&memlist); 2762 memlist_free_all(&pmemlist); 2763 } 2764 2765 static void 2766 memlist_remove_list(struct memlist **list, struct memlist *remove_list) 2767 { 2768 while (list && *list && remove_list) { 2769 (void) memlist_remove(list, remove_list->address, 2770 remove_list->size); 2771 remove_list = remove_list->next; 2772 } 2773 } 2774 2775 static int 2776 memlist_to_spec(struct pci_phys_spec *sp, struct memlist *list, int type) 2777 { 2778 int i = 0; 2779 2780 while (list) { 2781 /* assume 32-bit addresses */ 2782 sp->pci_phys_hi = type; 2783 sp->pci_phys_mid = 0; 2784 sp->pci_phys_low = (uint32_t)list->address; 2785 sp->pci_size_hi = 0; 2786 sp->pci_size_low = (uint32_t)list->size; 2787 2788 list = list->next; 2789 sp++, i++; 2790 } 2791 return (i); 2792 } 2793 2794 static void 2795 add_bus_available_prop(int bus) 2796 { 2797 int i, count; 2798 struct pci_phys_spec *sp; 2799 2800 /* no devinfo node - unused bus, return */ 2801 if (pci_bus_res[bus].dip == NULL) 2802 return; 2803 2804 count = memlist_count(pci_bus_res[bus].io_avail) + 2805 memlist_count(pci_bus_res[bus].mem_avail) + 2806 memlist_count(pci_bus_res[bus].pmem_avail); 2807 2808 if (count == 0) /* nothing available */ 2809 return; 2810 2811 sp = kmem_alloc(count * sizeof (*sp), KM_SLEEP); 2812 i = memlist_to_spec(&sp[0], pci_bus_res[bus].io_avail, 2813 PCI_ADDR_IO | PCI_REG_REL_M); 2814 i += memlist_to_spec(&sp[i], pci_bus_res[bus].mem_avail, 2815 PCI_ADDR_MEM32 | PCI_REG_REL_M); 2816 i += memlist_to_spec(&sp[i], pci_bus_res[bus].pmem_avail, 2817 PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); 2818 ASSERT(i == count); 2819 2820 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 2821 "available", (int *)sp, 2822 i * sizeof (struct pci_phys_spec) / sizeof (int)); 2823 kmem_free(sp, count * sizeof (*sp)); 2824 } 2825 2826 static void 2827 alloc_res_array(void) 2828 { 2829 static int array_max = 0; 2830 int old_max; 2831 void *old_res; 2832 2833 if (array_max > pci_bios_nbus + 1) 2834 return; /* array is big enough */ 2835 2836 old_max = array_max; 2837 old_res = pci_bus_res; 2838 2839 if (array_max == 0) 2840 array_max = 16; /* start with a reasonable number */ 2841 2842 while (array_max < pci_bios_nbus + 1) 2843 array_max <<= 1; 2844 pci_bus_res = (struct pci_bus_resource *)kmem_zalloc( 2845 array_max * sizeof (struct pci_bus_resource), KM_SLEEP); 2846 2847 if (old_res) { /* copy content and free old array */ 2848 bcopy(old_res, pci_bus_res, 2849 old_max * sizeof (struct pci_bus_resource)); 2850 kmem_free(old_res, old_max * sizeof (struct pci_bus_resource)); 2851 } 2852 } 2853 2854 static void 2855 create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 2856 ushort_t deviceid) 2857 { 2858 static dev_info_t *ioapicsnode = NULL; 2859 static int numioapics = 0; 2860 dev_info_t *ioapic_node; 2861 uint64_t physaddr; 2862 uint32_t lobase, hibase = 0; 2863 2864 /* BAR 0 contains the IOAPIC's memory-mapped I/O address */ 2865 lobase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0); 2866 2867 /* We (and the rest of the world) only support memory-mapped IOAPICs */ 2868 if ((lobase & PCI_BASE_SPACE_M) != PCI_BASE_SPACE_MEM) 2869 return; 2870 2871 if ((lobase & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) 2872 hibase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0 + 4); 2873 2874 lobase &= PCI_BASE_M_ADDR_M; 2875 2876 physaddr = (((uint64_t)hibase) << 32) | lobase; 2877 2878 /* 2879 * Create a nexus node for all IOAPICs under the root node. 2880 */ 2881 if (ioapicsnode == NULL) { 2882 if (ndi_devi_alloc(ddi_root_node(), IOAPICS_NODE_NAME, 2883 (pnode_t)DEVI_SID_NODEID, &ioapicsnode) != NDI_SUCCESS) { 2884 return; 2885 } 2886 (void) ndi_devi_online(ioapicsnode, 0); 2887 } 2888 2889 /* 2890 * Create a child node for this IOAPIC 2891 */ 2892 ioapic_node = ddi_add_child(ioapicsnode, IOAPICS_CHILD_NAME, 2893 DEVI_SID_NODEID, numioapics++); 2894 if (ioapic_node == NULL) { 2895 return; 2896 } 2897 2898 /* Vendor and Device ID */ 2899 (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 2900 IOAPICS_PROP_VENID, vendorid); 2901 (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 2902 IOAPICS_PROP_DEVID, deviceid); 2903 2904 /* device_type */ 2905 (void) ndi_prop_update_string(DDI_DEV_T_NONE, ioapic_node, 2906 "device_type", IOAPICS_DEV_TYPE); 2907 2908 /* reg */ 2909 (void) ndi_prop_update_int64(DDI_DEV_T_NONE, ioapic_node, 2910 "reg", physaddr); 2911 } 2912 2913 /* 2914 * NOTE: For PCIe slots, the name is generated from the slot number 2915 * information obtained from Slot Capabilities register. 2916 * For non-PCIe slots, it is generated based on the slot number 2917 * information in the PCI IRQ table. 2918 */ 2919 static void 2920 pciex_slot_names_prop(dev_info_t *dip, ushort_t slot_num) 2921 { 2922 char slotprop[256]; 2923 int len; 2924 2925 bzero(slotprop, sizeof (slotprop)); 2926 2927 /* set mask to 1 as there is only one slot (i.e dev 0) */ 2928 *(uint32_t *)slotprop = 1; 2929 len = 4; 2930 (void) snprintf(slotprop + len, sizeof (slotprop) - len, "pcie%d", 2931 slot_num); 2932 len += strlen(slotprop + len) + 1; 2933 len += len % 4; 2934 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "slot-names", 2935 (int *)slotprop, len / sizeof (int)); 2936 } 2937